JP2009117409A - Circuit board - Google Patents

Circuit board Download PDF

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Publication number
JP2009117409A
JP2009117409A JP2007285268A JP2007285268A JP2009117409A JP 2009117409 A JP2009117409 A JP 2009117409A JP 2007285268 A JP2007285268 A JP 2007285268A JP 2007285268 A JP2007285268 A JP 2007285268A JP 2009117409 A JP2009117409 A JP 2009117409A
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Prior art keywords
printed wiring
circuit
circuit board
frame
board
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JP2007285268A
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Japanese (ja)
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Yoshihiko Matsushima
義彦 松嶋
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SIIX Corp
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SIIX Corp
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Priority to JP2007285268A priority Critical patent/JP2009117409A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board that effectively controls the leakage of unnecessary electromagnetic waves and control the increase in a footprint in an electronic device even if a circuit scale becomes large. <P>SOLUTION: There is provided a circuit board on which one chip microcomputer 2 and a plurality of circuit components constituting its peripheral circuit are mounted. The circuit board includes a first printed circuit board 29 and a second printed circuit board 30 laminated such that a frame-like member is sandwiched. A circuit wiring layer 37 formed on the first printed circuit board 29 and a circuit wiring layer 38 formed on the second printed circuit board 30 are electrically connected with each other via a plurality of conductor paths 44 laid on the side surface of the frame-like member. A one chip microcomputer 2 is mounted on the first printed circuit board 29 such that the one chip microcomputer 2 is housed in an electromagnetic shielding space surrounded by the first and second printed circuit boards 29 and 30 and the frame-like member. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、ワンチップマイコンならびにその周辺回路を構成する複数の回路部品が実装された回路基板に関し、特に、不要電磁波対策の技術に関する。   The present invention relates to a circuit board on which a plurality of circuit components constituting a one-chip microcomputer and its peripheral circuits are mounted, and more particularly to a technique for countermeasures against unnecessary electromagnetic waves.

樹脂成型技術の向上による回路部品の小型化と回路基板実装技術の急速な進歩により、多種類の回路部品で構成される大規模な回路が単一のプリント基板に実装されている。その一つとして、ワンチップマイコン（ワンチップに成形されたマイクロコンピュータ）ならびにその周辺回路を構成する複数の回路部品が単一のプリント基板に実装され、高度の制御機能を発揮する回路基板がある。   Due to the miniaturization of circuit components by the improvement of resin molding technology and the rapid advancement of circuit board mounting technology, a large-scale circuit composed of many kinds of circuit components is mounted on a single printed circuit board. As one of them, there is a one-chip microcomputer (microcomputer molded into one chip) and a circuit board that exhibits a high degree of control functions by mounting multiple circuit components that make up its peripheral circuits on a single printed circuit board. .

この種の回路基板においては、ワンチップマイコンがスイッチング動作を行なうデジタル半導体デバイスであることから、回路動作時のスイッチング動作により高周波電流が発生し、不要電磁波の発生が避けられないところとなる。このため、デジタル半導体デバイスを含んで構成される制御回路を実装した回路基板を使用する電子機器ではその動作時に電子機器から漏れ出す不要電磁波が他の機器に影響を及ぼすことが懸念される。   In this type of circuit board, since the one-chip microcomputer is a digital semiconductor device that performs a switching operation, a high-frequency current is generated by the switching operation during the circuit operation, and generation of unnecessary electromagnetic waves is unavoidable. For this reason, in an electronic device using a circuit board on which a control circuit including a digital semiconductor device is mounted, there is a concern that unnecessary electromagnetic waves leaking from the electronic device during operation may affect other devices.

また、大規模な制御回路を構成する回路部品の全てを単一のプリント基板に二次元的に配置する実装方式では、制御回路の構成が大規模になると、この制御回路を実装するためのプリント基板面積が増大するため回路基板による電子機器の占有領域の増大が避けられず、電子機器の小型を阻む要因の一つになる。
図９は、ワンチップマイコンとその周辺回路を構成する回路部品を単一のプリント基板に実装した回路基板の実装状態を模式的に示した図であり、プリント配線基板１の一方の主面にワンチップマイコン２、ＭＯＳ形ＩＣ３、４、バイポーラＩＣ５、６、７、トランジスタ８、定電圧ダイオード９、ダイオード１０、抵抗１１、コンデンサ１２等の回路部品を二次元的に配置し、これらの外部端子を回路配線層（図示していない）に接続した構成となっている。 In addition, in a mounting method in which all of the circuit components that make up a large-scale control circuit are two-dimensionally arranged on a single printed circuit board, if the control circuit configuration becomes large, a printout for mounting this control circuit is required. Since the board area increases, an increase in the area occupied by the electronic device due to the circuit board is unavoidable, which is one of the factors that hinder the miniaturization of the electronic device.
FIG. 9 is a diagram schematically showing a mounting state of a circuit board in which circuit components constituting a one-chip microcomputer and its peripheral circuits are mounted on a single printed board, on one main surface of the printed wiring board 1. Circuit components such as one-chip microcomputer 2, MOS type ICs 3, 4, bipolar ICs 5, 6, 7, transistor 8, constant voltage diode 9, diode 10, resistor 11, capacitor 12 are arranged two-dimensionally and their external terminals Is connected to a circuit wiring layer (not shown).

この回路基板では、ワンチップマイコンならびにその周辺回路を構成する全ての回路部品がプリント配線基板１上に配されており、外部に露出している。したがって、この回路基板を用いた電子機器を動作させた場合にワンチップマイコンで発生する高周波電流が発生源となる不要電磁波が電子機器外に放射されることになる。
また、制御回路を構成する全ての回路部品のプリント配線基板１上への配置が二次元的であるため、制御回路の規模が増大して構成部品点数が増加するとプリント配線基板１の面積を大きくしなければならないことになる。 In this circuit board, all circuit components constituting the one-chip microcomputer and its peripheral circuits are arranged on the printed wiring board 1 and exposed to the outside. Therefore, when an electronic device using this circuit board is operated, an unnecessary electromagnetic wave that is generated by a high-frequency current generated by the one-chip microcomputer is emitted outside the electronic device.
In addition, since all the circuit components constituting the control circuit are two-dimensionally arranged on the printed circuit board 1, the area of the printed circuit board 1 increases as the size of the control circuit increases and the number of components increases. Will have to do.

なお電子素子の動作時に発生する電磁波の外部への漏洩を防止するための電子素子封止用パッケージの構造が例えば特許文献１で提案されている。
この電子素子封止用パッケージの構造を簡単に説明すると次の通りである。
図１０に示すように、電子素子封止用パッケージは電子素子の取付け基板１３と一部を破断して示した金属キャップ１４とで構成され、取付け基板１３の周縁に形成されている金属層１５と金属キャップ１４のフランジとを電気溶接して電子素子１６を気密封止している。なお、電子素子１６の電極端子１７と１８は電子素子封止用パッケージの外部に
導出されている。 For example, Patent Document 1 proposes a structure of an electronic element sealing package for preventing leakage of electromagnetic waves generated during operation of the electronic element to the outside.
The structure of the electronic device sealing package will be briefly described as follows.
As shown in FIG. 10, the electronic device sealing package includes an electronic device mounting substrate 13 and a metal cap 14 that is partially cut away, and a metal layer 15 formed on the periphery of the mounting substrate 13. And the flange of the metal cap 14 are electrically welded to hermetically seal the electronic element 16. The electrode terminals 17 and 18 of the electronic element 16 are led out of the electronic element sealing package.

また、二枚のプリント配線基板を所定の間隙を設けて積層配置し、上段と下段のプリント配線基板上に制御回路を構成する全ての電子部品を配置する構成として高密度実装を実現した多層基板が例えば特許文献２で提案されている。
この多層基板の構造を簡単に説明すると次の通りである。
図１１に示すように、二枚の電子部品搭載用基板１９と２０が枠体２１により所定の離間距離を付与されて積層され、夫々の電子部品搭載用基板には電子部品２２が半田ボール２３により固着されている。この多層基板では制御回路を形成するための回路接続が半田ボール２３、導電パターン層２４、スルーホール２５を利用して実現され、枠体２１と電子部品搭載用基板１９および２０とは導電パターン層の一部２６と半田ボール２７を利用して機械的に固着されている。なお、電子部品２２と電子部品搭載用基板１９ならびに２０との間にできる隙間は樹脂２８で充填されている。
特開２０００−４９２４７号公報 特開２００１−２１０９５４号公報 In addition, a multilayer board that realizes high-density mounting as a configuration in which two printed wiring boards are stacked with a predetermined gap and all electronic components that make up the control circuit are placed on the upper and lower printed wiring boards. Is proposed in Patent Document 2, for example.
The structure of this multilayer substrate will be briefly described as follows.
As shown in FIG. 11, two electronic component mounting boards 19 and 20 are stacked with a predetermined separation distance by a frame body 21, and an electronic component 22 is connected to a solder ball 23 on each electronic component mounting board. It is fixed by. In this multilayer substrate, circuit connection for forming a control circuit is realized using the solder balls 23, the conductive pattern layer 24, and the through holes 25. The frame body 21 and the electronic component mounting substrates 19 and 20 are connected to the conductive pattern layer. These parts 26 and the solder balls 27 are used for mechanical fixation. A gap formed between the electronic component 22 and the electronic component mounting substrates 19 and 20 is filled with a resin 28.
JP 2000-49247 A Japanese Patent Laid-Open No. 2001-210554

しかしながら、特許文献１で提案されている電子素子封止用パッケージは専用の取付け基板１３と金属キャップ１４を必要とするばかりでなく、単一の電子素子を封止した電子素子封止構体を実現するものであるため、回路基板実装に際してはこの電子素子封止構体が取付けられるプリント基板に挿入用の凹所を設けるなどの対策を施さなければならない。   However, the electronic device sealing package proposed in Patent Document 1 not only requires a dedicated mounting substrate 13 and a metal cap 14, but also realizes an electronic device sealing structure in which a single electronic device is sealed. Therefore, when mounting the circuit board, it is necessary to take measures such as providing a recess for insertion in the printed circuit board to which the electronic element sealing structure is attached.

また特許文献２で提案されている多層基板では電子部品が不要電磁波の発生源となり得ることについては言及されておらず、特に不要電磁波の漏洩を抑制するための対策は採られていない。
本発明は、上記の課題を解決するものであり、回路動作時に発生する不要電磁波の漏洩を効果的に抑制することができ、さらに、制御回路が大規模になっても電子機器における占拠領域の増大を抑制することができる回路基板を提供することを目的とする。 The multilayer substrate proposed in Patent Document 2 does not mention that an electronic component can be a source of unnecessary electromagnetic waves, and does not take measures especially for suppressing leakage of unnecessary electromagnetic waves.
The present invention solves the above-described problems, can effectively suppress the leakage of unnecessary electromagnetic waves generated during circuit operation, and further, the occupation area of an electronic device can be reduced even when the control circuit becomes large-scale. It aims at providing the circuit board which can suppress an increase.

本発明に係る回路基板は、ワンチップマイコンならびにその周辺回路を構成する複数の回路部品が実装された回路基板であって、第一のプリント配線基板と、前記第一のプリント配線基板上に枠状に成形された枠状部材を挟んで積み重ねられた第二のプリント配線基板とを備え、前記第一および第二のプリント配線基板はそれぞれ回路配線層を有し、これらの回路配線層は前記枠状部材の内部または側面に敷設された複数の導電経路を介して電気的に相互接続されており、前記ワンチップマイコンと前記複数の回路部品のうちの一部の回路部品とは、前記第一および第二のプリント配線基板ならびに前記枠状部材で包囲される電磁遮蔽空間に収容されるように前記第一および第二のプリント配線基板の一方または両方に実装され、前記複数の回路部品のうちの残余の回路部品は、外部に露呈するように前記第二のプリント配線基板に実装されている。   A circuit board according to the present invention is a circuit board on which a plurality of circuit components constituting a one-chip microcomputer and its peripheral circuits are mounted, and includes a first printed wiring board and a frame on the first printed wiring board. And a second printed wiring board stacked with a frame-shaped member formed in a shape, the first and second printed wiring boards each having a circuit wiring layer, and these circuit wiring layers are The one-chip microcomputer and a part of the plurality of circuit components are electrically connected to each other through a plurality of conductive paths laid inside or on a side surface of the frame-shaped member. Mounted on one or both of the first and second printed wiring boards and the first and second printed wiring boards so as to be accommodated in the electromagnetic shielding space surrounded by the frame-shaped member and the first and second printed wiring boards, Road remaining circuit components of the component is mounted on the second printed circuit board so as to be exposed to the outside.

上記構成によれば、第一および第二のプリント配線基板ならびに枠状部材で包囲される空間は、第一および第二のプリント配線基板がそれぞれ有する回路配線層ならびに枠状部材の内部または表面に敷設された複数の導電経路により電磁遮蔽空間として機能する。ワンチップマイコンはそのような電磁遮蔽空間に収容されているので、回路動作時に不要電磁波を発生させたとしても、その漏洩を効果的に抑制することができる。さらに、回路部品の実装が三次元的になるため、制御回路が大規模になっても回路基板による電子機器における占拠領域の増大を抑制することができる。   According to the above configuration, the space surrounded by the first and second printed wiring boards and the frame-like member is inside or on the surface of the circuit wiring layer and the frame-like member that the first and second printed wiring boards respectively have It functions as an electromagnetic shielding space by a plurality of installed conductive paths. Since the one-chip microcomputer is accommodated in such an electromagnetic shielding space, leakage can be effectively suppressed even if unnecessary electromagnetic waves are generated during circuit operation. Furthermore, since the circuit components are mounted three-dimensionally, an increase in the occupied area of the electronic device by the circuit board can be suppressed even if the control circuit becomes large.

また回路部品にＭＯＳ形ＬＳＩが含まれている場合には、ＭＯＳ型集積素子も電磁遮蔽空間に収容することとすることで、ＭＯＳ型集積素子に起因する不要電磁波の漏洩を効果的に抑制することができ、不要電磁波の漏洩効果を一層高めることができる。   In addition, when a MOS type LSI is included in the circuit component, the leakage of unnecessary electromagnetic waves caused by the MOS type integrated element is effectively suppressed by accommodating the MOS type integrated element in the electromagnetic shielding space. This can further enhance the leakage effect of unnecessary electromagnetic waves.

以下、本発明の実施の形態について図面を参照して説明する。
（実施の形態１）
図１乃至図４は、本発明の回路基板の構造を説明するための一実施形態を示す図であり、図１および図２は、図９で示したのと同一タイプで、かつ、同数の回路部品を実装した第一および第二のプリント配線基板の平面図、図３は二枚のプリント配線基板を積層するための枠状部材の平面図、図４は二枚のプリント配線基板と枠状部材とで構成された本発明の回路基板を図１および図２のＡ−Ａ線に沿って切断して示した断面図である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIGS. 1 to 4 are views showing an embodiment for explaining the structure of the circuit board of the present invention. FIGS. 1 and 2 are the same type and the same number as those shown in FIG. FIG. 3 is a plan view of a frame-like member for laminating two printed wiring boards, and FIG. 4 is a diagram showing two printed wiring boards and a frame. It is sectional drawing which cut | disconnected and showed the circuit board of this invention comprised by the shaped member along the AA line of FIG. 1 and FIG.

本実施形態の回路基板を形成するに際しては、図１に示された第一のプリント配線基板２９とこれと寸法形状が同一の図２に示された第二のプリント配線基板とに回路部品を二分して実装するが、実装に際しては第一のプリント配線基板２９に少なくともワンチップマイコン２およびＭＯＳ形ＩＣ３、４を実装することとし、第二のプリント配線基板３０にはワンチップマイコン２およびＭＯＳ形ＩＣ３、４を実装しないこととする。具体的には、第一のプリント配線基板２９には、ワンチップマイコン２、ＭＯＳ形ＩＣ３、４、トランジスタ８、ダイオード１０、抵抗１１、コンデンサ１２が実装されており、例えば当該回路基板が組み込まれる電子機器を制御する制御回路が構成されている。また第二のプリント配線基板３０には、バイポーラＩＣ５、６、７、定電圧ダイオード９、抵抗１１が実装されており、例えば電源回路が構成されている。   When forming the circuit board of this embodiment, circuit components are placed on the first printed wiring board 29 shown in FIG. 1 and the second printed wiring board shown in FIG. Although mounting is divided in two, at the time of mounting, at least the one-chip microcomputer 2 and the MOS type ICs 3 and 4 are mounted on the first printed wiring board 29, and the one-chip microcomputer 2 and the MOS are mounted on the second printed wiring board 30. The ICs 3 and 4 are not mounted. Specifically, the first printed wiring board 29 is mounted with the one-chip microcomputer 2, the MOS ICs 3, 4, the transistor 8, the diode 10, the resistor 11, and the capacitor 12, for example, the circuit board is incorporated. A control circuit for controlling the electronic device is configured. On the second printed wiring board 30, bipolar ICs 5, 6, and 7, a constant voltage diode 9, and a resistor 11 are mounted. For example, a power supply circuit is configured.

なお、第一のプリント配線基板２９と第二のプリント配線基板３０の周縁部にはそれぞれの回路配線層（図示せず）の必要部分に繋がるとともに第一のプリント配線基板２９および第二のプリント配線基板３０のそれぞれの回路配線層の要部を相互接続するための接続領域３１が形成されている。
図３は、二枚のプリント配線板とともに電磁波遮蔽空間を形成する枠状部材を例示する図であり、枠状部材３２は複数枚の口字形プリプレグを積層して所定の厚みとした枠基材３３の内周面に銅めっき層３４を被着した構成となっているため、枠状部材３２には空所３５が存在することになる。 The peripheral portions of the first printed wiring board 29 and the second printed wiring board 30 are connected to necessary portions of the respective circuit wiring layers (not shown), and the first printed wiring board 29 and the second printed wiring board 30 are connected. A connection region 31 for interconnecting the main parts of the respective circuit wiring layers of the wiring board 30 is formed.
FIG. 3 is a diagram illustrating a frame-shaped member that forms an electromagnetic wave shielding space together with two printed wiring boards, and the frame-shaped member 32 is a frame base material having a predetermined thickness by stacking a plurality of mouth-shaped prepregs. Since the copper plating layer 34 is attached to the inner peripheral surface 33, a void 35 exists in the frame-shaped member 32.

図４は、以上説明した第一のプリント配線基板２９と第二のプリント配線基板３０と枠状部材３２を一体化して形成した本発明の一実施形態に係る回路基板の構造を説明するための図であり、図１のＡ−Ａ線に沿った断面図である。
第一のプリント配線基板２９の上面２９ａには回路配線層３６が形成され回路配線層３６の一部であるランドに半田４０あるいはボールバンプ４１を介してワンチップマイコン２およびＭＯＳ形ＩＣ３、４を含む回路部品が接続されている。また第一のプリント配線基板２９の下面２９ｂには回路配線層３７が形成され回路配線層３７の一部であるランドに外部接続用の突起電極４３が形成されている。さらに第一のプリント配線基板２９は多層構造になっており内部に銅箔層４５が形成されている。 FIG. 4 is a diagram for explaining the structure of a circuit board according to an embodiment of the present invention in which the first printed wiring board 29, the second printed wiring board 30, and the frame-shaped member 32 described above are integrally formed. It is a figure and is sectional drawing along the AA of FIG.
A circuit wiring layer 36 is formed on the upper surface 29 a of the first printed wiring board 29, and the one-chip microcomputer 2 and the MOS type ICs 3 and 4 are connected to lands that are a part of the circuit wiring layer 36 via solder 40 or ball bumps 41. Including circuit components are connected. A circuit wiring layer 37 is formed on the lower surface 29 b of the first printed wiring board 29, and protruding electrodes 43 for external connection are formed on lands that are part of the circuit wiring layer 37. Further, the first printed wiring board 29 has a multilayer structure, and a copper foil layer 45 is formed therein.

一方、第二のプリント配線基板３０の上面３０ａには回路配線層３８が形成され回路配線層３８の一部であるランドに半田４０を介してバイポーラＩＣ６、定電圧ダイオード９など第一のプリント配線基板２９に実装されない回路部品が接続されている。また第二のプリント配線基板３０の下面３０ｂには銅箔層３９が形成されている。なお第二のプリント配線基板３０に実装する回路部品として電力損失の大きな回路部品を選定すれば、回路動作時に発生する熱の放散を効果的に行なわせることができる。   On the other hand, a circuit wiring layer 38 is formed on the upper surface 30a of the second printed wiring board 30, and a first printed wiring such as a bipolar IC 6 and a constant voltage diode 9 is connected to a land which is a part of the circuit wiring layer 38 via a solder 40. Circuit components that are not mounted on the substrate 29 are connected. A copper foil layer 39 is formed on the lower surface 30 b of the second printed wiring board 30. If a circuit component having a large power loss is selected as a circuit component to be mounted on the second printed wiring board 30, it is possible to effectively dissipate heat generated during circuit operation.

第一のプリント配線基板２９に形成された回路配線層３７および第二のプリント配線基板３０に形成された回路配線層３８は枠基材３３の側面に形成された金めっき層４４により相互に接続されている。また第一のプリント配線基板２９に形成された回路配線層３６、３７の間は、第一のプリント配線基板２９に設けられたスルーホールにより相互に接続されている。なおスルーホールは、銅箔層４５から絶縁するために、銅箔層４５を一部除去した領域に形成される。   The circuit wiring layer 37 formed on the first printed wiring board 29 and the circuit wiring layer 38 formed on the second printed wiring board 30 are connected to each other by a gold plating layer 44 formed on the side surface of the frame substrate 33. Has been. The circuit wiring layers 36 and 37 formed on the first printed wiring board 29 are connected to each other by through holes provided on the first printed wiring board 29. The through-hole is formed in a region where the copper foil layer 45 is partially removed in order to insulate from the copper foil layer 45.

なお第一および第二のプリント配線基板２９、３０は、耐熱性ガラス基材両面銅張り積層板からなる。第一および第二のプリント配線基板２９、３０に形成された回路配線層３６、３７、３８は、耐熱性ガラス基材に被着された銅箔層を所定の配線パターンでエッチングすることにより形成される。
上述のとおりワンチップマイコン２およびＭＯＳ形ＩＣ３、４は、空所３５に収容されることになる。この空所３５は、枠基材３３に形成された銅めっき層３４、第一のプリント配線基板２９に形成された銅箔層４５および第二のプリント配線基板３０に形成された銅箔層３９により包囲されて電磁波遮蔽空間として機能する。したがって、回路動作時に不要電磁波を発生するおそれがあるデジタル半導体デバイスを含んで構成される制御回路を実装した場合であっても、デジタル半導体デバイスの実装がプリント配線基板の電磁遮蔽空間内においてなされるため、制御回路の動作時に電子機器から漏れ出す不要電磁波が他の機器に影響を及ぼすことを防止することができる。 The first and second printed wiring boards 29 and 30 are made of a heat-resistant glass base double-sided copper-clad laminate. The circuit wiring layers 36, 37, 38 formed on the first and second printed wiring boards 29, 30 are formed by etching a copper foil layer applied to a heat-resistant glass substrate with a predetermined wiring pattern. Is done.
As described above, the one-chip microcomputer 2 and the MOS ICs 3 and 4 are accommodated in the space 35. The void 35 includes a copper plating layer 34 formed on the frame base material 33, a copper foil layer 45 formed on the first printed wiring board 29, and a copper foil layer 39 formed on the second printed wiring board 30. It is surrounded by and functions as an electromagnetic wave shielding space. Therefore, even when a control circuit configured to include a digital semiconductor device that may generate unnecessary electromagnetic waves during circuit operation is mounted, the digital semiconductor device is mounted in the electromagnetic shielding space of the printed wiring board. Therefore, it is possible to prevent unnecessary electromagnetic waves leaking from the electronic device during the operation of the control circuit from affecting other devices.

なお回路配線層３６、３７、３８を形成するにあたり、銅箔層のうちの配線部分のみを残して非配線部分を全てエッチングで除去するというのではなく、非配線部分も極力残存させることとするのが望ましい。そうすることで非配線部分としての銅箔層が隣接する配線間に島状に残存することとなり、電磁遮蔽効果を一層高めることができる。
なお上記の実施形態では第一および第二のプリント配線基板と枠状部材とを別個の構成として説明したが、一方のプリント配線基板に対して複数枚の口字形プリプレグを積層貼付して枠上部材相当物とする構成とすることもできる。
（実施の形態２）
図５乃至図８は、本発明の回路基板の構造を説明するための一実施形態を示す図であり、図５および図６は、図９で示したのと同一タイプで、かつ、同数の回路部品を実装した第一および第二のプリント配線基板の平面図、図７は二枚のプリント配線基板を積層するための枠状部材の平面図、図８は二枚のプリント配線基板と枠状部材とで構成された本発明の回路基板を図５および図６のＡ−Ａ線に沿って切断して示した断面図である。 In forming the circuit wiring layers 36, 37, and 38, the non-wiring portion is not removed by etching, leaving only the wiring portion of the copper foil layer, but the non-wiring portion is left as much as possible. Is desirable. By doing so, the copper foil layer as a non-wiring portion remains in an island shape between adjacent wirings, and the electromagnetic shielding effect can be further enhanced.
In the above embodiment, the first and second printed wiring boards and the frame-like member have been described as separate structures. However, a plurality of square-shaped prepregs are laminated on one printed wiring board and attached to the frame. It can also be set as the member equivalent.
(Embodiment 2)
FIGS. 5 to 8 are views showing an embodiment for explaining the structure of the circuit board of the present invention. FIGS. 5 and 6 are the same type and the same number as those shown in FIG. FIG. 7 is a plan view of a frame-like member for laminating two printed wiring boards, and FIG. 8 is a diagram showing two printed wiring boards and a frame. It is sectional drawing which cut | disconnected and showed the circuit board of this invention comprised by the shaped member along the AA line of FIG. 5 and FIG.

本実施の形態では、第一および第二のプリント配線基板２９、３０の周縁部の全周にわたりそれぞれの接続領域３１が形成され、それに伴い接続領域３１間を電気的に接続する導電経路４６が枠基材３３の全周にわたり形成されている。また枠基材３３の内周面には銅めっき層３４が形成されていない。
このように銅めっき層３４を形成しなくても、導電経路４６を枠基材３３の全周にわたり満遍なく形成することで電磁遮蔽効果を発揮させることができる。したがって回路動作時に不要電磁波を発生するおそれがあるデジタル半導体デバイスを含んで構成される制御回路を実装した場合であっても、デジタル半導体デバイスの実装がプリント配線基板の電磁遮蔽空間内においてなされるため、制御回路の動作時に電子機器から漏れ出す不要電磁波が他の機器に影響を及ぼすことを防止することができる。 In the present embodiment, the connection regions 31 are formed over the entire circumference of the peripheral edge portions of the first and second printed wiring boards 29 and 30, and accordingly, the conductive paths 46 that electrically connect the connection regions 31 are formed. It is formed over the entire circumference of the frame base material 33. Further, the copper plating layer 34 is not formed on the inner peripheral surface of the frame base material 33.
Thus, even if the copper plating layer 34 is not formed, the electromagnetic shielding effect can be exhibited by forming the conductive path 46 uniformly over the entire circumference of the frame base material 33. Therefore, even when a control circuit including a digital semiconductor device that may generate unwanted electromagnetic waves during circuit operation is mounted, the digital semiconductor device is mounted in the electromagnetic shielding space of the printed wiring board. It is possible to prevent unnecessary electromagnetic waves leaking from the electronic device during operation of the control circuit from affecting other devices.

また本実施の形態に示すように導電経路４６を枠基材３３の内部に形成することとしてもよい。また本実施の形態に示すように第一および第二のプリント配線基板２９、３０に形成された銅箔層４５、３９に配線を形成し、これらを回路配線層として利用してもよい。
なお第二のプリント配線基板３０に形成された銅箔層３９を回路配線層として利用する場合には、空所３５に収容されるべきワンチップマイコン２等を第二のプリント配線基板３０の銅箔層３９に実装することとしてもよい。 Further, the conductive path 46 may be formed inside the frame base material 33 as shown in the present embodiment. Further, as shown in the present embodiment, wiring may be formed on the copper foil layers 45 and 39 formed on the first and second printed wiring boards 29 and 30, and these may be used as circuit wiring layers.
When the copper foil layer 39 formed on the second printed wiring board 30 is used as a circuit wiring layer, the one-chip microcomputer 2 or the like to be accommodated in the space 35 is replaced with the copper of the second printed wiring board 30. It may be mounted on the foil layer 39.

また銅箔層４５、３９および銅めっき層３４は、電磁波遮蔽効果を発揮することができれば銅に限らない。他の金属を用いても構わない。また箔ではなくメッシュ状のものとしてもよい。メッシュの場合には、ワンチップマイコン２から放射される不要電磁波の波長に応じて適切に開口部のサイズを設計すれば、箔と同等の効果を得ることができる。   The copper foil layers 45 and 39 and the copper plating layer 34 are not limited to copper as long as they can exhibit an electromagnetic wave shielding effect. Other metals may be used. Moreover, it is good also as a mesh form instead of foil. In the case of the mesh, if the size of the opening is appropriately designed according to the wavelength of the unnecessary electromagnetic wave radiated from the one-chip microcomputer 2, an effect equivalent to that of the foil can be obtained.

本発明は、ワンチップマイコンならびにその周辺回路を構成する回路部品が実装された回路基板に広く適用することが可能であり、本発明の適用により不要電磁波の漏洩を抑制した電子機器を実現することができる。   The present invention can be widely applied to a circuit board on which circuit components constituting a one-chip microcomputer and its peripheral circuits are mounted. By applying the present invention, an electronic device that suppresses leakage of unnecessary electromagnetic waves is realized. Can do.

本発明の一実施形態に係る回路基板を構成する第一のプリント配線基板の平面図The top view of the 1st printed wiring board which comprises the circuit board which concerns on one Embodiment of this invention. 本発明の一実施形態に係る回路基板を構成する第二のプリント配線基板の平面図The top view of the 2nd printed wiring board which comprises the circuit board which concerns on one Embodiment of this invention. 第一および第二のプリント配線基板の間に配設されて二枚のプリント配線基板を積層するための枠状部材の平面図The top view of the frame-shaped member arrange | positioned between the 1st and 2nd printed wiring boards, and laminating | stacking two printed wiring boards 二枚のプリント配線基板と枠状部材とで構成した本発明の回路基板を図１のＡ−Ａ線に沿って切断して示した断面図Sectional drawing which cut and showed the circuit board of this invention comprised by the two printed wiring boards and the frame-shaped member along the AA line of FIG. 本発明の一実施形態に係る回路基板を構成する第一のプリント配線基板の平面図The top view of the 1st printed wiring board which comprises the circuit board which concerns on one Embodiment of this invention. 本発明の一実施形態に係る回路基板を構成する第二のプリント配線基板の平面図The top view of the 2nd printed wiring board which comprises the circuit board which concerns on one Embodiment of this invention. 第一および第二のプリント配線基板の間に配設されて二枚のプリント配線基板を積層するための枠状部材の平面図The top view of the frame-shaped member arrange | positioned between the 1st and 2nd printed wiring boards, and laminating | stacking two printed wiring boards 二枚のプリント配線基板と枠状部材とで構成した本発明の回路基板を図５のＡ−Ａ線に沿って切断して示した断面図Sectional drawing which cut and showed the circuit board of this invention comprised by the two printed wiring boards and the frame-shaped member along the AA line of FIG. ワンチップマイコンとその周辺回路を構成する回路部品を単一のプリント基板に実装した回路基板の実装状態を模式的に示した図Schematic diagram showing the mounting state of the circuit board in which the circuit components that make up the one-chip microcomputer and its peripheral circuits are mounted on a single printed circuit board 電子素子の動作時に発生する電磁波の外部への漏洩を防止するための電子素子封止用パッケージの構造を示す要部断面図Cross-sectional view of the main part showing the structure of an electronic device sealing package for preventing leakage of electromagnetic waves generated during operation of the electronic device to the outside 二枚のプリント配線基板を所定の間隙を設けて積層配置し、上段と下段のプリント配線基板上に制御回路を構成する全ての電子部品を配置する構成として高密度実装を実現した多層基板の構造を示す断面図Multi-layer board structure that achieves high-density mounting as a configuration in which two printed wiring boards are stacked with a predetermined gap and all electronic components that make up the control circuit are placed on the upper and lower printed wiring boards Cross section showing

符号の説明Explanation of symbols

１、２９、３０ プリント配線基板
２ ワンチップマイコン
３、４ ＭＯＳ形ＩＣ
５、６、７ バイポーラＩＣ
８ トランジスタ
９ 定電圧ダイオード
１０ ダイオード
１１ 抵抗
１２ コンデンサ
１３ 取付け基板
１４ 金属キャップ
１５ 金属層
１６ 電子素子
１７、１８ 電極端子
１９、２０ 電子部品搭載用基板
２１ 枠体
２２ 電子部品
２３ 半田ボール
２４、２６ 導電パターン層
２５ スルーホール
２７ 半田ボール
２８ 樹脂
３１ 接続領域
３２ 枠状部材
３３ 枠基材
３４ 銅めっき層
３５ 空所
３６、３７、３８ 回路配線層
３９、４５ 銅箔層
４０ 半田
４１ ボールバンプ
４３ 突起電極
４４ 金めっき層
４６ 導電経路 1, 29, 30 Printed wiring board 2 One-chip microcomputer 3, 4 MOS type IC
5, 6, 7 Bipolar IC
8 Transistor 9 Constant Voltage Diode 10 Diode 11 Resistance 12 Capacitor 13 Mounting Board 14 Metal Cap 15 Metal Layer 16 Electronic Element 17, 18 Electrode Terminal 19, 20 Electronic Component Mounting Board 21 Frame 22 Electronic Component 23 Solder Ball 24, 26 Conductivity Pattern layer 25 Through hole 27 Solder ball 28 Resin 31 Connection region 32 Frame member 33 Frame base material 34 Copper plating layer 35 Space 36, 37, 38 Circuit wiring layer 39, 45 Copper foil layer 40 Solder 41 Ball bump 43 Projection electrode 44 Gold plating layer 46 Conductive path

Claims (6)

ワンチップマイコンならびにその周辺回路を構成する複数の回路部品が実装された回路基板であって、
第一のプリント配線基板と、前記第一のプリント配線基板上に枠状に成形された枠状部材を挟んで積み重ねられた第二のプリント配線基板とを備え、
前記第一および第二のプリント配線基板はそれぞれ回路配線層を有し、これらの回路配線層は前記枠状部材の内部または側面に敷設された複数の導電経路を介して電気的に相互接続されており、
前記ワンチップマイコンと前記複数の回路部品のうちの一部の回路部品とは、前記第一および第二のプリント配線基板ならびに前記枠状部材で包囲される電磁遮蔽空間に収容されるように前記第一および第二のプリント配線基板の一方または両方に実装され、前記複数の回路部品のうちの残余の回路部品は、外部に露呈するように前記第二のプリント配線基板に実装されていること
を特徴とする回路基板。 A circuit board on which a plurality of circuit components constituting a one-chip microcomputer and its peripheral circuits are mounted,
A first printed wiring board, and a second printed wiring board stacked on both sides of a frame-shaped member formed in a frame shape on the first printed wiring board,
Each of the first and second printed wiring boards has a circuit wiring layer, and these circuit wiring layers are electrically interconnected through a plurality of conductive paths laid inside or on the side surface of the frame-shaped member. And
The one-chip microcomputer and a part of the plurality of circuit components are housed in the electromagnetic shielding space surrounded by the first and second printed wiring boards and the frame member. It is mounted on one or both of the first and second printed wiring boards, and the remaining circuit components of the plurality of circuit components are mounted on the second printed wiring board so as to be exposed to the outside. A circuit board characterized by. 前記複数の回路部品には一または複数のＭＯＳ形集積素子が含まれており、一または複数のＭＯＳ型集積素子はいずれも前記第一および第二のプリント配線基板ならびに前記枠状部材で包囲される電磁遮蔽空間に収容されていること
を特徴とする請求項１に記載の回路基板。 The plurality of circuit components include one or more MOS type integrated elements, and each of the one or more MOS type integrated elements is surrounded by the first and second printed wiring boards and the frame-like member. The circuit board according to claim 1, wherein the circuit board is housed in an electromagnetic shielding space. 前記第一および第二のプリント配線基板は、いずれも耐熱性ガラス基材両面銅張り積層板からなること
を特徴とする請求項１に記載の回路基板。 The circuit board according to claim 1, wherein each of the first and second printed wiring boards is made of a heat-resistant glass-based double-sided copper-clad laminate. 前記複数の導電経路はいずれも金めっき層からなること
を特徴とする請求項１に記載の回路基板。 The circuit board according to claim 1, wherein each of the plurality of conductive paths is made of a gold plating layer. 前記枠状部材の内周面には金属層が形成されていること
を特徴とする請求項１に記載の回路基板。 The circuit board according to claim 1, wherein a metal layer is formed on an inner peripheral surface of the frame-shaped member. 前記第一および第二のプリント配線基板の一方または両方には、回路配線層とは別に金属層が形成されていること
を特徴とする請求項１に記載の回路基板。 The circuit board according to claim 1, wherein a metal layer is formed separately from the circuit wiring layer on one or both of the first and second printed wiring boards.
JP2007285268A 2007-11-01 2007-11-01 Circuit board Pending JP2009117409A (en)

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