TW201007914A - Three-dimensional conducting structure and method of fabricating the same - Google Patents

Three-dimensional conducting structure and method of fabricating the same Download PDF

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Publication number
TW201007914A
TW201007914A TW097129949A TW97129949A TW201007914A TW 201007914 A TW201007914 A TW 201007914A TW 097129949 A TW097129949 A TW 097129949A TW 97129949 A TW97129949 A TW 97129949A TW 201007914 A TW201007914 A TW 201007914A
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Taiwan
Prior art keywords
substrate
pad
hole
conductor
active surface
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TW097129949A
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Chinese (zh)
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TWI387087B (en
Inventor
Hsiang-Hung Chang
Shu-Ming Chang
Tzu-Ying Kuo
Yuan-Chang Lee
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Ind Tech Res Inst
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Priority to TW097129949A priority Critical patent/TWI387087B/en
Priority to US12/500,780 priority patent/US8193632B2/en
Publication of TW201007914A publication Critical patent/TW201007914A/en
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Publication of TWI387087B publication Critical patent/TWI387087B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

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Abstract

A three-dimensional conducting structure is applied to a package. The three-dimensional conducting structure comprises a substrate, a first redistributed conductor, a second redistributed conductor, and an insulator. The substrate has an active surface, a passive surface opposite to the active one, a pad on the active surface, and through hole. The first redistributed conductor comprises a projecting portion and a receiving portion. The projecting portion is projected from the active surface of the substrate and electrically connected to the pad. The receiving portion is outside the active surface and in contact with the projecting portion. The projecting portion and the receiving portion constitute a recess, which communicates with the through hole. The second redistributed conductor is positioned within the through hole and the recess, in contact with the receiving portion, and extended toward the passive surface along the through hole. The insulator is filled between the second redistributed conductor and the substrate and between the second redistributed conductor and the projecting portion.

Description

201007914 i W4052PA 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種導通結構及其製造方法’且 特別是有關於一種立體導通結構及其製造方法。 【先前技術】201007914 i W4052PA IX. Description of the Invention: [Technical Field] The present invention relates to a conductive structure and a method of fabricating the same, and more particularly to a three-dimensional conductive structure and a method of fabricating the same. [Prior Art]

廣泛來說，系統構裝（System in Package, SiP) 涵括了早期的多晶片模組（Multi-chip Module，MCM) 技術、多晶片封裝（Multi-chip Package, MCP)技術、 晶片堆疊（Stack die)、PoP (Package on Package)、 PiP (Package in Package)以及將主/被動元件内埋於 基板（Embedded Substrate)等技術。以結構外觀來 說’ MCM屬於二維的2D構裝，而MCP、晶片堆疊、 PoP、PiP等則屬於立體的3D構裝；由於3D構裝更 能符合小型化、高效能等需求，因而近年來備受業界 青睞。 若進一步就互連技術（Interconnection)來看，傳 統的2D或3D構裝多以打線接合(wire bonding)為 主，少部分採用覆晶技術（Flip Chip)，或是結合兩者。 以晶片堆疊（Stack die)為例，上層晶片仍須藉由打線 接合技術與其他晶片互連，當堆疊的晶片數目增加 時’越上層的晶片所需的銲線長度則越長，也因此影 響了f個封裝系統的效能；再者，為了保留打線空 間，晶片與晶片之間需適度的***隔板，也會造成封Broadly speaking, System in Package (SiP) covers early Multi-chip Module (MCM) technology, Multi-chip Package (MCP) technology, and wafer stacking (Stack). Die), PoP (Package on Package), PiP (Package in Package), and techniques for embedding the active/passive component in a substrate (Embedded Substrate). In terms of structural appearance, 'MCM belongs to the two-dimensional 2D structure, while MCP, wafer stacking, PoP, PiP, etc. belong to the three-dimensional 3D structure; since the 3D structure can meet the requirements of miniaturization and high efficiency, it has been in recent years. Come to be favored by the industry. Further, in terms of interconnection, the conventional 2D or 3D architecture is mostly based on wire bonding, a small part of Flip Chip, or a combination of both. Taking a stack die as an example, the upper wafer must still be interconnected with other wafers by wire bonding technology. When the number of stacked wafers increases, the longer the wire length required for the upper wafer, the greater the impact. The performance of f package systems; in addition, in order to preserve the wire space, a proper insertion of the spacer between the wafer and the wafer will also result in a seal.

TW4682PA 201007914TW4682PA 201007914

IW4682PA 裝體積增加。 近年來，業界所研發的新互連技術—矽通道技 術(Through Silicon Via，TSV)誕生。請參照第 1A〜 1F圖，其繪示矽通道導體結構之製造方涑的示意流 程圖。首先，如第1A圖所示’提供晶片1 〇，晶片的 正面10a具有增厚的銲接墊12。接著，如第1B圖所 示，施行第一次雷射鑽孔，從晶片背面i 以雷射鑽 參 孔’並停止在焊接墊12表面’形成開孔14。由於必 須從晶片背面10b鑽孔，也容易產生對位不準確的問 題。另一方面，由於雷射功率不穩定，加Λ對於矽（晶 片的材料）與金屬（焊接墊的材料)選擇比不高，導致在 此步驟中雷射很容易打穿焊接墊。雖然這個問題可以 藉由將焊接墊12增厚的方式解決，但是增厚焊接塾 12無疑地會增加製造過程中金錢與時間的成本。 請參照第1C圖，將絕緣材料16填八開孔14。 φ 接著，施行第一次雷射鐵孔，如第1 D圖戶斤示，在絕 緣材料16内鑽孔並同樣停止在焊接墊12表面，形成 通道17。之後，如第1Ε圖所示，將導電材料18填 入通道17内。最後，如第1F圖所示，蔣晶片1〇與 另一晶片20黏合在一起，晶片1〇之焊换墊12係透 過導電材料18與另一晶片20之焊接墊以電性連接。The IW4682PA has an increased volume. In recent years, the new interconnect technology developed by the industry, the Through Silicon Via (TSV), was born. Referring to Figures 1A to 1F, there is shown a schematic flow chart of the manufacturing process of the channel conductor structure. First, as shown in Fig. 1A, the wafer 1 is provided, and the front surface 10a of the wafer has a thickened solder pad 12. Next, as shown in Fig. 1B, the first laser drilling is performed, and the opening 14 is formed by laser drilling the hole ' from the back side of the wafer and stopping on the surface of the solder pad 12. Since it is necessary to drill holes from the back surface 10b of the wafer, it is easy to cause an inaccurate alignment problem. On the other hand, due to the unstable laser power, the twisting ratio is not high for the choice of the germanium (the material of the wafer) and the metal (the material of the soldering pad), so that the laser can easily penetrate the soldering pad in this step. Although this problem can be solved by thickening the solder pads 12, thickening the solder bumps 12 undoubtedly increases the cost of money and time in the manufacturing process. Referring to FIG. 1C, the insulating material 16 is filled with eight openings 14. φ Next, the first laser iron hole is applied, as shown in Fig. 1D, and the hole 17 is drilled in the insulating material 16 and also stopped on the surface of the solder pad 12 to form the channel 17. Thereafter, as shown in Fig. 1, the conductive material 18 is filled into the channel 17. Finally, as shown in Fig. 1F, the wafer 1 is bonded to the other wafer 20, and the pad 12 of the wafer is electrically connected to the pad of the other wafer 20 through the conductive material 18.

TW4682PA 然而，在第二次雷射鑽孔以形成通道17時，非 常容易擴孔而導致漏電流問題。當以雷射鑽孔至烊 墊12時’金屬材質（i.e·焊接塾12)會反射或折射雷 7 201007914TW4682PA However, when the second laser is drilled to form the channel 17, it is very easy to ream the hole and cause leakage current problems. When drilling with a laser to the mat 12, the metal material (i.e. soldering weir 12) will reflect or refract the thunder 7 201007914

i ww^PA 射光，鄰近焊接墊12的絕緣材料16也同時會被雷射 燒掉，導致通道17末端孔徑較大甚至暴露出晶片 1〇°當通道17内重新填入導電材料18,將使得導電 材料18接觸到晶片10,造成原本必須絕緣的導電材 料18與晶片1〇產生電性連接，也就是所謂的漏電流 問題。 【發明内容】 w 本發明係有關於一種立體導通結構及其製造方 法。 本發明提出一種立體導通結構，係應用於封裝 件。立體導通結構包括基板、第一重佈導體、第二重 佈導體以及絕緣材料。基板具有主動表面及與其相對 之被動表面’基板具有焊接墊以及貫孔，焊接墊位於 主動表面上。第一重佈導體包括***部與承接部，隆 φ 起部由基板之主動表面向外***，並電性連接於焊接 塾’承接部位於主動表面之外侧，並連接於***部， 其中***部與承接部係構成容置空間，容置空間係與 貫孔連通。第二重佈導體位於貫孔内以及容置空間 内，且第二重佈導體係接觸承接部，並沿著貫孔由承 接部朝向被動表面方向延伸出去。絕緣材料填充於第 二重佈導體與基板以及第二重佈導體與***部之間。 本發明提出一種立體導通結構的製造方法，係應 用於封裝件’方法包括：（a)提供基板，基板具有主動 Ήν4682ΡΑ 8i ww ^ PA light, the insulating material 16 adjacent to the solder pad 12 will also be burned by the laser at the same time, resulting in a larger aperture at the end of the channel 17 or even exposing the wafer 1 〇 ° when the channel 17 is refilled with the conductive material 18, will make The conductive material 18 contacts the wafer 10, causing the electrically conductive material 18, which would otherwise have to be insulated, to be electrically connected to the wafer 1 , also known as the leakage current problem. SUMMARY OF THE INVENTION The present invention relates to a three-dimensional conductive structure and a method of fabricating the same. The present invention proposes a three-dimensional conduction structure for use in a package. The three-dimensional conduction structure includes a substrate, a first redistribution conductor, a second redistribution conductor, and an insulating material. The substrate has an active surface and a passive surface opposite thereto. The substrate has solder pads and through holes, and the pads are located on the active surface. The first redistribution conductor includes a ridge portion and a receiving portion, and the ridge portion is bulged outward from the active surface of the substrate, and is electrically connected to the solder 塾 ' receiving portion on the outer side of the active surface, and is connected to the ridge portion, wherein the ridge portion The receiving portion forms a receiving space, and the receiving space communicates with the through hole. The second redistribution conductor is located in the through hole and in the accommodating space, and the second redistribution system contacts the receiving portion and extends along the through hole from the receiving portion toward the passive surface. The insulating material is filled between the second distribution conductor and the substrate and the second redistribution conductor and the ridge. The present invention provides a method of fabricating a three-dimensional conductive structure, which is applied to a package. The method includes: (a) providing a substrate having an active Ήν4682ΡΑ8

201007914 1 W406/PA 表面及與其相對之被動表面，基板具有焊接塾位於主 動表面；（b)從基板之主動表面鑽孔至被動表面，據此 形成貫孔；（c)在主動表面形成第一重佈導體，第一重 佈導體係連接焊接墊並由主動表面向外***，據以構 成與貫孔連通之容置空間；（d)填入絕緣材料於貫孔以 及容置空間内；（e)施行雷射鑽孔，沿著貫孔與容置空 間在絕緣材料内形成通孔，通孔末端係暴露出第一重 佈導體；以及(f)填入導電材料於通孔内，據以形成接 觸第一重佈導體之第二重佈導體。 為讓本發明之上述内容能更明顯易懂，下文特舉 一較佳實施例，並配合所附圖式，作詳細說明如下： 【實施方式】 本發明主要提供一種立體導通結構及其製造方 法，立體導通結構包括基板、第一重佈導體、第二重 佈導體以及絕緣材料。基板具有主動表面及與其&對 之被動表面，基板具有焊接墊以及貫孔，焊接墊位於 主動表面上。第一重佈導體包括***部與承接部，隆 起部由基板之主動表面向外***並電性連接於焊接 墊，承接部位於主動表面之外側並連接於***部，其 中***部與承接部係構成容置”， 貫 孔連通。第二重佈導體位於貫孔内以及容置空間内貝 f第二重料料翻承接部，絲著貫孔由承接部 朝向被動表面方向延伸出去。絕緣材料填充於第二重201007914 1 W406/PA surface and its opposite passive surface, the substrate has a soldering crucible on the active surface; (b) drilling from the active surface of the substrate to the passive surface, thereby forming a through hole; (c) forming a first surface on the active surface Re-distributing the conductor, the first re-wiring system is connected to the soldering pad and is bulged outward from the active surface to form an accommodating space communicating with the through-hole; (d) filling the insulating material in the through-hole and the accommodating space; e) performing laser drilling, forming a through hole in the insulating material along the through hole and the accommodating space, the first rewiring conductor is exposed at the end of the through hole; and (f) filling the conductive material in the through hole, Forming a second redistribution conductor that contacts the first redistribution conductor. In order to make the above-mentioned content of the present invention more comprehensible, a preferred embodiment will be described below in detail with reference to the accompanying drawings. The present invention mainly provides a three-dimensional conductive structure and a manufacturing method thereof. The stereo conduction structure includes a substrate, a first redistribution conductor, a second redistribution conductor, and an insulating material. The substrate has an active surface and a passive surface opposite thereto, the substrate has a solder pad and a through hole, and the solder pad is on the active surface. The first redistribution conductor includes a ridge portion and a receiving portion. The ridge portion is bulged outward from the active surface of the substrate and electrically connected to the solder pad. The receiving portion is located on the outer side of the active surface and is connected to the ridge portion, wherein the ridge portion and the receiving portion are The through-hole is connected. The second redistributed conductor is located in the through-hole and in the accommodating space, the second heavy material is turned over, and the wire-through hole extends from the receiving portion toward the passive surface. Filled in the second weight

TW4682PA 9 201007914TW4682PA 9 201007914

1 WHD6-iPA 佈導體與基板以及第二$料體與***部之間。 本發n ϋ ·射μ麵㈣基板並水 平地延伸j 件需相互連通的封裝結構内實現 三維空間：：不僅可以縮小封裝體積還可以縮短導 線路徑，讓傳輸速度更快、雜訊更小、效能更佳。以 下係舉出„例，配合圖示詳細說明立體導通』 構的製造流程…结構特徵，並描緣出立體導通結構於 封裝結構的配置方式，然熟悉此技藝者當可明瞭，這 攀㈣示與文字僅為說明之用，並不會對本發明之欲保 護範圍造成限縮。 第一實施例 請參照第2A〜2J _ ’其繪示依照本發明之第一 實施例的具有立體導通結構之封裝件之製造流程 圖。本實施例之具有立體導通結構之封裝件的製造方 法包括下列步驟。首先，請參照第2八圖，提供第一 基板11〇,第一基板11〇具有主動表面112及與其相 對之被動表面114，第一基板11〇具有焊换墊116位 於主動表面112。第一基板110較佳的是影像感測晶 片（CMOS Image Sensor，C丨S)，經由主動表面μ2 接受影像或光線。 之後，從第一基板110之主動表面彳彳2鑽孔至 被動表面114，據此形成貫孔118，貫孔可以設 置於第一基板110的任意位置，例如是可以是直接穿 TW4682PA 10 2010079141 WHD6-iPA cloth conductor and substrate and between the second material and the ridge. The present invention n ϋ · shot μ surface (four) substrate and horizontally extending j pieces of interconnected package structure to achieve three-dimensional space: not only can reduce the package volume but also shorten the wire path, making transmission faster, less noise, Better performance. The following is a exemplification of the manufacturing process of the three-dimensional conduction structure, and the configuration of the three-dimensional conduction structure in the package structure, but it is clear to those skilled in the art that this climb (four) shows And the text is for illustrative purposes only, and does not limit the scope of protection of the present invention. For the first embodiment, please refer to FIGS. 2A to 2J _ ', which shows a stereoscopic conduction structure according to the first embodiment of the present invention. The manufacturing method of the package having the three-dimensional conduction structure of the present embodiment includes the following steps. First, referring to FIG. 28, the first substrate 11 is provided, and the first substrate 11 has an active surface 112. And the passive surface 114 opposite thereto, the first substrate 11 has a solder pad 116 on the active surface 112. The first substrate 110 is preferably a CMOS image sensor (C丨S), which is accepted via the active surface μ2 The image or the light is then drilled from the active surface 彳彳 2 of the first substrate 110 to the passive surface 114, thereby forming a through hole 118, and the through hole may be disposed at any position of the first substrate 110. , For example, may be worn directly TW4682PA 10 201007914

1 W4682PA 過焊接墊116(如第2B圖所示）或是穿過線路較不密 集的基板(如本發明第二實施例，如第4B圖所示）。 從主動表面上可以清楚地觀察到焊接墊位置及金屬 線路圖案，無論預計將貫孔穿過焊接墊116或者是芙 板上任意位置，由主動表面進行鑽孔的方式都可以精 確地將貫孔118形成於預設位置，換句話說，本實施 例經由第一基板110之主動表面112進行鑽孔，可以 有效地解決傳統上對位不精準的問題。 接著’在第一基板的主動表面112形成第一重 佈導體(如第2G圖之130)，由於第一重佈導體的製 造方法可以有很多種，本實施例提出其中一種方法並 配合第2C〜2G圖詳細說明如下。首先，如第2C圖 所示，提供第二基板120，並形成至少一個接墊122 於第二基板120上。第二基板120較佳的是透明基 板’例如是玻璃基板’使得光線可以穿透第二基板120 0 進入其下方基板。通常是藉由形成金屬層於第二基板 120上，並移除部分之金屬層以形成圖案化金屬層’ 例如是接墊122，於第二基板120上。之後，請參照 第2D圖，覆蓋絕緣層124於接墊122以及第二基板 120上，絕緣層124較佳的是ABF絕緣膜(Ajin〇mC)tC)1 W4682PA over solder pad 116 (shown in Figure 2B) or a substrate that is less densely lined through the line (as in the second embodiment of the invention, as shown in Figure 4B). The position of the solder pad and the metal line pattern can be clearly observed from the active surface. Whether the through hole is expected to pass through the solder pad 116 or any position on the board, the hole can be accurately drilled by the active surface. The 118 is formed at a preset position. In other words, the present embodiment performs drilling through the active surface 112 of the first substrate 110, which can effectively solve the problem of conventional misalignment. Then, 'the first redistribution conductor is formed on the active surface 112 of the first substrate (such as 130 of FIG. 2G). Since the manufacturing method of the first redistributed conductor can be various, the present embodiment proposes one of the methods and cooperates with the second C. The ~2G diagram is described in detail below. First, as shown in Fig. 2C, the second substrate 120 is provided, and at least one pad 122 is formed on the second substrate 120. The second substrate 120 is preferably a transparent substrate ', such as a glass substrate', such that light can penetrate the second substrate 120 0 into the underlying substrate. The metal layer is formed on the second substrate 120 by removing a portion of the metal layer to form a patterned metal layer, such as pads 122, on the second substrate 120. Then, referring to FIG. 2D, the insulating layer 124 is covered on the pad 122 and the second substrate 120. The insulating layer 124 is preferably an ABF insulating film (Ajin〇mC) tC)

Build-up Film, ABF)或異方性導電膠膜(Anisotropic Conductive Film, ACF)。接著，請參照第2E圖’移 除部份之絕緣層124，藉此形成絕緣層124之凹口 126，且凹口 126係暴露出接墊122。另一方面’絕 TW4682PA 11 201007914Build-up Film, ABF) or Anisotropic Conductive Film (ACF). Next, a portion of the insulating layer 124 is removed as shown in Fig. 2E, whereby the recess 126 of the insulating layer 124 is formed, and the recess 126 exposes the pad 122. On the other hand, ' TW4682PA 11 201007914

1 W406iPA 緣層124較佳地具有開口 127，對應至第一基板11() 主動表面上112。至此，完成第二基板組件120a，其 表面覆蓋絕緣層124,絕緣層124具有凹口 126暴露 出接墊122。然後，請參照第2F圖，形成導電層128 於接墊122、凹口 126内壁以及部分之絕緣層124 上。導電層128可以透過濺鍍(sputter)、化學氣相沈 積（Chemical Vapor Deposition，CVD)、印刷（printing) 等方式形成。根據分佈位置，導電層128進一步地分 為***部128a與承接部128b，***部128a包括位 於絕緣層124上與凹口 126内壁之導電層128,承接 部128b包括位於接墊122上之導電層128，承接部 128b連接於***部128a，其中***部128a與承接 部128b係構成容置空間136。***部1283與承接部 128b較佳的是一體成型。在本實施例中，導電層彳& 以及接墊122較佳地構成第一重佈導體13〇β 需注意的是’第二基板120上之接塾122是可 以省略的，第二基板組件120a内就算沒有接墊122， 也可以沿著凹口 126形成同樣形狀的導電層128，因 此，在其他較佳實施例中，導電層128係單獨地構成 第一重佈導體130。 值得一提的是，本實施例在形成第二基板組件 120a的過程中係採用兩次黃光钱刻步驟，分別用以The W406iPA edge layer 124 preferably has an opening 127 corresponding to the active surface 112 of the first substrate 11(). To this end, the second substrate assembly 120a is completed, the surface of which is covered with an insulating layer 124 having a recess 126 exposing the pads 122. Then, referring to FIG. 2F, a conductive layer 128 is formed on the pad 122, the inner wall of the recess 126, and a portion of the insulating layer 124. The conductive layer 128 can be formed by sputtering, chemical vapor deposition (CVD), printing, or the like. According to the distribution position, the conductive layer 128 is further divided into a ridge portion 128a and a receiving portion 128b. The ridge portion 128a includes a conductive layer 128 on the insulating layer 124 and the inner wall of the recess 126. The receiving portion 128b includes a conductive layer on the pad 122. 128, the receiving portion 128b is connected to the ridge portion 128a, wherein the ridge portion 128a and the receiving portion 128b constitute the accommodating space 136. The ridge portion 1283 and the receiving portion 128b are preferably integrally formed. In the present embodiment, the conductive layer 彳 & and the pad 122 preferably constitute the first redistribution conductor 13 〇 β. It should be noted that the interface 122 on the second substrate 120 can be omitted, and the second substrate assembly can be omitted. The conductive layer 128 of the same shape may be formed along the recess 126 even if there is no pad 122 in 120a. Therefore, in other preferred embodiments, the conductive layer 128 separately constitutes the first redistributor conductor 130. It is worth mentioning that in the process of forming the second substrate assembly 120a, the embodiment uses two yellow light engraving steps respectively.

TW4682PA 餘刻出接塾以及絕緣層開口’而黃絲刻並不會損傷 玻璃表面，因此通過當光線通過第二基板12〇(e.g. 12 201007914The TW4682PA is engraved with the opening and the opening of the insulating layer, and the yellow wire engraved does not damage the glass surface, so by passing light through the second substrate 12 (e.g. 12 201007914)

IW4682PA 玻璃）與絕緣層開口進入第一基板11〇(e.g.影像感測 晶片）時，影像感測晶片得以接收到清晰無誤的影 像，避免影像出現由玻璃表面刮傷引起的雜訊或污 點。 接著，請參照第2G圖’翻覆第二基板組件 120a，對應地將其黏合於第一基板110之主動表面 112側，其中將位於絕緣層124上之導電層128係連 接於焊接墊116 ’並將位於接墊122上以及凹口内壁 之導電層128面對貫孔118,據此於第一基板110之 主動表面112形成第一重佈導體130。至此，在第— 基板110的主動表面112已經形成第一重佈導體 130,第一重佈導體130係連接焊接墊116並由主動 表面112向外***’據以構成與貫孔118連通之容置 空間136，如第2G圖所示。 接著，填入絕緣材料134於貫孔118以及容置 空間136内，如第2 Η圖所示。在較佳的實施例中， 將第三基板140設置於第一基板110的被動表面 114，而絕緣材料134也覆蓋於第三基板140以及第 一基板110的被動表面114上。第三基板140也具有 主動表面及與其相對之被動表面，第三基板140之主 動表面包括焊接墊142 ’焊接墊142較佳的是遠離第 一基板110之被動表面114。 之後’從被動表面114朝向主動表面112的方 向沿著貫孔118與容置空間136在絕緣材料134内 TW4682PA u 201007914When the IW4682PA glass) and the insulating layer are opened into the first substrate 11 (e.g. image sensing wafer), the image sensing wafer can receive a clear and unambiguous image to avoid noise or stain caused by scratches on the glass surface. Next, referring to FIG. 2G, 'overturning the second substrate assembly 120a, correspondingly bonding it to the active surface 112 side of the first substrate 110, wherein the conductive layer 128 on the insulating layer 124 is attached to the solder pad 116' and The conductive layer 128 on the pad 122 and the inner wall of the recess faces the through hole 118, whereby the first redistribution conductor 130 is formed on the active surface 112 of the first substrate 110. So far, the first redistribution conductor 130 has been formed on the active surface 112 of the first substrate 110, and the first redistribution conductor 130 is connected to the solder pad 116 and is bulged outward by the active surface 112 to form a space communicating with the through hole 118. Space 136 is placed as shown in Figure 2G. Next, the insulating material 134 is filled in the through hole 118 and the accommodating space 136 as shown in FIG. In a preferred embodiment, the third substrate 140 is disposed on the passive surface 114 of the first substrate 110, and the insulating material 134 also covers the third substrate 140 and the passive surface 114 of the first substrate 110. The third substrate 140 also has an active surface and a passive surface opposite thereto. The active surface of the third substrate 140 includes solder pads 142. The solder pads 142 are preferably away from the passive surface 114 of the first substrate 110. Thereafter, the direction from the passive surface 114 toward the active surface 112 is along the through hole 118 and the accommodating space 136 in the insulating material 134. TW4682PA u 201007914

i W40«2PA 鑽孔，形成通孔146，通孔146末端係暴露出第一重 佈導體130之導電層128,如第2I圖所示。鑽孔方 法車乂佳地疋施行雷射鑽孔技術（丨ase「dr丨丨丨丨叩），由於雷 射對於絕緣材料與金屬材料的選擇比很高，要控制雷 射使其#刻完絕緣材料134後不會繼續蝕刻導電層 128疋比較容易達成的’因此可以避免傳統上打穿導 電層的問題。在較佳的實施例中，可以透過相同或不 籲同的方式移除絕緣材料134形成開孔147,以暴露出 第二基板140之焊接墊142。 接者填入導電材料於通孔146内，據以形成 接觸第—重佈導體⑽之第二重佈導體148，如第 2 J圖所示。 根據上述製造方法製成之立體導通結構的結構 特徵揭露如下。請參照第2(3圖，本實施例之立體導 通結構包括：第一基板11〇、第一重佈導體13〇、第 _ 二重佈導體148以及絕緣材料134。第一基板11〇具 有焊接墊116以及貫孔118,焊接墊116•位於主動& 面112上。在本實施例中，貫孔118係較•佳地是穿過 焊接墊116。 第一重佈導體130包括***部1288|與承接部 128b，***部128a與承接部128b較佳的是一體成 型。***部128a(即位於凹口 126内壁之導電層128) 由第一基板110之主動表面112向外***，並電性連 接於焊接墊116,本實施例之***部12如較佳的是 TW4682PA 14 201007914The i W40 «2PA is drilled to form a via 146, and the end of the via 146 exposes the conductive layer 128 of the first redistribution conductor 130, as shown in FIG. Drilling method 乂 乂 疋 疋 疋 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 丨丨丨丨叩 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷The insulating material 134 does not continue to etch the conductive layer 128, which is relatively easy to achieve. Therefore, the problem of conventionally penetrating the conductive layer can be avoided. In a preferred embodiment, the insulating material can be removed by the same or non-discriminatory manner. 134 is formed with an opening 147 to expose the solder pad 142 of the second substrate 140. The connector fills the conductive material in the through hole 146, thereby forming a second redistribution conductor 148 contacting the first repeating conductor (10), such as 2 J. The structural features of the three-dimensional conductive structure produced by the above manufacturing method are disclosed as follows. Referring to FIG. 2 (3), the three-dimensional conductive structure of the present embodiment includes: a first substrate 11 〇, a first redistributed conductor The first substrate 11 has a solder pad 116 and a through hole 118, and the solder pad 116 is disposed on the active & surface 112. In this embodiment, the through hole 118 The system is better than the soldering pad 11 6. The first redistribution conductor 130 includes a ridge portion 1288| and a receiving portion 128b, and the ridge portion 128a and the receiving portion 128b are preferably integrally formed. The ridge portion 128a (ie, the conductive layer 128 located on the inner wall of the recess 126) is first The active surface 112 of the substrate 110 is bulged outwardly and electrically connected to the solder pad 116. The ridge portion 12 of the embodiment is preferably TW4682PA 14 201007914.

I WHOCiPA 认置於焊接墊116上。承接部128b(即位於接墊122 表面之導電層128)位於主動表面112之外侧，並連 接於***部1283 ’其中***部128a與承接部128b 係構成容置空間136，容置空間136係與貫孔連通 118。在本實施例中，第—重佈導體13◦較佳地更包 括接墊122,係設置於第二基板12〇上，並與承接部 12 8 b相連。 第二重佈導體148位於貫孔118内以及容置空 間136内，且第二重佈導體148係接觸承接部128卜 並沿著貫孔118由承接部128b朝向被動表面114方 向延伸出去。絕緣材料134填充於第二重佈導體148 與第一基板110以及第一重佈導體148與***部 128a之間。 請注意’第一基板110之焊接墊116連接第一 重佈導體130(包括第二基板之接塾122與導電層 ^ 128)，第一重佈導體130連接第二重佈導體148，如 此一來，第一基板110之電訊號得以經由第一重佈導 體130與第二重佈導體148傳遞出去。值得一提的 是，本實施例之立體導通結構可以避免漏電流的問 題。詳細地說，傳統上以雷射鐵孔至導電層128時， 導電層128會反射或折射雷射光，鄰近導電層128 的絕緣材料134也同時會被雷射燒掉，導致通孔146 末端孔徑較大甚至暴露出周圍材料(例如是基板），當 通孔146内重新填入導電材料，將使得導電材料接觸 TW4682PA 15 201007914I WHOCiPA is placed on the solder pad 116. The receiving portion 128b (that is, the conductive layer 128 on the surface of the pad 122) is located on the outer side of the active surface 112, and is connected to the ridge portion 1283'. The ridge portion 128a and the receiving portion 128b constitute an accommodating space 136, and the accommodating space 136 is coupled to The through hole is connected to 118. In the present embodiment, the first repeating conductor 13 ◦ preferably further includes a pad 122 disposed on the second substrate 12 , and connected to the receiving portion 12 8 b. The second redistribution conductor 148 is located in the through hole 118 and in the accommodation space 136, and the second redistribution conductor 148 is in contact with the receiving portion 128 and extends along the through hole 118 from the receiving portion 128b toward the passive surface 114. The insulating material 134 is filled between the second redistribution conductor 148 and the first substrate 110 and the first redistribution conductor 148 and the raised portion 128a. Please note that the solder pad 116 of the first substrate 110 is connected to the first redistribution conductor 130 (including the interface 122 of the second substrate and the conductive layer 128), and the first redistribution conductor 130 is connected to the second redistribution conductor 148. The electrical signals of the first substrate 110 are transmitted through the first redistribution conductor 130 and the second redistribution conductor 148. It is worth mentioning that the three-dimensional conduction structure of this embodiment can avoid the problem of leakage current. In detail, when the iron hole is conventionally irradiated to the conductive layer 128, the conductive layer 128 reflects or refracts the laser light, and the insulating material 134 adjacent to the conductive layer 128 is also burned by the laser, resulting in the aperture at the end of the through hole 146. Larger or even exposed surrounding material (such as a substrate), when the conductive material is refilled in the via 146, the conductive material will be contacted with TW4682PA 15 201007914

1 W4682PA 到周圍材料，造成原未必須絕緣的導電材料與基板產 生電性連接，也就是所謂的漏電流問題。然而，本實 施例之立體導通結構以導電層128環繞通孔146末 端，就算以雷射鑽孔睛發生擴孔現象’填入的導電材 料（即第二重佈導體148)仍是與導電層128接觸，不 會將電流傳遞至基板’因此本實施例之立體導通結構 可以解決傳統上矽通道導通結構(Thr〇ugh Silicon Via，TSV)難以避免的潙電流問題。 •最後，在較佳的實施例中，導電材料也填入開孔 147，在絕緣材料134表面形成圖案化導電層 152/154/156 ’覆蓋絕緣層150於第一基板11〇與第 三基板140 ’钱刻絕緣層150並填入導電材料形成焊 接墊162/164/166，最後於焊接墊162/164/166植上 銲球172/174/176 ’藉此完成封裝件Ί〇〇，如第2」 圖所示。 馨本實施例之封裝件100利用立體導通結構可以 在基板與基板之間或者是基板與外部元件之間傳遞 電sfl號。舉例來說，第一基板彳1〇可以透過焊接整 116、第一重佈導體13〇、第二重佈導體148、導電 層152、焊接墊162以及銲球172構成的路徑與外部 元件傳遞電訊號；第—基板11〇也可以透過焊接墊 116、第-重佈導體13〇、第二重佈導體148、導電 層/56、焊接墊166以及銲球176構成的路徑傳送電 訊號至第三基板140，例如是將接收到的影像傳送至1 W4682PA to the surrounding material, causing the conductive material that is not necessarily insulated to be electrically connected to the substrate, which is the so-called leakage current problem. However, the three-dimensional conductive structure of the present embodiment surrounds the end of the through hole 146 with the conductive layer 128, even if the hole is filled by the laser drilling hole, the conductive material (ie, the second red cloth conductor 148) is still connected with the conductive layer. The 128 contact does not transfer current to the substrate. Therefore, the stereo conduction structure of the present embodiment can solve the problem of the 沩 current that is difficult to avoid by the conventional 矽 channel conduction structure (TSV). • Finally, in a preferred embodiment, the conductive material is also filled into the opening 147, and a patterned conductive layer 152/154/156 is formed on the surface of the insulating material 134 to cover the insulating layer 150 on the first substrate 11 and the third substrate. 140 'money insulating layer 150 and filled with conductive material to form solder pads 162 / 164 / 166, and finally solder balls 172 / 174 / 176 ' on the solder pads 162 / 164 / 166 ' to complete the package Ί〇〇, such as Figure 2 is shown. The package 100 of the embodiment of the present invention can transmit an electric sfl number between the substrate and the substrate or between the substrate and the external component by using a three-dimensional conduction structure. For example, the first substrate 彳1〇 can transmit telecommunications through the path formed by the soldering unit 116, the first redistributing conductor 13〇, the second redistributing conductor 148, the conductive layer 152, the soldering pad 162, and the solder ball 172, and the external component. The first substrate 11 can also transmit a signal to the third through a path formed by the solder pad 116, the first redistribution conductor 13A, the second redistribution conductor 148, the conductive layer/56, the solder pad 166, and the solder ball 176. The substrate 140 is, for example, transmitting the received image to

TW4682PA 16TW4682PA 16

201007914 1 W402S2PA 第三基板進行影像處理。 本實施例雖已揭露第二基板較佳的是玻璃 基板，第一基板110較佳的是影像感測晶片（CMOS Image Sensor，CIS)可以透過玻璃基板經由主動表面 112接受影像或光線，第三基板140較佳的是數位訊 號處理器（Digital Signal Processor, DSP) ’ 用以將由 第一基板11〇(e.g.影像感測晶片）接收到的影像處理 之後傳送出去。然而，此技術領域中具有通常知識者 當可明瞭，本發明之立體導通結構及其製造方法之應 用範圍並不限定於此，亦可以應用至微機電系統 (Micro-Electro-Mechanical Systems, MEMS)或其他 封裝結構或技術。 再者’本實施例雖已揭露第二基板組件形成步驟 於第2C〜2E圖，然而形成步驟並不限定於此。舉例 來說，请參照第3A〜3 E圖，其繪·示依照本發明之第 一較佳實施例之第二基板組件的另一形成方法的示 意流程圖。首先’如第3A圖所示，提供第二基板12〇, 並形成圖案化金屬層於第二基板120上，圖案化金屬 層包括保護層222以及至少一個接墊122，圖案化金 屬層厚度較佳的是大約ιμΓΤΊ。之後，請參照第3B圖， 覆蓋絕緣層124於保護層222、接墊122以及第二基 板120上，絕緣層124的厚度較佳的是大約叩。 接著，請參照第3C圖，移除一部分之絕緣層124，201007914 1 W402S2PA The third substrate is used for image processing. In this embodiment, it is disclosed that the second substrate is preferably a glass substrate. The first substrate 110 is preferably a CMOS image sensor (CIS) that can receive images or light through the active surface 112 through the glass substrate. The substrate 140 is preferably a digital signal processor (DSP) 'for transmitting the image received by the first substrate 11 (eg image sensing wafer) and then transmitting it. However, it is obvious to those skilled in the art that the application range of the three-dimensional conductive structure and the manufacturing method thereof of the present invention is not limited thereto, and can also be applied to Micro-Electro-Mechanical Systems (MEMS). Or other packaging structure or technology. Further, in the present embodiment, the second substrate assembly forming step is disclosed in Figs. 2C to 2E, but the forming step is not limited thereto. For example, please refer to Figures 3A to 3E, which show a schematic flow chart of another method of forming a second substrate assembly in accordance with a first preferred embodiment of the present invention. First, as shown in FIG. 3A, a second substrate 12 is provided, and a patterned metal layer is formed on the second substrate 120. The patterned metal layer includes a protective layer 222 and at least one pad 122, and the thickness of the patterned metal layer is relatively The best is about ιμΓΤΊ. Thereafter, referring to FIG. 3B, the insulating layer 124 is covered on the protective layer 222, the pad 122, and the second substrate 120. The thickness of the insulating layer 124 is preferably about 叩. Next, please refer to the 3C figure, remove a part of the insulating layer 124,

據此暴露出保護層222。較麵是以雷射移除絕緣 TW4682PA 201007914The protective layer 222 is thereby exposed. The face is laser-removed and insulated TW4682PA 201007914

J W4682PA 層，由於雷射也會蝕刻第二基板120，如果沒有保護 層222’此-㈣之f射非常容易在第二基板12〇'表 面形成傷痕，加上雷射對於絕緣材料與金屬材料(接 墊122)的選擇比很高，因此保護層222可以有效地 防止第二基板120被雷射破壞。然後，請參照第3d 圖，以黃光製程蝕刻暴露出來的保護層222以形成絕 緣層之開口 127’對應至第一基板主動表面上 之感光區’使得光線可以穿透第二基板120以及開口 127進入其下方基板。最後，請參照第3日圖，移除 另一部分之絕緣層124,藉此形成絕緣層124之凹口 126,且凹口 126係暴露出接签122，此步驟較佳的 是施行雷射鑽孔技術來移除絕緣材料。值得一提的 是，本實施方法利用兩次雷射鑽孔以及一次黃光製程 來完成第二基板組件，可以保持第二基板表面平整 度，且製造成本較為低廉。此外，由於雷射對於絕緣 材料與金屬材料的選擇比很高，要控制雷射使其蝕列 完絕緣材料後不會繼續蝕刻金屬材料是比較容易達〆 成的，因此可以避免傳統上打穿金屬材料的問題。 第二實施例 本實施例與上述實施例不同之處在於貫孔位 置、第一重佈導體的結構及其形成方法，其餘相同的 元件與步驟係沿用相同標號，於此不再贅述。 請參照第4Α〜4Ε圖，其繪示依照本發明之第二 實施例之具有立體導通結構之封裴件的製造流程示J W4682PA layer, because the laser will also etch the second substrate 120, if there is no protective layer 222' this - (four) f shot is very easy to form a flaw on the surface of the second substrate 12 〇 ', plus laser for insulating materials and metal materials The selection ratio of (pad 122) is high, and thus the protective layer 222 can effectively prevent the second substrate 120 from being damaged by the laser. Then, referring to FIG. 3d, the exposed protective layer 222 is etched by a yellow light process to form an opening 127' of the insulating layer corresponding to the photosensitive region on the active surface of the first substrate such that light can penetrate the second substrate 120 and the opening. 127 enters the lower substrate. Finally, please refer to the third day diagram to remove another portion of the insulating layer 124, thereby forming the recess 126 of the insulating layer 124, and the recess 126 is exposed to the label 122. This step preferably performs a laser drill. Hole technology to remove insulation. It is worth mentioning that the method of the present invention utilizes two laser drilling and one yellow light process to complete the second substrate assembly, which can keep the surface of the second substrate flat and has a relatively low manufacturing cost. In addition, since the laser has a high selection ratio of the insulating material and the metal material, it is relatively easy to control the laser to etch the metal material after etching the insulating material, so that the conventional breakdown can be avoided. The problem with metallic materials. The second embodiment differs from the above embodiment in the position of the through hole, the structure of the first redistributed conductor, and the method of forming the same. The same components and steps are denoted by the same reference numerals and will not be described again. Please refer to FIG. 4 to FIG. 4 for a manufacturing process diagram of a sealing member having a three-dimensional conduction structure according to a second embodiment of the present invention.

TW4682PA 18TW4682PA 18

201007914 1W4682PA 意圖。請參照第4A圖，第一基板110具有焊接墊116 於其主動表面112上，且具有貫孔218。接著，在第 一基板110的主動表面112形成第一重佈導體，其步 驟揭露如下。 首先，如第4A圖所示，形成導電凸塊228於第 一基板110之主動表面112上，例如是電鍍或印刷等 方式。導電凸塊228係由第一基板110之主動表面 112向外***，並電性連接於該焊接墊116，構成本 實施例之第一重佈導體之***部。在本實施例中，導 電凸塊228較佳的是設置於焊接墊116上，並延伸至 貫孔218周圍之主動表面112上。相較於第一實施 例，本實施例藉由導電凸塊228重新佈線的功能，將 貫孔218遠離焊接墊116,例如是設置於第一基板110 邊緣或是線路較不集中的地方，藉此提高第一基板線 路佈局的自由度。 接著，如第4B圖所示，提供第二基板組件 220a，包括第二基板120、接墊122以及絕緣層124, 接墊122以及絕緣層124係相鄰地設置於第二基板 120 上。 之後，如第4C圖所示，翻覆第二基板組件 220a，將第二基板組件220a之接墊122焊接於第一 基板110之導電凸塊228，並將第二基板組件220a 黏合於第一基板110之主動表面112,據此於第一基 板110之主動表面112形成第一重佈導體230。 TW4682PA 19 201007914201007914 1W4682PA Intent. Referring to FIG. 4A, the first substrate 110 has a solder pad 116 on its active surface 112 and has a through hole 218. Next, a first redistribution conductor is formed on the active surface 112 of the first substrate 110, the steps of which are disclosed below. First, as shown in Fig. 4A, conductive bumps 228 are formed on the active surface 112 of the first substrate 110, such as by electroplating or printing. The conductive bumps 228 are outwardly raised from the active surface 112 of the first substrate 110 and electrically connected to the solder pads 116 to form the ridges of the first redistribution conductor of the embodiment. In the present embodiment, the conductive bumps 228 are preferably disposed on the solder pads 116 and extend over the active surface 112 around the vias 218. Compared with the first embodiment, in this embodiment, the through hole 218 is separated from the solder pad 116 by the function of rewiring the conductive bump 228, for example, at the edge of the first substrate 110 or where the line is less concentrated. This increases the degree of freedom in the layout of the first substrate line. Next, as shown in FIG. 4B, a second substrate assembly 220a is provided, including a second substrate 120, pads 122, and an insulating layer 124. The pads 122 and the insulating layer 124 are adjacently disposed on the second substrate 120. Then, as shown in FIG. 4C, the second substrate assembly 220a is flipped, the pads 122 of the second substrate assembly 220a are soldered to the conductive bumps 228 of the first substrate 110, and the second substrate assembly 220a is bonded to the first substrate. The active surface 112 of the 110, whereby the first redistribution conductor 230 is formed on the active surface 112 of the first substrate 110. TW4682PA 19 201007914

1 W4052PA 本實施例之第一重佈導體230係由第二基板 120之接墊122以及第一基板11〇之導電凸塊228 對組而成。從結構上爽砉，筮 ^ 再工木有第一重佈導體230包括隆 &p(i.e.導電凸塊228〉與承接部（丨e接塾122)，*** 部(i.e.導電凸塊228)由第-基板11〇之主動表面112 向外***’並電性連接於焊接墊116。承接部（i_e.接 墊122)位於主動表面112之外侧，並連接於***部 (i_e.導電凸塊228〉，其中***部（j e導電凸塊228) 與承接部（i.e.接墊122)係構成容置空間236，容置空 間236係與貫孔連通218。 最後，依序形成絕緣材料134、第二重佈導體 148、第三基板140、銲球170等，完成封裝件2〇〇， 如第4D圖所示。第二重佈導體148位於貫孔218内 以及容置空間236内，且第二重佈導體148係接觸承 接部（i.e.接墊122)，並沿著貫孔218由承接部（丨匕接 墊122)朝向被動表面114方向延伸出去。 9 雖然本實施例之第一重佈導體230與第—實施 例之第一重佈導體130的形成方式不同，但本實施例 之導電凸塊228與接墊122組成之第一重佈導體係 230同樣具有容置空間，就算鑽孔時發生擴孔現象， 填入的導電材料（即第二重佈導體148)仍是與第一重 佈導體230接觸，不會將電流傳遞至基板，因此本實 施例之立體導通結構仍然可以解決傳統上梦通道導 通結構(Through Silicon Via，TSV)的漏電流門題。 TW4682PA 20 2010079141 W4052PA The first redistribution conductor 230 of the present embodiment is formed by a pair of pads 122 of the second substrate 120 and conductive bumps 228 of the first substrate 11 . From the structurally refreshing, 筮^ re-working wood has a first redistribution conductor 230 including a ridge & p (ie conductive bump 228> and a receiving portion (丨e interface 122), a raised portion (ie conductive bump 228) The active surface 112 of the first substrate 11 is bulged outwardly and electrically connected to the solder pad 116. The receiving portion (i_e. pad 122) is located on the outer side of the active surface 112 and is connected to the ridge (i_e. conductive bump) 228>, wherein the ridge portion (je conductive bump 228) and the receiving portion (ie pad 122) constitute an accommodating space 236, and the accommodating space 236 is connected to the through hole 218. Finally, the insulating material 134 is formed in sequence. The double-disc conductor 148, the third substrate 140, the solder ball 170, and the like complete the package 2, as shown in FIG. 4D. The second redistribution conductor 148 is located in the through-hole 218 and in the accommodating space 236, and The double cloth conductor 148 is in contact with the receiving portion (ie pad 122) and extends along the through hole 218 by the receiving portion (the splicing pad 122) toward the passive surface 114. 9 Although the first re-clothing of this embodiment The conductor 230 is formed differently from the first redistribution conductor 130 of the first embodiment, but the conductive bump 22 of the present embodiment 8 and the first re-distribution system 230 composed of the pads 122 have the same accommodation space, even if the hole expansion phenomenon occurs during drilling, the filled conductive material (ie, the second red cloth conductor 148) is still the first red cloth. The conductor 230 is in contact with each other and does not transmit current to the substrate. Therefore, the three-dimensional conduction structure of the embodiment can still solve the leakage current problem of the conventional Dream Silicon Via (TSV). TW4682PA 20 201007914

1 W4682PA 值得一提的是，本實施例之第一重佈導體230 的***部（i.e.導電凸塊228)較佳的是由電鍍法所形 成’因此第一重佈導體230整體結構較為穩固紮實， 不易損壞。1 W4682PA It is worth mentioning that the ridge portion (ie conductive bump 228) of the first redistribution conductor 230 of the present embodiment is preferably formed by electroplating method. Therefore, the overall structure of the first redistribution conductor 230 is relatively stable and solid. , not easy to damage.

另一方面，本實施例雖然藉由導電凸塊228重 新佈線的功能，讓貫孔218遠離焊接墊116，然本發 明並不限定於此。本實施例也可以讓貫孔穿過焊接 墊’並直接將導電凸塊設置於焊接墊上也會位於貫孔 周圍’之後與第 ，一-八。"八工W % — 心，| 以構成上述結構但位置不同之第一重佈導體。 本發明上述實施例所揭露之立體導通結構，可以 垂直地穿過基板並水平地延伸 通的封裝結構时現三維㈣ 有***部與承接部構：:：。此外，第-重佈導體具 程中發生擴孔，也不會產的形狀，即使雷射鑽孔遇 本發明提出的立體導流問題。另-方面’ 正面鑽孔避免對位不=的製造方法’可以由基核 保護基板使得雷射鱗孔過、°】題此外，形成金屬層 綜上所述，雖然本發=不會刮傷基板表面。 上，然其並非用以限定本以較佳實施例揭露如 中具有通常知識者，在不月本發明所屬技術領域 内，當可作各種之 更動與^離本發明之精神和範圍 範圍當視後附之申諳直、t £飾。因此，本發明之保護 TW4682PA °利範圍所界定者為準。 21On the other hand, in the present embodiment, the through hole 218 is kept away from the solder pad 116 by the function of rewiring the conductive bump 228, but the present invention is not limited thereto. In this embodiment, the through hole can also be passed through the solder pad and the conductive bump can be directly disposed on the solder pad and also located around the through hole and after the first one. "eight workers W % - heart, | The first red cloth conductor that constitutes the above structure but has a different position. The three-dimensional conductive structure disclosed in the above embodiments of the present invention can be vertically passed through the substrate and extends horizontally through the package structure. The three-dimensional (four) ridges and the receiving portions are:::. In addition, the reaming of the first-re-distribution conductor has a shape that does not occur, even if the laser drilling encounters the problem of the stereoscopic flow proposed by the present invention. Another aspect - the front hole drilling avoids the alignment method = the manufacturing method can be protected by the base core to make the laser scale hole pass, °) In addition, the formation of the metal layer is described above, although the hair = not scratched The surface of the substrate. In addition, it is not intended to limit the scope of the present invention, and the scope of the invention may be varied and varied within the scope of the invention. Attached to the application of the straight, t £ decorated. Therefore, the protection of the present invention is defined by the scope of protection TW4682PA. twenty one

201007914 1 W405^PA 【圖式簡單說明】 第1A〜1F圖繪示矽通道導體結構之製造方法 的示意流程圖。 第2A〜2J圖繪示依照本發明之第一實施例的具 有立體導通結構之封裝件之製造流程圖。 第3A〜3E圖繪示依照本發明之第一較佳實施 例之第二基板組件的另一形成方法的示意流程圖。 第4A〜4D圖繪示依照本發明之第二實施例之 具有立體導通結構之封裝件的製造流程示意圖。 【主要元件符號說明】 10 ： 晶片 10a :晶片正面 10b .晶片背面 12 ： 焊接墊 14 ： 開孔 16 ： 絕緣材料 17 ： 通道 18 ： 導電材料 20 ： 晶片 22 ： 焊接墊 100 :封裝件 110 :第一基板 112 :主動表面 TW4682PA 22201007914 1 W405^PA [Simple description of the drawings] Figs. 1A to 1F show schematic flow charts of a method of manufacturing a channel conductor structure. 2A to 2J are views showing a manufacturing flow chart of a package having a three-dimensional conduction structure according to a first embodiment of the present invention. 3A to 3E are schematic flow charts showing another method of forming the second substrate assembly in accordance with the first preferred embodiment of the present invention. 4A to 4D are views showing a manufacturing process of a package having a three-dimensional conduction structure according to a second embodiment of the present invention. [Main component symbol description] 10 : Wafer 10a : Wafer front side 10 b. Wafer rear side 12 : Solder pad 14 : Opening 16 : Insulation material 17 : Channel 18 : Conductive material 20 : Wafer 22 : Solder pad 100 : Package 110 : A substrate 112: active surface TW4682PA 22

201007914 1 W4682PA 1 1 4 :被動表面 116 :焊接墊 118 :貫孔 120 :第二基板 120a :第二基板組件 122 :接墊 124 :絕緣層 126 :凹口 127 :開口 128 :導電層 128a :***部 128b :承接部 130 :第一重佈導體 134 :絕緣材料 136 :容置空間 140 :第三基板 142 :焊接墊 146 :通孔 147 :開孔 148 :第二重佈導體 150 :絕緣層 152、154、156 :圖案化導電層 162、164、166 :焊接墊 170、172、174、176 :銲球 TW4682PA 23 201007914201007914 1 W4682PA 1 1 4 : Passive surface 116 : solder pad 118 : through hole 120 : second substrate 120 a : second substrate assembly 122 : pad 124 : insulating layer 126 : notch 127 : opening 128 : conductive layer 128 a : ridge Portion 128b: receiving portion 130: first redistribution conductor 134: insulating material 136: accommodating space 140: third substrate 142: soldering pad 146: through hole 147: opening 148: second redistributing conductor 150: insulating layer 152 , 154, 156: patterned conductive layer 162, 164, 166: solder pads 170, 172, 174, 176: solder balls TW4682PA 23 201007914

L· *?-TUU^rW 200 :封裝件 218 :貫孔 220a :第二基板組件 222 :保護層 228 :導電凸塊 230 :第一重佈導體 236 :容置空間 TW4682PA 24L· *?-TUU^rW 200 : package 218 : through hole 220 a : second substrate assembly 222 : protective layer 228 : conductive bump 230 : first redistributed conductor 236 : accommodation space TW4682PA 24

Claims (1)

201007914 十、申請專利範圍： 1. 一種立體導通結構，係應用於一封裝件’該 立體導通結構包括： 一基板，具有一主動表面及與其相對之一被動表 面’該基板具有一焊接墊以及一貫孔，該焊接墊位於 該主動表面上； 一第一重佈導體，包括·· Φ 一***部’由該基板之該玄動表面向外隆 起’並電性連接於該焊接墊；及 一承接部，位於該主動表面之外侧，並連接 於該***部，其中該***部與該承换部係構成一容置 空間，該容置空間係與該貫孔連通； 一第二重佈導體，位於該貫孔内以及該容置空間 内’且該第二重佈導體係接觸該承换部’並沿著該貫 孔由該承接部朝向該被動表面方向延伸出去；以及 Φ 一絕緣材料，填充於該第二重钸導體與該基板以 及該第二重佈導體與該***部之間。 2·如申請專利範圍第彳項所述之結構，其中該 貫孔係穿過焊接墊。 3·如申請專利範圍第2頊所述之結構，其中該 ***部係設置於該焊接墊上。 4·如申請專利範圍第1頊所述之結構’其中該 貫孔係遠離該焊接墊。 5.如申請專利範圍第4項所述之結構，其中該 TW4682PA 25 201007914 * ”*t\/u2Pa ***部係設置於該焊接塾上，並延伸至該貫孔周圍之 該主動表面上。 6. 如申請專利範圍第1項所述之結構，其中該 ***部係一導電凸塊。 7. 如申請專利範圍第1項所述之結構，其中該 ***部與該承接部係一體成型。 8. 如申請專利範圍第1項所述之結構，其中該 鲁 基板係一第一基板’該封裝件更包括一第二基板，該 第二基板係位於該第一基板之該主動表面侧，並與該 第一基板實質上平行設置。 9. 如申請專利範圍第8項所述之結構，其中該 第一重佈導體更包括一接墊(pad)，係設置於該第二 基板上，並與該承接部相連。 10. 如申請專利範圍第8項所述之結構，其中該 承接部接觸該第二基板。 ^ 11.如申請專利範圍第8項所述之結構，其中該 ❹ 第一基板係一影像感測晶片（CMOS Image Sensor, CIS)，該第二基板係一透明基板。 12.如申請專利範圍第8項所述之結構，其中該 封裝件更包括一第三基板，係設置於該第一基板之該 被動表面。 13.如申請專利範圍第12項所述之結構，其中 該第三基板包括一焊接墊，且該焊接墊係遠離該第一 基板之該被動表面。 TW4682PA 26 201007914 TW4682PA 14. 如申請專利範圍第12項所述之結構，其中 該第三基板之該焊接墊係係透過該第一重佈導體以 及該第二重佈導體與該第二基板之該焊接墊電性連 接。 15. 如申請專利範圍第12項所述之結構，其中 該第三基板係一數位訊號處理器（Digital Signal Processor, DSP)。 16. 如申請專利範圍第8項所述之結構，其中該 封裝件更包括： 一絕緣層，係覆蓋於該第一基板以及該第三基 板；以及 一銲球，係位於該絕緣層之下，並連接於該第二 重佈導體。 17. —種立體導通結構的製造方法，係應用於一 封裝件，該方法包括： 提供一基板，該基板具有一主動表面及與其相對 之一被動表面，該基板具有一焊接塾位於該主動表 面； 從該基板之該主動表面鑽孔至該被動表面，據此 形成一貫孔； 在該主動表面形成一第一重佈導體，該第一重佈 導體係連接該焊接墊並由該主動表面向外***，據以 構成與該貫孔連通之一容置空間； 填入一絕緣材料於該貫孔以及該容置空間内； TW4682PA 27 201007914 1 W40»2PA 沿著該貫孔與該容置空間在絕緣材料内形成一 通孔，該通孔末端係暴露出該第一重佈導體；以及 填入一導電材料於該通孔内，據以形成接觸該第 一重佈導體之一第二重佈導體。 18.如申請專利範圍第17項所述之方法，其中 該基板係一第一基板，形成該第一重佈導體之步驟包 括： 提供一第二基板組件，其表面覆蓋一絕緣層，該 絕緣層具有一凹口暴露出一接整； 形成一導電層於該接墊、該凹口内壁以及部分之 該絕緣層上’其中該導電層以及該接墊係構成該第一 重佈導體；以及 翻覆該第二基板組件，對應地將其黏合於該第一 基板之該主動表面，其中將位於該絕緣層上之該導電 層係連接於該焊接墊，並將位於該接墊上以及該凹口 内壁之該導電層面對該貫孔，據此於該第一基板之該 主動表面形成該第一重佈導體。 19.如申請專利範圍第18項所述之方法，其中提 供該第二基板組件之步驟包括： 提供一第二基板； 形成一圖案化金屬層於該第二基板上，該圖案化 金屬層至少包括一保護層以及該接墊； 覆蓋一絕緣層於該保護層、該接墊以及該第二基 板上； TW4682PA 28 201007914 1 w抑δ2ΡΑ 移除一部分之該絕緣層，據此暴露出該保護層； 蝕刻該保護層；以及 移除另一部分之該絕緣層，藉此形成該絕緣層之 該凹口，且該凹口係暴露出該接墊。 20. 如申請專利範圍第18項所述之方法，其中 提供該第二基板組件之步驟包括： 提供一第二基板，並形成一接墊於該第二基板 上； 覆蓋一絕緣層於該接墊以及該第二基板上；以及 移除一部份之該絕緣層，藉此形成該絕緣層之該 凹口，且該凹口係暴露出該接墊。 21. 如申請專利範圍第17項所述之方法，其中 該基板係為一第一基板，其中形成該第一重佈導體之 步驟包括： 形成一導電凸塊於該第一基板之該主動表面上； 提供一第二基板組件，包括一第二基板、一接墊 以及一絕緣層，該接墊以及該絕緣層係相鄰地設置於 該第二基板上； 翻覆該第二基板組件，將該第二基板組件之該接 墊焊接於該第一基板之該導電凸塊，並將第二基板組 件黏合於該第一基板之該主動表面，據此於該第一基 板之該主動表面形成該第一重佈導體。 22.如申請專利範圍第21項所述之方法，其 中該導電凸塊係形成於該焊接墊上，並延伸至該貫孔 TW4682PA 29 201007914 1 W4082PA 周圍之該主動表面上。201007914 X. Patent application scope: 1. A three-dimensional conduction structure is applied to a package. The three-dimensional conduction structure includes: a substrate having an active surface and a passive surface opposite thereto. The substrate has a solder pad and is consistent a hole, the soldering pad is located on the active surface; a first redistribution conductor comprising: Φ a ridge portion 'extending outward from the substantially moving surface of the substrate' and electrically connected to the solder pad; a portion of the outer surface of the active surface and connected to the ridge, wherein the ridge portion and the receiving portion form an accommodating space, the accommodating space is in communication with the through hole; Located in the through hole and in the accommodating space 'and the second redistribution system contacts the receiving portion ′ and extends along the through hole toward the passive surface along the through hole; and Φ an insulating material, Filled between the second heavy conductor and the substrate and the second redistributing conductor and the raised portion. 2. The structure of claim 2, wherein the through hole is passed through the solder pad. 3. The structure of claim 2, wherein the raised portion is disposed on the solder pad. 4. The structure of claim 1 wherein the through hole is remote from the solder pad. 5. The structure of claim 4, wherein the TW4682PA 25 201007914 * "*t\/u2Pa ridge portion is disposed on the welding raft and extends onto the active surface around the through hole. The structure of claim 1, wherein the ridge is a conductive bump. 7. The structure of claim 1, wherein the ridge is integrally formed with the receiving portion. The structure of claim 1, wherein the substrate is a first substrate, the package further comprises a second substrate, the second substrate is located on the active surface side of the first substrate, and The structure is substantially parallel to the first substrate. The structure of claim 8, wherein the first redistribution conductor further comprises a pad disposed on the second substrate, and 10. The structure of claim 8, wherein the receiving portion contacts the second substrate. ^ 11. The structure of claim 8 wherein the first Substrate is an image sensing chip (CMOS I The second substrate is a transparent substrate. The structure of claim 8, wherein the package further comprises a third substrate disposed on the passive substrate of the first substrate. 13. The structure of claim 12, wherein the third substrate comprises a solder pad, and the solder pad is away from the passive surface of the first substrate. TW4682PA 26 201007914 TW4682PA 14. Patent application The structure of claim 12, wherein the solder pad of the third substrate is electrically connected to the solder pad of the second substrate through the first redistribution conductor and the second redistribution conductor. The structure of claim 12, wherein the third substrate is a digital signal processor (DSP). The structure of claim 8, wherein the package further comprises An insulating layer covering the first substrate and the third substrate; and a solder ball under the insulating layer and connected to the second redistributed conductor. 17. A stereo conduction structure The manufacturing method is applied to a package, the method comprising: providing a substrate having an active surface and a passive surface opposite thereto, the substrate having a soldering pad on the active surface; the active surface from the substrate Drilling to the passive surface, thereby forming a uniform hole; forming a first redistribution conductor on the active surface, the first redistribution system connecting the soldering pad and bulging outward from the active surface, thereby forming a through hole is connected to one of the accommodating spaces; an insulating material is filled in the through hole and the accommodating space; TW4682PA 27 201007914 1 W40»2PA forms a through hole in the insulating material along the through hole and the accommodating space, The via end exposes the first redistributor conductor; and a conductive material is filled in the via hole to form a second redistributor conductor contacting the first redistributor conductor. 18. The method of claim 17, wherein the substrate is a first substrate, and the step of forming the first redistribution conductor comprises: providing a second substrate assembly having a surface covered with an insulating layer, the insulation The layer has a recess exposing a turn; forming a conductive layer on the pad, the inner wall of the recess, and a portion of the insulating layer, wherein the conductive layer and the pad constitute the first redistributor conductor; Overturning the second substrate assembly, correspondingly bonding the active substrate to the active surface of the first substrate, wherein the conductive layer on the insulating layer is attached to the solder pad and will be located on the pad and the recess The conductive layer of the inner wall is opposite the via hole, and the first redistribution conductor is formed on the active surface of the first substrate. 19. The method of claim 18, wherein the providing the second substrate assembly comprises: providing a second substrate; forming a patterned metal layer on the second substrate, the patterned metal layer being at least Including a protective layer and the pad; covering an insulating layer on the protective layer, the pad and the second substrate; TW4682PA 28 201007914 1 w suppressing δ2ΡΑ removing a part of the insulating layer, thereby exposing the protective layer Etching the protective layer; and removing another portion of the insulating layer, thereby forming the recess of the insulating layer, and the recess exposes the pad. 20. The method of claim 18, wherein the step of providing the second substrate assembly comprises: providing a second substrate and forming a pad on the second substrate; covering an insulating layer a pad and the second substrate; and removing a portion of the insulating layer, thereby forming the recess of the insulating layer, and the recess exposes the pad. The method of claim 17, wherein the substrate is a first substrate, and the step of forming the first redistribution conductor comprises: forming a conductive bump on the active surface of the first substrate Providing a second substrate assembly, including a second substrate, a pad, and an insulating layer, the pad and the insulating layer are adjacently disposed on the second substrate; flipping the second substrate assembly, The pad of the second substrate assembly is soldered to the conductive bump of the first substrate, and the second substrate component is bonded to the active surface of the first substrate, thereby forming the active surface of the first substrate The first redistribution conductor. 22. The method of claim 21, wherein the conductive bump is formed on the solder pad and extends onto the active surface around the through hole TW4682PA 29 201007914 1 W4082PA. TW4682PATW4682PA
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CN103325799A (en) * 2012-03-20 2013-09-25 南茂科技股份有限公司 Chip stacking structure and manufacturing method thereof

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US4777718A (en) * 1986-06-30 1988-10-18 Motorola, Inc. Method of forming and connecting a resistive layer on a pc board
US6483101B1 (en) * 1999-12-08 2002-11-19 Amkor Technology, Inc. Molded image sensor package having lens holder
US7061106B2 (en) * 2004-04-28 2006-06-13 Advanced Chip Engineering Technology Inc. Structure of image sensor module and a method for manufacturing of wafer level package
US7045888B2 (en) * 2004-06-29 2006-05-16 Macronix International Co., Ltd. Ultra thin dual chip image sensor package structure and method for fabrication

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Publication number Priority date Publication date Assignee Title
CN103325799A (en) * 2012-03-20 2013-09-25 南茂科技股份有限公司 Chip stacking structure and manufacturing method thereof
US8809088B2 (en) 2012-03-20 2014-08-19 Chipmos Technologies Inc. Structure of stacking chips and method for manufacturing the same
TWI462266B (en) * 2012-03-20 2014-11-21 Chipmos Technologies Inc Chips stack structure and method for manufacturing the same
CN103325799B (en) * 2012-03-20 2016-12-28 南茂科技股份有限公司 Chip stacking structure and manufacturing method thereof

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