TW201004863A - Super lattice/quantum well nanowires - Google Patents

Super lattice/quantum well nanowires Download PDF

Info

Publication number
TW201004863A
TW201004863A TW98109050A TW98109050A TW201004863A TW 201004863 A TW201004863 A TW 201004863A TW 98109050 A TW98109050 A TW 98109050A TW 98109050 A TW98109050 A TW 98109050A TW 201004863 A TW201004863 A TW 201004863A
Authority
TW
Taiwan
Prior art keywords
nanowire
layer
segmented
segment
segmented nanowire
Prior art date
Application number
TW98109050A
Other languages
English (en)
Inventor
Harold J Hovel
Qiang Huang
xiao-yan Shao
James Vichiconti
George F Walker
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW201004863A publication Critical patent/TW201004863A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00Nanotechnology for materials or surface science, e.g. nanocomposites
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02Elements
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02Elements
    • C30B29/06Silicon
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10Inorganic compounds or compositions
    • C30B29/40AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10Inorganic compounds or compositions
    • C30B29/52Alloys
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/60Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape characterised by shape
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/60Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape characterised by shape
    • C30B29/605Products containing multiple oriented crystallites, e.g. columnar crystallites
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/08Etching
    • C30B33/10Etching in solutions or melts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669Nanowires or nanotubes
    • H01L29/0673Nanowires or nanotubes oriented parallel to a substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669Nanowires or nanotubes
    • H01L29/0676Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669Nanowires or nanotubes
    • H01L29/068Nanowires or nanotubes comprising a junction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/122Single quantum well structures
    • H01L29/125Quantum wire structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

Description

201004863 ' 六、發明說明: 【發明所屬之技術領域】 本發明之揭露係_包含不辭導體材料片段之奈米線及製 造此類奈米線之方法,特別是關於包含内建超晶格/量子井結構之 奈米線。 【先前技術】 由於微尺度及奈米尺度裴置組件之創新電子及光學性質(包含 源自奈米限量子機械面向之勒新物理領域),半導體奈米線逐漸引 © 起關注。材料如巨大型態(bulk form)之鍺化矽(SiGe)、應變石夕 (strained Si)、超晶格、及量子井具有獨特之性質,使此類材料可 應用於許多光學及電子裝置。 習知技術係使用化學氣相澱積法將矽奈米線於石夕基座上方晶 膜生成,如專利申請案公開號第US2〇〇7/〇222〇74 A1號所述,或 將石夕奈米線於矽基座上方之二塊狀共聚物(dibl〇ckc〇p〇lymer)所界 定之圖案樣板生成。專利申請案公開號第US2〇〇6/〇〇987〇5 A1號 〇所述之方法係藉化學氣相澱積(CVD)法於圖案矽基座上方生成矽 奈米線及量子點。專利申請案公開號第US2〇〇5/〇248〇〇3 A1號所 述之方法係藉化學氣相法形成異質接面(heter〇juncti〇n)奈米線。專 利申請案公開號第US2007/0235738 A1號所述之方法係藉化學氣 相殿積法形成具有内嵌量子之p矽/n矽奈米線接面。
钱刻均勻摻雜矽基座以形成矽奈米線之化學方法已於K Q
Peng 等人(Adv. Mater. 14(2002) 1164 ; J. Electroanal. Chem. 558(2003) 35 ; Adv. Func· Mates. 13(2003) 127。)之公開案(published 3 201004863 WWk)t有所論述。® 1顯示之示意圖係關於Peng等人如何獲得 石夕奈米線之方法。 【發明内容】 ★本發明揭露分段奈米線及製造此類分段奈雜之方法。此處 揭露^奈米線藉由於奈祕形式結合超晶格及量子絲構、創造 二維篁子井結構㈣—般二維量子井結構,具有展現更鑛物理 性質之高度可能性。 形成二或多半導體材料層之基座後,基座係藉化學蝕刻部分 移除而不使用樣板(template)。最初’化學侧始於基座表面之某 二位置。半導體材料可由特定晶面(crystal plane)而向表面定位,如 平面(111)或(110)。化學蝕刻優先沿半導體材料之晶軸 (crystallographic axis)持續’就矽而言係方向[1〇〇],致使具有不同 材料片段(其對應不同層之材料)之奈米線保持位於極少化學蝕刻 或無化學蝕刻之位置。不同片段間之介面可與分段奈米線之縱向 垂直或與其形成一角度。 揭路之化學钮刻方法係一減去(subtractive)做法,由具有二或 多不同半導體層之平面基座產生具有鍺化矽(SiGe)、鍺(Ge)量子井 結構、及石夕奈米線内之垂直接面。 【實施方式】 包含不同選替半導體層如石夕/鍺化石夕(SiGe)/石夕/鍺化石夕、石夕/緒/ 石夕/錯、或η-矽/p-石夕/η->δ夕選替層之多層基座可進行化學蝕刻處理。 蝕刻基座以形成具有内嵌量子井或超晶格結構之半導體奈米線。 4 201004863 較佳半導體為矽。尤以η摻雜及p亨雜矽為佳。特別是,此處揭 露之奈米線包含具有量子尺寸之多^選替材料。例如,以堆疊幾 何(stacked geometry)具有鍺或鍺化矽層之矽奈米線。量子井藉7吉合 矽(Si)、錯化矽(SiGe)、石夕、鍺化石夕等之選替層而獲得。結構不限 於錯化石夕;錯奈米線可結合砰化鎵(GaAs)層,石夕奈米線可結合破 化鎵(GaP)、砷磷化鎵(GaAsP)、或其他πΐ_ν或u-yj族元辛 如此幕多之料枝祕細絲_之紅,如帶 structure)修正及修正之f子性f所引起之魏增加。在某些實施例 中,奈米線-維之橫截面較另一維之橫截面小,即橫截面係姻 ❹㈣棚形。可㈣奈樣Μ段之三維允浦賴㈣子 性質。以下將列舉特定範例。 于 平線3 :包t或多層基座上之層對應自基座所獲得之奈 未線片。因此,此處使用之「分層奈米線」—詞可* 米線」-詞錢使H步,某些實施地含 ς 施例包含複數個片段。揭露草意又、實 線不可包含額外=段某數1之片段不應視為意謂分段奈米 基座上之層厚度係決定最終奈米線#段 2可依據晶膜生成參數或晶體生成參數而。已製造出 度同樣可介於丨。奈米及方料。錯切及錯層之厚 ㈣===;線形成係使用相同物基座_之化學 基座之上表面。貧又保4之邊緣以指㉘奈米線之形成乃始自 5 201004863 已透枣氟化氫-氮氧化銀(HF-AgN03)溶液蝕刻矽晶圓表面之 平面(100)而獲得矽奈米線。澱積於表面上之銀微小粒子導致某些 位置餘刻之增加;然而,在未出現銀粒子之位置上蝕刻則大大減 少。結果產生如圖3所示矽基座上眾多垂直奈米線。稍後藉酸钱 刻移除銀粒子。銀粒子移除以硝鹽酸(王水,aquaregia)為較佳。另 一較佳之酸為硝酸(nitric acid)。奈米線及基座表面不殘留反應副產 物’反應副產物會危害其他製造奈米線之方法。 在較佳實施例中’化學姓刻劑係石肖酸銀,AgN〇3) ❹及氣化氫(Mrogen fluoride,HF)水溶液之混合。氟化氫對硝酸銀 之較佳克分子比(molarratio)係120至480,而以範圍約240為更 佳。用於獲得圖3中奈米線之姓刻溶液包含1 :丨混合之3 4克/ 毫升(0.02M)确酸銀加1 : 5(4.8M)氟化氫溶液,因此氟化氫/確酸銀 水溶液之克分子比等於240。1 : 1混合之硝酸銀/氟化氫尚可稀釋 或濃縮至尚達5至10倍,且雖姓刻速率實質不同但仍形成半導體 奈米線。若溶液包含過量之硝酸銀,如氟化氫/硝’酸銀克分子比為 24,則钱刻變為平面而不導致奈米線之形成。溶液中過量之氟化 _ 氫,如氟化氫/確酸銀克分子比為2400,則不導致奈米線之形成且 矽幾乎不受蝕刻。 / 〇°C至90°C範圍之溶液溫度為較佳,而以約室溫之溫度為更 佳。溶液溫度對奈米線形成之主要影響係蝕刻速率隨溫度之增加 而增加。於溫度2(TC之標準溶液(3.4克/毫升(0.02M)硝酸銀加 5(4·8Μ)氟化氫)钱刻1〇分鐘後’可獲得長度介於〖〇至丨5微米門 201004863 奈米線之橫截面(dimension)尺寸範圍自1 〇奈米至500奈米, 且係多面而非圓形。通常一橫截面較另一橫截面小,且在某些條 件下奈米線係奈米帶(nano-ribbon)狀。#刻速率依溶液濃度、溶液 溫度、及攪動(agitation)而定。矽基座(1〇〇)於溫度2〇t:之標準溶液 (3.4克/毫升(0.02M)确酸銀加1 : 5(4.8M)氟化氫)浸入30分鐘後, 導致約3微米長之奈米線。相同之基座於溫度35。〇之標準溶液浸 入30分鐘產生約6微米長之奈米線,而相同之基座溫度5〇〇c於相 同之溶液浸入30分鐘則產生約16微米長之奈米線。當於超音波 處理槽(其提供強烈攪動)執行相同實驗’則與靜止蝕刻溶液相比之 〇餘刻速率倍升。 蝕刻速率對於半導體基座之摻雜物形式或摻雜物密度並非特 別靈敏’除對未摻雜石夕(内部石夕)外。與磷(P)、硼⑼、或砷(As)摻 雜而導致體電阻率(resistivity)0.01歐姆-公分(ohm_cm)之p型摻雜 物及體電阻率(resistivity)lOO歐姆-公分⑽取㈣之n型摻雜物,產 生之半導體奈米線具有類似長度及幾何。然而,内部石夕之活動相 當不同。内部矽(體電阻率9999歐姆-公分)之蝕刻速率較摻雜矽範 ❹例之速率慢20倍。 " 具有鍺化矽量子井之矽奈米線可藉晶膜生成矽基座上之石夕及 鍺化石夕選替層而製造。可藉晶膜生成過程(epipr_s)將層變薄, 致使鍺化石夕厚度低於臨界厚度且不發生鬆弛/缺陷。執行銀增強 (Ag-enhanced)姓刻同時,製造包含鍺化矽/石夕量子井之奈米^,如 圖3所示。已發現石夕上方之鍺化石夕層尚可以相同方式ϋ圖如 及4b分別顯不之橫截面及由上而下掃描式電子顯微鏡(聰)影 像,係使衫層基座之内嵌鍺化⑦量子點之糊⑪奈米線範^ 201004863 具有内建垂直p-n接面之矽奈米線可藉p及n摻雜物摻雜石夕基 座接著以確酸銀-狀化風溶液之化學敍刻而產生。圖5顯示具有 P:n接面矽奈米線之產生流程,而圖6顯示此範例蝕刻後之橫截面 掃描式電子顯微鏡(SEM)影像。 、 材料之選擇僅依據生成晶膜層之能力而定,且晶體生成層亦 可能有所影響。可製造此類量子奈米線之材料配對範例係石夕 鍺化矽(SiGe)、石夕 (GaAsP)、矽/硫化鋅(ZnS)、錯(Ge)/神化嫁(GaAs)、錯/石夕、錯/姻砷 霸化鎵(GalNAs)、細化鋅(驗)等。細見可於晶膜生成期間將 不同之層傳導性摻雜(c〇nductivity_d〇ped),於奈米線及量子井内產 生雷揚1。 進一步,可使用兩種以上不同材料作為絲層之材料,產生 甚至更多新的物理/材料效應。在一實施例中, 之矽/鍺化矽(SiGe)/坤化鎵(G,三片段量子層。另一;施例中, 層間提供絕緣層。限制結構本質之唯一因素係 ❹ΪΪϊΐΖ,始生成過程。再者’已藉石肖酸鹽化學侧顯 不導致不未線及1子井奈米線之增強铜,而其他化學物可展顯 類似之效應,且不同之化學物可優化以用於不同之材料組合。” 圖7顯示以平面⑽)朝向表面定位之残座。基座係以化學 蝕刻方法處理。掃描式電子顯微鏡(SEM)影 '土 _發生,即於朝向表面之60度角。辟满,優先义軸 八於尤η η人 ++ 方法獲传之奈米線具有 ”於不冋队間之“,其定位於朝向奈米線縱向之⑻度角。 201004863 ffl 8顯示以平面(ill)朝向表面定位之兩層⑦基座。基座係以 化學蝕刻方法處理。 —· 圖9顯不之掃描式電子顯微鏡(SEM)影像揭示賴優先沿軸 [1〇〇]發生’即奈米線定也於朝向表面之547度角。藉此方法獲得 之奈米線具有介於不同片段間之介面,其定餘朝向奈米線縱向 之54.7度角。 ® 10顯示之上下圖式係自平面(111)侧之基座所獲得之石夕 β ί倍放*。侧係使用原始之標準溶液於溫度耽執 圖11顯示之側視圖式係自平面(111)钱刻之基座所獲得之石夕 奈米線5_倍放大,奈米線與基座形成—54J度角。 之詞係概括複數及單數 此處所使用「包含」-詞(及其文法上之變異)係敘述「具有 (或「包含(induding)」之函括意思,轉「僅包含(咖㈣ ❹〇'y 〇f)」之排除意思。應了解此處所使用「一⑻」及「該(㈣」 而法H 有公開文件、專觀專利申請案藉引用 各之Γ部,且因任何及所有目的’如嚼红個別指定 t開文件、翻及專利申請絲個而成為本文之—部。 不—致之處,則以本發明之揭露為主。 9 201004863 一巧,露之詳猶示並_本發明之揭露。另外,揭露僅顯 不並說明錄實施例’但如上所述,應了解揭露可驗不同之其 他組合、修正、及魏,且财於此處所麻概紅細内加^ 改變或Ljl ’ #合上列揭示及/或相關技術之技術或知識。 ,上述實施例進-步欲_執行之已知最佳模式,且欲致使此 =領域具有通常知識者以此類或其他實補及特定應用或用途 所^不哪正*實簡露。因此,詳述不欲_於此處所揭露 之形式。再者’應轉峨之申請專繼_包含觀之實施例。 【圖式簡單說明】 ^顯示_技術方法於發晶圓上製造經蝴、未分段梦奈 未線之不意圖。 圖2顯示藉化學餘刻石夕基座⑽)而形成石夕奈米線之掃描 子顯微鏡(SEM)橫截面圖。 面示=顯不具餘合(⑻卿㈣好井之分縣米線之橫截
圖4a及4b顯示由化學餘刻所形成之石夕/錯化石夕/石夕奈米線之橫 截面及由上而下掃描式電子顯微鏡(SEM)影像。 圖5顯示具有垂直p_n接面之奈米線處理之示意圖。 截面=顯示根據圖5示意圖處理之具有垂直Ρ·η接面奈米線之橫 圖7 及Ρ摻雜 方向。 顯示自平面(110)触刻之基座所獲得之石夕奈米線,η摻雜 片段與奈米線縱向形成—60度角,賊應於⑪⑽)晶體 圖δ顯示之上至下圖式係自平面(1丨丨)蝴之基座所獲得之石夕 201004863 ’ 奈米線500倍放大。 ’ 圖9顯示之側視掃描式電子顯微鏡(SEM)影像係自平面(lu) 蝕刻之基座所獲得之碎奈米線1〇,〇〇〇倍放大’奈米線與基座形成 一 54.7度角。 圖10顯示之上至下圖式係自平面(111)餘刻之基座所獲得之 碎奈米線1,000倍放大。 圖11顯示之侧視圖式係自平面(111)蚀刻所獲得之矽奈来線 5,000倍放大掃描式電子顯微鏡(SEM)影像,奈米線與基座形成— 54.7度角。 Φ 【主要元件符號說明】

Claims (1)

  1. 201004863 七、申請專利範圍: 1. 一種獲得一分段奈米線之方法,其包含: ’ 一 …自-層狀結構部分移除-第—材料及與該第—材料不同之一 第二材料’其中該層狀結構係包含該第—材料及該第二材料 以獲得具有該第—材料—片段及該第二材料—片段之該分段奈^ 線。 、 2. 如申請專利範圍第丨項所述之方法,其中該部分移除包含化學钱 刻。 3·如申請專繼圍第2項職之方法,其巾該辨侧包含施加— 氟化氫/硝酸銀溶液。 4. 如申請專利範圍第2項所述之方法,其中該化學蝕刻主要沿該第 材料或该第一材料之一晶軸(cryStau〇graphic狀的方向發生。 5. 如申請專利範圍第4項所述之方法,其中該化學蝕刻主要沿晶軸 ❹方向[100]發生。 6. 如申請專利範圍第1項所述之方法,其中該第一材料係n摻雜矽 且該第二材料係ρ摻雜矽,或該第一材料係ρ摻雜矽且該第二材 料係η摻雜矽。 7·如申請專利範圍第1項所述之方法,其中該層狀結構包含至少二 不同材料之複數層。 12 201004863 8. 如中請專祕S1第1項所述之方法,其中該分段奈米線係一分段 奈米帶(nano-ribbon) 〇 、 9. 如申請專舰®帛1酬叙料,其t該分段奈錄具有一多 面表面。 10.如申請專利範圍第1項所述之方法,其中該第—材料及該第二 材料係選自包含石夕、鍺化石夕(siGe)、填化錄(Gap)、神填化嫁 (GaAsP)、硫化鋅(ZnS)、錯(Ge)、魏錯(Ge岭辦化鎵(GainAs) ^ 及硒化鋅(ZnSe)之群組。 包含獲得根據 11.一種製造-電子、光學、及熱電子裝置之方法 申明專利範圍第1項之一分段奈米線。 I2.一種獲得一分段奈米線之方法,其包含: 形成一第一材料之一第一層; 1成與該第-材料不同且與該第—材料相鄰之—第二材料之 〇 —第二層;以及 一=分移除該第一材料及第二材料,藉以獲得具有該第一材料 片段及該第二材料一片段之一分段奈米線。 請專利範圍第12項所述之方法,其中該® —層或該第二層 係包含晶膜生成(epitaxial growth)。 請專利範圍第12項所述之方法,其中該第一層或該第二層 ^成係包含澱積一多晶態材料。 13 201004863 ’其進一步包含於該部分移 15.如申請免利範圍第12項所述之方法 除前形成至少二不同材料之複數層。 16.如申請專利範圍第12項所述之方法,其中該第一材料及該第二 材料係選自包含矽(si)、鍺化矽(SiGe)、磷化鎵(GaP)、砷磷化鎵 (GaAsP)、硫化鋅(ZnS)、鍺(Ge)、砷化鍺(GeAs)、銦砷化鎵(GaInAs) 及砸化鋅(ZnSe)之群組。 Π.—種製造一電子、光學、或熱電子裝置之方法,係包含獲得根 ® 據申請專利範圍第12項之一分段奈米線。 18.—種包含一第一材料第一片段、及一第二材料第二片段之分段 奈米線,其中該第一片段及該第二片段間之一介面係定位於朝向 該分段奈米線縱向之一角度。 19.一種包含根據申請專利範圍第18項之分段奈米線之太陽能電 池。 20·—種包含根據申請專利範圍第18項之分段奈米線之垂直空腔 表面發光雷射、一發光二極體、或一光電裝置。 14
TW98109050A 2008-03-25 2009-03-20 Super lattice/quantum well nanowires TW201004863A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/054,886 US8273591B2 (en) 2008-03-25 2008-03-25 Super lattice/quantum well nanowires

Publications (1)

Publication Number Publication Date
TW201004863A true TW201004863A (en) 2010-02-01

Family

ID=41114260

Family Applications (1)

Application Number Title Priority Date Filing Date
TW98109050A TW201004863A (en) 2008-03-25 2009-03-20 Super lattice/quantum well nanowires

Country Status (6)

Country Link
US (2) US8273591B2 (zh)
EP (1) EP2257968A4 (zh)
JP (1) JP2011519730A (zh)
KR (1) KR20100127249A (zh)
TW (1) TW201004863A (zh)
WO (1) WO2009120404A1 (zh)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0601319D0 (en) 2006-01-23 2006-03-01 Imp Innovations Ltd A method of fabricating pillars composed of silicon-based material
GB0709165D0 (en) 2007-05-11 2007-06-20 Nexeon Ltd A silicon anode for a rechargeable battery
GB0713896D0 (en) 2007-07-17 2007-08-29 Nexeon Ltd Method
GB0713898D0 (en) 2007-07-17 2007-08-29 Nexeon Ltd A method of fabricating structured particles composed of silcon or a silicon-based material and their use in lithium rechargeable batteries
GB0713895D0 (en) 2007-07-17 2007-08-29 Nexeon Ltd Production
JP2011523902A (ja) 2008-04-14 2011-08-25 バンドギャップ エンジニアリング, インコーポレイテッド ナノワイヤアレイを製造するためのプロセス
KR20100028412A (ko) * 2008-09-04 2010-03-12 삼성전자주식회사 나노 막대를 이용한 발광 다이오드 및 그 제조 방법
GB2464157B (en) 2008-10-10 2010-09-01 Nexeon Ltd A method of fabricating structured particles composed of silicon or a silicon-based material
GB2464158B (en) 2008-10-10 2011-04-20 Nexeon Ltd A method of fabricating structured particles composed of silicon or a silicon-based material and their use in lithium rechargeable batteries
TWI379430B (en) * 2009-04-16 2012-12-11 Atomic Energy Council A method of fabricating a thin interface for internal light reflection and impurities isolation
FR2944783B1 (fr) * 2009-04-28 2011-06-03 Commissariat Energie Atomique Procede d'elaboration de nanofils de silicium et/ou de germanium.
GB2470056B (en) 2009-05-07 2013-09-11 Nexeon Ltd A method of making silicon anode material for rechargeable cells
GB2470190B (en) 2009-05-11 2011-07-13 Nexeon Ltd A binder for lithium ion rechargeable battery cells
US9853292B2 (en) 2009-05-11 2017-12-26 Nexeon Limited Electrode composition for a secondary battery cell
GB201005979D0 (en) 2010-04-09 2010-05-26 Nexeon Ltd A method of fabricating structured particles composed of silicon or a silicon-based material and their use in lithium rechargeable batteries
GB201009519D0 (en) 2010-06-07 2010-07-21 Nexeon Ltd An additive for lithium ion rechargeable battery cells
GB201014706D0 (en) 2010-09-03 2010-10-20 Nexeon Ltd Porous electroactive material
GB201014707D0 (en) 2010-09-03 2010-10-20 Nexeon Ltd Electroactive material
US20120181502A1 (en) 2011-01-18 2012-07-19 Bandgap Engineering, Inc. Method of electrically contacting nanowire arrays
GB201113464D0 (en) * 2011-08-03 2011-09-21 Sunflake As Nanostructure, nanostructure fabrication method and photovoltaic cell incorporating a nanostructure
US10049871B2 (en) 2013-02-06 2018-08-14 President And Fellows Of Harvard College Anisotropic deposition in nanoscale wires
WO2015171699A1 (en) 2014-05-07 2015-11-12 President And Fellows Of Harvard College Controlled growth of nanoscale wires
WO2015191847A1 (en) * 2014-06-13 2015-12-17 President And Fellows Of Harvard College Facet-selective growth of nanoscale wires
US9343529B2 (en) 2014-09-05 2016-05-17 International Business Machines Corporation Method of formation of germanium nanowires on bulk substrates
US9607900B1 (en) * 2015-09-10 2017-03-28 International Business Machines Corporation Method and structure to fabricate closely packed hybrid nanowires at scaled pitch
JP6339230B2 (ja) 2015-10-09 2018-06-06 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. 半導体装置
WO2017064793A1 (ja) 2015-10-15 2017-04-20 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置
CN108352400B (zh) 2015-10-30 2021-09-10 佛罗里达大学研究基金会有限公司 包封的纳米结构及其制造方法
US10312081B2 (en) 2016-07-15 2019-06-04 University Of Kentucky Research Foundation Synthesis of metal oxide surfaces and interfaces with crystallographic control using solid-liquid-vapor etching and vapor-liquid-solid growth

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05175123A (ja) * 1991-06-20 1993-07-13 Sanyo Electric Co Ltd 半導体装置の製造方法
JP3243303B2 (ja) * 1991-10-28 2002-01-07 ゼロックス・コーポレーション 量子閉じ込め半導体発光素子及びその製造方法
US6294450B1 (en) * 2000-03-01 2001-09-25 Hewlett-Packard Company Nanoscale patterning for the formation of extensive wires
US7301199B2 (en) 2000-08-22 2007-11-27 President And Fellows Of Harvard College Nanoscale wires and related devices
EP1374310A4 (en) 2001-03-14 2008-02-20 Univ Massachusetts NANOFABRICATION
KR101008294B1 (ko) * 2001-03-30 2011-01-13 더 리전트 오브 더 유니버시티 오브 캘리포니아 나노구조체 및 나노와이어의 제조 방법 및 그로부터 제조되는 디바이스
US6656573B2 (en) * 2001-06-26 2003-12-02 Hewlett-Packard Development Company, L.P. Method to grow self-assembled epitaxial nanowires
JP2003101069A (ja) * 2001-09-25 2003-04-04 Nagoya Industrial Science Research Inst Iii族窒化物量子ドットおよびその製造方法
US6773616B1 (en) * 2001-11-13 2004-08-10 Hewlett-Packard Development Company, L.P. Formation of nanoscale wires
US7192533B2 (en) * 2002-03-28 2007-03-20 Koninklijke Philips Electronics N.V. Method of manufacturing nanowires and electronic device
US6872645B2 (en) 2002-04-02 2005-03-29 Nanosys, Inc. Methods of positioning and/or orienting nanostructures
JP3844443B2 (ja) * 2002-04-12 2006-11-15 新日本製鐵株式会社 海底光ファイバーケーブル補強用異形線
KR100481209B1 (ko) * 2002-10-01 2005-04-08 삼성전자주식회사 다중 채널을 갖는 모스 트랜지스터 및 그 제조방법
US7211143B2 (en) 2002-12-09 2007-05-01 The Regents Of The University Of California Sacrificial template method of fabricating a nanotube
US7181836B2 (en) * 2003-12-19 2007-02-27 General Electric Company Method for making an electrode structure
WO2005079308A2 (en) 2004-02-17 2005-09-01 New Jersey Institute Of Technology One dimensional nanostructures for vertical heterointegration on a silicon platform and method for making same
US7105428B2 (en) * 2004-04-30 2006-09-12 Nanosys, Inc. Systems and methods for nanowire growth and harvesting
US20050279274A1 (en) * 2004-04-30 2005-12-22 Chunming Niu Systems and methods for nanowire growth and manufacturing
CN1957477A (zh) 2004-05-26 2007-05-02 皇家飞利浦电子股份有限公司 具有垂直部件的电子器件
KR100647288B1 (ko) 2004-09-13 2006-11-23 삼성전자주식회사 나노와이어 발광소자 및 그 제조방법
US7307271B2 (en) 2004-11-05 2007-12-11 Hewlett-Packard Development Company, L.P. Nanowire interconnection and nano-scale device applications
US7400665B2 (en) 2004-11-05 2008-07-15 Hewlett-Packard Developement Company, L.P. Nano-VCSEL device and fabrication thereof using nano-colonnades
WO2006060599A2 (en) * 2004-12-02 2006-06-08 The Regents Of The University Of California Semiconductor devices based on coalesced nano-rod arrays
JP2006239857A (ja) * 2005-02-25 2006-09-14 Samsung Electronics Co Ltd シリコンナノワイヤ、シリコンナノワイヤを含む半導体素子及びシリコンナノワイヤの製造方法
US20060207647A1 (en) * 2005-03-16 2006-09-21 General Electric Company High efficiency inorganic nanorod-enhanced photovoltaic devices
WO2006101659A2 (en) * 2005-03-17 2006-09-28 The George Washington University Method of making nanoparticle wires
KR100594327B1 (ko) * 2005-03-24 2006-06-30 삼성전자주식회사 라운드 형태의 단면을 가지는 나노와이어를 구비한 반도체소자 및 그 제조 방법
GB0601318D0 (en) * 2006-01-23 2006-03-01 Imp Innovations Ltd Method of etching a silicon-based material
JP2007214260A (ja) * 2006-02-08 2007-08-23 Matsushita Electric Ind Co Ltd 半導体発光素子およびその製造方法

Also Published As

Publication number Publication date
US8273591B2 (en) 2012-09-25
EP2257968A4 (en) 2014-05-07
KR20100127249A (ko) 2010-12-03
US20120286236A1 (en) 2012-11-15
JP2011519730A (ja) 2011-07-14
US8878259B2 (en) 2014-11-04
US20090242869A1 (en) 2009-10-01
EP2257968A1 (en) 2010-12-08
WO2009120404A1 (en) 2009-10-01

Similar Documents

Publication Publication Date Title
TW201004863A (en) Super lattice/quantum well nanowires
Kim et al. Position‐and morphology‐controlled ZnO nanostructures grown on graphene layers
TWI455182B (zh) 第四族基板表面上的氮化物半導體裝置夾層架構
US8207521B2 (en) Method for producing catalyst-free single crystal silicon nanowires, nanowires produced by the method and nanodevice comprising the nanowires
CN104904016B (zh) 具有过渡金属缓冲层的包含纳米线电子器件、至少一个纳米线的生长方法以及器件制造方法
Chung et al. Transferable single-crystal GaN thin films grown on chemical vapor-deposited hexagonal BN sheets
CN104871317B (zh) 从在两个步骤中获得的氮化过渡金属层生长至少一个纳米线的方法
JP2005123619A (ja) シリコン基板上に形成された窒化物半導体及びその製造方法
TW200941559A (en) Semiconductor substrate and method of making same
Kim et al. Fabrication of full-color GaN-based light-emitting diodes on nearly lattice-matched flexible metal foils
US11131039B2 (en) Diamond on nanopatterned substrate
TWI645454B (zh) 磊晶基板及其製造方法
TW201248920A (en) Light emitting diode element and method for fabricating the same
Wurm et al. Demonstration of device-quality 60% relaxed In0. 2Ga0. 8N on porous GaN pseudo-substrates grown by PAMBE
Tan et al. Highly uniform zinc blende GaAs nanowires on Si (111) using a controlled chemical oxide template
Sivakov et al. Silicon nanowire oxidation: the influence of sidewall structure and gold distribution
Wang et al. Enhancement of p-type conductivity of monolayer hexagonal boron nitride by driving Mg incorporation through low-energy path with N-rich condition
JP2020105038A (ja) 半導体基板、半導体基板の製造方法およびそれを用いた半導体装置
Ansah-Antwi et al. Growth optimization and characterization of GaN epilayers on multifaceted (111) surfaces etched on Si (100) substrates
Seo et al. The size and diffusion effect of gold on silicon nanowire sidewall faceting
TW201718930A (zh) 具有經減低之線差排密度的基材之製造方法
US20140202378A1 (en) METHOD FOR PRODUCING AN ORGANISED NETWORK OF SEMICONDUCTOR NANOWIRES, IN PARTICULAR MADE OF ZnO
TW200832739A (en) Method of forming GaN substrate
Iwabuchi et al. Dependence of epitaxial layer defect morphology on substrate particle contamination of Si epitaxial wafer
Leu et al. Oxide-encapsulated vertical germanium nanowire structures and their DC transport properties