TW201003806A - Chip package structure - Google Patents

Chip package structure Download PDF

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Publication number
TW201003806A
TW201003806A TW97126666A TW97126666A TW201003806A TW 201003806 A TW201003806 A TW 201003806A TW 97126666 A TW97126666 A TW 97126666A TW 97126666 A TW97126666 A TW 97126666A TW 201003806 A TW201003806 A TW 201003806A
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TW
Taiwan
Prior art keywords
substrate
adhesive layer
package structure
wafer
stage
Prior art date
Application number
TW97126666A
Other languages
Chinese (zh)
Inventor
Geng-Shin Shen
Wei-David Wang
Original Assignee
Chipmos Technologies Inc
Chipmos Technologies Bermuda
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Chipmos Technologies Inc, Chipmos Technologies Bermuda filed Critical Chipmos Technologies Inc
Priority to TW97126666A priority Critical patent/TW201003806A/en
Publication of TW201003806A publication Critical patent/TW201003806A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors

Abstract

A chip package structure including a first substrate, a second substrate, a plurality of bumps, a first B-staged adhesive layer and a second B-staged adhesive layer is provided. The first substrate has a plurality of first bonding pads. The second substrate has a plurality of second bonding pads, and the second substrate is disposed above the first substrate. The bumps are disposed between the first substrate and the second substrate, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps. The first B-staged adhesive layer is adhered on the first substrate. The second B-staged adhesive layer is adhered between the first B-staged adhesive layer and the second substrate, wherein the first B-staged adhesive layer and the second B-staged adhesive layer encapsulate the bumps.

Description

201003806 --------tU01-t 17063-OPtwf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種晶片封裝結構，且特別是有關於 一種具有較佳可靠度的晶片封裝結構。 、 - 【先前技術】 隨著積體電路的輸入/輸出接點的增多，晶片封裝技術 變得越來越多樣化。這歸因於覆晶（Flip Chip)互^技術 極小化晶片封裝尺寸並減少信號傳輸路徑等的事實。應用 1 覆晶互連技術的最常用的晶片封裝結構包括諸如覆晶^柵 格陣列（Flip Chip Ball Grid Array)及覆晶針腳柵格陣列 (Flip Chip Pin Grid Array)等晶片封裝結構。 覆晶互連技術採用這樣一種方法，即通過在晶片的主 動表面上設置多個焊塾，並在這些焊墊上分別形成多個凸 塊’來界定區域陣列。接著，將晶片翻覆，以分別連接晶 j #的谭接凸塊與設置在諸如電路基板的承載n上的多個接 觸墊。因此，晶片通過凸塊電性連接並機械連接至承載器。 另外，晶片可通過承載器的内部電路電性連接至外部電子 裝置通#，凸塊具有若干種類型，例如焊料凸塊、金凸 塊、銅凸塊、導電高分子凸塊、高分子凸塊等。 &圖1為具有高分子凸塊的晶片封裝結構的剖面示意 .圖二請參考圖卜晶片封裝結構100包括第一基板110、多 . 個阿分子凸塊U0、晶片130與焊料140。第一基板110 具有表面ll〇a，在表面u〇a上設置有多個接觸墊112。晶 5 201003806 .001-t 17063-OPtwf.doc/n 片130具有主動表面130a，在主動表面13〇&上設置有多 個焊墊132。由具有導電特性的高分子材料製成的高分子 凸塊120分別設置在接觸墊112與焊墊132之間，以電性 連接基板110與曰曰曰片130。由於高分子凸塊12〇並不附著 .=接觸墊112，因此需要焊料140來將高分子凸塊12〇固 - 定在基板U0上。焊料的表面A附著於接觸墊ιι2， 且其表面B附著於高分子凸塊12〇。因此，當晶片封裝結 1 構受到外力或熱應力（未圖示）之作用時，焊料140^^ 接觸墊112上脫離，且高分子凸塊12〇將不再電性連&至 接觸墊112。顯然地，晶片封裝結構卿的可靠度較低。 【發明内容】 本發明提供一種可靠度獲得提昇的晶片封裝結構。 —本發明提出一種晶片封裝結構，其包括一第—基板、 一第二基板、多個凸塊、一第一B階黏著層及一第:B階 黏著層。第-基板具有多個第一焊塾。第二基板具有多^ 第一焊墊且第一基板設置於第一基板的上方。這些凸塊設 置於第-基板與第二基板之間，其中各第一焊 其^一凸塊與對應之第二焊塾電性連接。第一 B階== 黏者於第一基板上。第二B階黏著層黏著於第—β階黏著 層與第二基板之間，其中第一 B階黏著層與第二B階黏著 層包覆這些凸塊。第-B階黏著層與第二B階黏著層皆可 為整層的黏著層或是圖案化的黏著層。 θ 在本發明之-實施例中，上述之凸塊包括結線凸塊或 201003806 ….....'jOOl-t 17〇63-〇Ptwf.doc/n 電鍍凸塊。 在本發明之一實施例中，上述之第一 B 二B階黏著層為非導電。 者層/、第 夕在本發明之一實施例中，上述之第一B階黏 ί 1:!:B: J著塊，且第二B階黏著層包括多個i二b ^者在另-可行的實施例中，當第二 Γ li 導電或非導電’第-B階黏著層轉電。在另鬼為 JJ…黏著塊為導電或非導電，第一 6階“： 之—實施例中，上述之第—基板與第二基板 J白句a曰乃。 有-ϊϊϊγγ實施例中，上述之第—基板與第二基板 餘轉實Γ中’上述之第一Β階黏著層的玻 ，於、等於或低於第二Β_著層的玻璃轉 在本發明之一實施例中，上述之 工器，線’其中第—基板與第二 且弟-基板透過這些焊線而電性連接至承載器。 之實施例中，上述 二固層的尺寸。此外’第-B階黏著層包 括多個弟一 B階黏著塊。 承上述，本發明之晶片封袭結構利用—第一 与與一第二B階黏著層包覆設置於第—基板與第二基板之 7 201003806 l^t 17063-OPtwf.doc/n 間的凸塊。當-外力或熱應力作用於晶片封裝結構時，第 二B _著層與第二B P綠著層可分職供支収保護， 亚防止凸塊損壞’以使得晶片封裝結構的可靠度獲得進一 步的提高。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 - 舉較佳實施例，並配合所_式，作詳細說明如下。 【實施方式】 圖2A及圖2B為本發明之一實施例之晶片封裝結構的 剖面示意圖。請參考圖2A及圖2B，本發明之晶片封裝結 構200包括一第一基板21〇、一第二基板22〇、多個凸塊 230a (繪示於圖2A)或23〇b (繪示於圖2B)、一第一 b 階黏著層240a及一第二b階黏著層24%。第一基板21〇 具有多個第-焊塾212。第二基板220具有多個第二焊塾 222且第二基板22〇設置於第一基板21〇的上方。凸塊 230a、230b設置於第一基板210與第二基板22〇之間，其 夕 中各第一焊墊212分別透過其中一凸塊23〇a、230b與對應 ，第二焊墊222電性連接。第一 B階黏著層24〇a黏著於 第一基板210上。第二B階黏著層24〇b黏著於第一 6階 黏著層2術與第二基板22〇之間，其中第一 b階黏著層 240a與第二B階黏著層24〇b包覆凸塊230a、230b。此外， . 第一 B階黏著層240a的構成成份可不同於或實質上等同 - 於第二B階黏著層240b的構成成份。如圖2A及圖2B所 示’第一 B階黏著層24〇a黏著於第一基板210的表面si 8 201003806 -------->ϋ01 -t 17063-OPtwf.doc/n 上且第=B階黏著層2働黏著於第二基板22〇的表面幻 上。值付注意的是’本發明利用第一 B階黏著層2伽愈 第二B階黏著層2她加強第一基板21〇及第二基板22〇 ^間的黏著性’並可分職供支撐及保護，以防止凸塊損201003806 --------tU01-t 17063-OPtwf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a chip package structure, and particularly relates to a Good reliability of the chip package structure. - [Prior Art] As the input/output contacts of integrated circuits increase, chip packaging technology becomes more diverse. This is attributed to the fact that Flip Chip technology minimizes the size of the chip package and reduces the signal transmission path and the like. Applications 1 The most common chip package structures for flip chip interconnect technology include wafer package structures such as Flip Chip Ball Grid Arrays and Flip Chip Pin Grid Arrays. The flip chip interconnection technique employs a method of defining an array of regions by providing a plurality of solder bumps on the active surface of the wafer and forming a plurality of bumps ' on each of the pads. Next, the wafer is flipped over to connect the tan bumps of the crystal j and the plurality of contact pads provided on the carrier n such as a circuit substrate, respectively. Thus, the wafer is electrically connected by bumps and mechanically coupled to the carrier. In addition, the wafer can be electrically connected to the external electronic device through the internal circuit of the carrier, and the bump has several types, such as solder bumps, gold bumps, copper bumps, conductive polymer bumps, polymer bumps. Wait. 1 is a schematic cross-sectional view of a wafer package structure having polymer bumps. FIG. 2 is a reference to the wafer package structure 100 including a first substrate 110, a plurality of molecular bumps U0, a wafer 130, and a solder 140. The first substrate 110 has a surface 11a, and a plurality of contact pads 112 are disposed on the surface u〇a. Crystal 5 201003806 .001-t 17063-OPtwf.doc/n Sheet 130 has an active surface 130a on which a plurality of pads 132 are disposed. The polymer bumps 120 made of a polymer material having conductive properties are respectively disposed between the contact pads 112 and the pads 132 to electrically connect the substrate 110 and the die 130. Since the polymer bump 12 does not adhere to the contact pad 112, the solder 140 is required to fix the polymer bump 12 to the substrate U0. The surface A of the solder adheres to the contact pad ι 2 and the surface B thereof adheres to the polymer bump 12 〇. Therefore, when the wafer package structure is subjected to external force or thermal stress (not shown), the solder 140 is detached from the contact pad 112, and the polymer bumps 12 不再 will no longer be electrically connected to the contact pads. 112. Obviously, the reliability of the chip package structure is low. SUMMARY OF THE INVENTION The present invention provides a chip package structure with improved reliability. The present invention provides a chip package structure including a first substrate, a second substrate, a plurality of bumps, a first B-stage adhesive layer, and a B-stage adhesive layer. The first substrate has a plurality of first solder pads. The second substrate has a plurality of first pads and the first substrate is disposed above the first substrate. The bumps are disposed between the first substrate and the second substrate, wherein each of the first solder bumps is electrically connected to the corresponding second solder bump. The first B-order == sticks to the first substrate. The second B-stage adhesive layer is adhered between the first-stage adhesion layer and the second substrate, wherein the first B-stage adhesive layer and the second B-stage adhesive layer cover the bumps. The first-B adhesive layer and the second B-th adhesive layer may be an entire adhesive layer or a patterned adhesive layer. θ In the embodiment of the invention, the bumps described above comprise junction bumps or 201003806 . . . 'jOOl-t 17〇63-〇Ptwf.doc/n plated bumps. In an embodiment of the invention, the first B B-stage adhesive layer is non-conductive. In one embodiment of the present invention, the first B-th order sticky ί 1:!: B: J is block-shaped, and the second B-stage adhesive layer includes a plurality of i-two b ^ in another - In a possible embodiment, when the second Γ li is electrically conductive or non-conductive, the -B-stage adhesive layer is electrically switched. In the other six-stage ":", in the embodiment, the first substrate and the second substrate J are in the embodiment. In the embodiment of the -ϊϊϊγγ, the above The first substrate-to-substrate and the second substrate are in the form of a glass of the first first-order adhesive layer, and the glass is equal to or lower than the second layer of the second layer. In one embodiment of the present invention, the above In the embodiment, the first substrate and the second substrate are electrically connected to the carrier through the bonding wires. In the embodiment, the size of the two solid layers is further included. The 'B-B adhesive layer includes In the above, the wafer encapsulation structure of the present invention utilizes a first and a second B-stage adhesive layer to be disposed on the first substrate and the second substrate. 201003806 l^t 17063 -OPtwf.doc/n bumps. When external force or thermal stress acts on the chip package structure, the second B_layer and the second BP green layer can be divided for protection and protection, and the bumps are prevented from being damaged. 'To further improve the reliability of the chip package structure. To make the above features of the present invention The point can be more clearly understood, and the following is a detailed description of the preferred embodiment and the following description. [Embodiment] FIG. 2A and FIG. 2B are schematic cross-sectional views showing a wafer package structure according to an embodiment of the present invention. Referring to FIG. 2A and FIG. 2B, the chip package structure 200 of the present invention includes a first substrate 21A, a second substrate 22A, a plurality of bumps 230a (shown in FIG. 2A) or 23〇b (illustrated 2B), a first b-stage adhesive layer 240a and a second b-stage adhesive layer 24%. The first substrate 21 has a plurality of first solder pads 212. The second substrate 220 has a plurality of second solder pads 222. The second substrate 22 is disposed above the first substrate 21〇. The bumps 230a and 230b are disposed between the first substrate 210 and the second substrate 22, and each of the first pads 212 passes through one of the convex portions 212 The blocks 23A, 230b are electrically connected to the second pads 222. The first B-stage adhesive layer 24A is adhered to the first substrate 210. The second B-stage adhesive layer 24A is adhered to the first 6th stage. Between the adhesive layer 2 and the second substrate 22, wherein the first b-stage adhesive layer 240a and the second B-stage adhesive layer 24〇b cover the bumps 230a, 230b. The composition of the first B-stage adhesive layer 240a may be different from or substantially equivalent to the constituent components of the second B-stage adhesive layer 240b. As shown in FIGS. 2A and 2B, the first B-stage adhesive layer 24〇 a adhered to the surface of the first substrate 210, si 8 201003806 --------> ϋ01 -t 17063-OPtwf.doc/n and the second layer B of the adhesive layer 2 is adhered to the second substrate 22 The surface is illusory. It is noted that the present invention utilizes the first B-stage adhesive layer 2 to garnish the second B-stage adhesive layer 2 to enhance the adhesion between the first substrate 21 and the second substrate 22 并可 and Separate for support and protection to prevent bump damage

. 壞，使得晶片封裝結構的可靠度可被提高，另，該第一 B '階黏著層2他與第二B階黏著層24Gb皆可為圖案化的黏 著層。 ^如圖2A及圖2B所示，在本實施例中，第一 B階黏 著層240a的厚度實質上等於第二B階黏著層2働的厚 度。然而，基於實際設計需求，第一 B階黏著層24〇a的 厚度也可不同於第二B階黏著層24〇b的厚度。 第一基板210包括多個設置於其具有之表面S1上的 夕個焊墊212。第二基板220設置於第一基板21〇的上方 且亦包括多個設置於其具有之表面S2上的多個焊墊222。 根據本實施例，第一基板21〇與第二基板22〇可皆為晶片。 在本發明之另一實施例中，第一基板21〇與第二基板22〇 其中之一者為晶片。在本發明中，第一基板210與第二基 板220的型式不被限定。凸塊230a、230b設置於第一焊塾 212與第二焊墊222之間。特別的是，各凸塊23〇a、23〇b 的上端與第二焊墊222接觸且各凸塊230a、230b的下端與 第一焊墊212接觸。 • 在本實施例中’凸塊為結線凸塊230a (如圖2A所The reliability of the chip package structure can be improved. Further, the first B'-stage adhesive layer 2 and the second B-stage adhesive layer 24Gb can be patterned adhesive layers. As shown in Figs. 2A and 2B, in the present embodiment, the thickness of the first B-stage adhesive layer 240a is substantially equal to the thickness of the second B-stage adhesive layer 2A. However, based on actual design requirements, the thickness of the first B-stage adhesive layer 24〇a may also be different from the thickness of the second B-stage adhesive layer 24〇b. The first substrate 210 includes a plurality of pads 212 disposed on the surface S1 thereof. The second substrate 220 is disposed above the first substrate 21A and also includes a plurality of pads 222 disposed on the surface S2 thereof. According to the embodiment, the first substrate 21 and the second substrate 22 can both be wafers. In another embodiment of the invention, one of the first substrate 21 and the second substrate 22 is a wafer. In the present invention, the types of the first substrate 210 and the second substrate 220 are not limited. The bumps 230a, 230b are disposed between the first pad 212 and the second pad 222. In particular, the upper ends of the bumps 23a, 23b are in contact with the second pad 222 and the lower ends of the bumps 230a, 230b are in contact with the first pad 212. • In this embodiment, the bump is a junction bump 230a (as shown in Figure 2A).

- 示）’且結線凸塊230a可為金結線凸塊或銅結線凸塊。在 本發明之另一實施例中，凸塊可為電鍍凸塊230b(如圖2B 9 201003806 .....J〇〇l-t 17063-OPtwf.doc/n 所示)胃。電鍍凸塊230b可為金凸塊、銅凸塊、焊錫凸塊或 其他‘電凸塊。各結線凸塊230a或各電鍍凸塊230b被各 黏著塊240a’包覆。 根據本實施例，第一 B階黏著層24〇a包括多個第一 B - 階黏^塊240a’，且第二B階黏著層240b包括多個第二B ' 階黏著塊240b’’其中第一 B階黏著塊240a，黏著於第一基 板210的表面si上且第二b階黏著塊24〇b，黏著於第二基 板2ω的表面S2上。在本實施例中，當第二8階黏著塊 24=’為導電或非導電，第—Β階黏著塊240a，為導電或非 =¾。由於第一 B階黏著塊240a，彼此之間為電性絕緣且 第一 B階黏著塊240b’彼此之間為電性絕緣，故即使第一 B階黏著塊240a’與第二B階黏著塊240b，皆為導電，仍可 防止凸塊230a、230b之間的短路。 朴在本實施例中，第一 B階黏著層240a與第二B階黏 著層240b可為ABLESTIK的8008或8008HT，且其玻璃 轉換溫度(Tg)大約介於攝氏八十度麟氏三百度之間。此 〇 外，第一 B階黏著層240a與第二b階黏著層24〇b亦可為 ABLESTIK 的 6200、62(H、6202C 或 HITACHI Chemical CO.，Ltd.提供的SA_200_6、SA_2〇〇_1〇，且其玻璃轉換溫度 (Tg)大約介於攝氏負四十度與攝氏一百五十度之間。第: B 黏著層24Ga的玻璃轉換溫度(项可大於、等於或小於 第二B階黏著層240b的玻璃轉換溫度(Tg)。此外，例如可 將一些導電粒子（如銀粒子、銅粒子及金粒子）掺雜於第 一 B階黏著層240a與第二B階黏著層24%中以增加導電 201003806 jOOl-t 17063-OPtwf.doc/n 性。- show) ' and the junction bump 230a can be a gold junction bump or a copper junction bump. In another embodiment of the present invention, the bumps may be electroplated bumps 230b (as shown in Figure 2B 9 201003806 ..... J〇〇l-t 17063-OPtwf.doc/n). The plated bumps 230b can be gold bumps, copper bumps, solder bumps, or other 'electric bumps. Each of the bonding bumps 230a or each of the plating bumps 230b is covered by each of the bonding blocks 240a'. According to this embodiment, the first B-stage adhesive layer 24A includes a plurality of first B-step adhesive blocks 240a', and the second B-stage adhesive layer 240b includes a plurality of second B'-stage adhesive blocks 240b' The first B-stage adhesive block 240a is adhered to the surface si of the first substrate 210 and the second b-stage adhesive block 24〇b is adhered to the surface S2 of the second substrate 2ω. In this embodiment, when the second 8th-order adhesive block 24 = 'is conductive or non-conductive, the first-order adhesive block 240a is electrically conductive or non-zero. Since the first B-stage adhesive block 240a is electrically insulated from each other and the first B-stage adhesive block 240b' is electrically insulated from each other, even the first B-stage adhesive block 240a' and the second B-stage adhesive block 240b, both electrically conductive, still prevents short circuits between the bumps 230a, 230b. In this embodiment, the first B-stage adhesive layer 240a and the second B-stage adhesive layer 240b may be ABLESTIK's 8008 or 8008HT, and the glass transition temperature (Tg) is about 80 degrees Celsius. between. Further, the first B-stage adhesive layer 240a and the second b-stage adhesive layer 24〇b may also be 6200, 62 of ABLESTIK (SA, 200_6, SA_2〇〇_1 provided by H, 6202C or HITACHI Chemical CO., Ltd. 〇, and its glass transition temperature (Tg) is approximately between minus 40 degrees Celsius and 150 degrees Celsius. Section: B Glass transition temperature of the adhesive layer 24Ga (term can be greater than, equal to, or less than the second B-order The glass transition temperature (Tg) of the adhesive layer 240b. Further, for example, some conductive particles (such as silver particles, copper particles, and gold particles) may be doped into the first B-stage adhesive layer 240a and the second B-stage adhesive layer 24%. To increase the conductivity 201003806 jOOl-t 17063-OPtwf.doc/n sex.

圖3A至圖3D為本發明之另一實施例之晶片封裝結 構的剖面示意圖。請參考圖3A及圖3B，除了第一 B階黏 著層240a與第二B階黏著層240b完全地填滿凸塊230之 間的空隙之外’本實施例之晶片封裝結構2〇〇,與如圖2A 及圖2B的晶片封裝結構200是相似的。特別的是，第一 B3A to 3D are schematic cross-sectional views showing a wafer package structure according to another embodiment of the present invention. Referring to FIG. 3A and FIG. 3B, except that the first B-stage adhesive layer 240a and the second B-stage adhesive layer 240b completely fill the gap between the bumps 230, the chip package structure 2 of the present embodiment, The wafer package structure 200 of Figures 2A and 2B is similar. In particular, the first B

1¾黏著層240a與苐二B階黏著層240b皆為非導電以防止 凸塊230之間的短路。 請參考圖3C，除了第一 B階黏著層240a的尺寸D1 與第二B階黏著層240b的尺寸D2不同之外，本實施例之 晶片封裝結構200’’與如圖3A的晶片封裝結構2〇〇,是相似 的。如圖3C所示 卜 丨策黏者層240a的尺寸 第二B階黏著層24Gb的尺寸D2,以使得第—基板21〇 一Both the adhesive layer 240a and the second B-stage adhesive layer 240b are non-conductive to prevent shorting between the bumps 230. Referring to FIG. 3C, the chip package structure 200'' of the present embodiment and the chip package structure 2 of FIG. 3A are different from the size D1 of the first B-stage adhesive layer 240a and the size D2 of the second B-stage adhesive layer 240b. Oh, it’s similar. The size of the second adhesive layer 24Gb of the second B-stage adhesive layer 24G is as shown in FIG. 3C, so that the first substrate 21 is

部分的面積不會被第—B _著層·續覆蓋並暴露於 外。除了凸塊230所佔的面積之外，第二B階黏著層24〇b 完全地覆^蓋第二基板22〇的表面S2，且第—B ‘著廣 240a使第-基板21〇的表面S1 (周圍的區域）暴露於外。 請參考圖3D，除了第一 B P嫌著層240a包括多個第 :B階黏著塊織，之外，本實施例之晶片封裝結構⑽，” -、如圖3C的晶片封裝結構2〇〇，，是相似的。 ，4為本發明之—實_之堆疊型⑼封裝結構的别 :思圖。請參考圖4，堆疊型晶片封裝結構_包括〆 410:-第—晶片21()’、—第二晶片22q，、多個凸 0、一第一 B階黏著層240a、一第二B階黏著層24〇b 11 201003806 ------〇001-t 17063-OPtwf.doc/n f多條焊線420。第一晶片210，、第二晶片22〇，、凸塊23〇、 第一 B階黏著塊240a’、第二B階黏著塊24〇b，的排列方式 實貝上與如圖2A或圖2B的排列方式相同。在本實施例 中’第一晶片210,藉由一黏著層430(如環氧樹脂、銀膠、 黏晶膠膜(DAF)等等）與承載器410結合且透過焊線42〇 與承載器410電性連接。承載器410例如是印刷電路板。 印刷電路板可為FR4、FR5、BT、PI電路基板。特別的是， 第一晶片210,具有透過焊線420與承載器41〇電性連接的 線焊墊214。 圖5至圖7為本發明之多個實施例之堆疊型晶片封誓 、=的剖面示意圖。請參考圖5,堆疊型晶片封裝結構棚& ^一承載盗410、-第一晶片細，、—第二晶片22〇，、 夕個凸塊230、-第-B階黏著層2術、 層纖及多條焊線42〇。第— 弟β/白黏者 _。、第- 二= o 由上，或 ，器4lG結合且透過焊線侧與承 與承載器電性連接的:焊;片2 == 墊214的焊線420的—姓址楚0 遷接於線烊 藉以提供支撐及保護作B階崎層2術包覆， 睛參考圖6及圖7， 伽c中，第一晶片21()，、Ϊ = =封裝結構彻b與 罘一曰日片220、凸塊230、第一 12 3001 -t 17063-OPtwf.doc/n 201003806 B階黏者層240a及苐一 B階黏著層240b的排列方式亦可 與如圖3C及圖3D之前述實施例相同或相似。如圖6及圖 7所示，第一晶片210’的線焊墊214不會被第一 B階黏著 層240a或第一 B階黏著塊24〇a，覆蓋並且暴露於外，以使 得焊線420不會被第一 B階黏著層24〇a或第一 B階黏 塊240a’所包覆。The area of the part will not be covered and exposed by the first-B _ layer. In addition to the area occupied by the bumps 230, the second B-stage adhesive layer 24〇b completely covers the surface S2 of the second substrate 22〇, and the surface of the first substrate 21 is widened by the first B' S1 (the surrounding area) is exposed to the outside. Referring to FIG. 3D, in addition to the first BP smear layer 240a including a plurality of: B-stage adhesive slabs, the chip package structure (10) of the present embodiment, "-, the chip package structure of FIG. 3C," 4 is a stacking type (9) package structure of the present invention: Fig. 4, the stacked chip package structure _ including 〆 410: - the first wafer 21 ()', a second wafer 22q, a plurality of convex zeros, a first B-stage adhesive layer 240a, a second B-stage adhesive layer 24〇b 11 201003806 ------〇001-t 17063-OPtwf.doc/nf a plurality of bonding wires 420. The first wafer 210, the second wafer 22, the bump 23, the first B-stage adhesive block 240a', and the second B-stage adhesive block 24〇b are arranged in a manner The arrangement is the same as that of FIG. 2A or FIG. 2B. In the present embodiment, the first wafer 210 is bonded to the carrier by an adhesive layer 430 (such as epoxy resin, silver paste, adhesive film (DAF), etc.). The 410 is bonded and electrically connected to the carrier 410 through the bonding wire 42. The carrier 410 is, for example, a printed circuit board. The printed circuit board can be an FR4, FR5, BT, PI circuit substrate. In particular, the first crystal The sheet 210 has a wire bonding pad 214 electrically connected to the carrier 41 through the bonding wire 420. Figures 5 to 7 are schematic cross-sectional views of the stacked wafer sealing and ??? according to various embodiments of the present invention. 5, stacked chip package structure shed & ^ a carrier stolen 410, - the first wafer fine, - the second wafer 22 〇, 夕 凸 230, - the - B-stage adhesive layer 2, layer fiber and A plurality of bonding wires 42 〇. The first brother β / white sticky _., the first - second = o by the upper, or the device 4lG combined and electrically connected to the bearing through the wire side: welding; == The bonding wire 420 of the pad 214 - the surname Chu 0 is migrating to the wire 烊 to provide support and protection for the B-order layer 2 coating, the eye is referred to FIG. 6 and FIG. 7, in the gamma c, the first wafer 21 (),, Ϊ = = package structure, b and 罘 曰 220 220, bump 230, first 12 3001 -t 17063-OPtwf.doc/n 201003806 B-order adhesive layer 240a and first-order B-layer adhesive layer The arrangement of 240b may be the same as or similar to the previous embodiment of Figures 3C and 3D. As shown in Figures 6 and 7, the wire bond pad 214 of the first wafer 210' is not replaced by the first B-stage adhesive layer 240a. Or the first B-stage adhesive block 24〇 a, covered and exposed, so that the bonding wire 420 is not covered by the first B-stage adhesive layer 24A or the first B-stage adhesive 240a'.

C 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明’任何所屬技術領域中具有通常知識者，在不 = 之精神Ϊ範圍内，當可作些許之更動與潤飾， 為準。《明之賴範J5當視後附之冑料㈣目所界定者 圖 圖式簡單說明】 。圖1為具有高分子凸塊的晶片封裝結構的剖面 示意 Ο 及為本發日狀—實施狀晶片封裝結構的Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention to any of the ordinary skill in the art, and may be modified and retouched within the scope of the invention. Prevail. "Mingzhi Lai Fan J5 is regarded as the material defined by the attached four (4). The figure is a simple explanation]. 1 is a cross-sectional view of a wafer package structure having polymer bumps, and a wafer-like structure of the present invention.

剖面示意圖 圖3Α至圖3D為本發明之另一實施例之 構的剖面示意圖。 片 圖4為本發明之—實施例之堆㈣晶片封 面示意圖。 Q 封裝結 構的剖 結構圖為本發明之多個實施例之堆疊型 晶片封裝 13 201003806 〇〇01-t 17063-OPtwf.doc/n 【主要元件符號說明】 100 :晶片封裝結構 110 :第一基板 110a :表面 112:接觸墊 120:高分子凸塊 130 :晶片 130a :主動表面 I 132 :焊墊 140 :焊料 200 :晶片封裝結構 200’ ：晶片封裝結構 200” ：晶片封裝結構 200’’’ ：晶片封裝結構 210 :第一基板 210’ ：第一晶片 U 212:第一焊墊 214 :線焊墊 220 :第二基板 220’ ··第二晶片 222 :第二焊墊 230 :凸塊 230a :結線凸塊 230b :電鍍凸塊 14 201003806〇uol.t 17063-OPtwf.doc/n 240 :黏著材料 240a :第一 B階黏著層 240a’ ：第一 B階黏著塊 240b :第二B階黏著層 240b’ ：第二B階黏著塊 310 :基板 312 :焊墊 320 :凸塊 320a :結線凸塊 330 :黏著材料 330a :熱固性黏著塊 340 :具有B階特性之黏著塊 400 :堆疊型晶片封裝結構 400b :堆疊型晶片封裝結構 400c :堆疊型晶片封裝結構 410 :承載器 420 :焊線 430 :黏著層 A :表面 B :表面 D1 :尺寸 D2 :尺寸 51 :表面 52 :表面 15BRIEF DESCRIPTION OF THE DRAWINGS Fig. 3A to Fig. 3D are schematic cross-sectional views showing another embodiment of the present invention. Figure 4 is a schematic view of a stack of (4) wafers in accordance with an embodiment of the present invention. A cross-sectional view of a Q package structure is a stacked type chip package 13 of various embodiments of the present invention. 201003806 〇〇01-t 17063-OPtwf.doc/n [Description of main component symbols] 100: chip package structure 110: first substrate 110a: surface 112: contact pad 120: polymer bump 130: wafer 130a: active surface I 132: pad 140: solder 200: chip package structure 200': chip package structure 200": chip package structure 200"': The chip package structure 210: the first substrate 210': the first wafer U212: the first pad 214: the wire pad 220: the second substrate 220' · the second wafer 222: the second pad 230: the bump 230a: Bonding bump 230b: plating bump 14 201003806〇uol.t 17063-OPtwf.doc/n 240: adhesive material 240a: first B-stage adhesive layer 240a': first B-stage adhesive block 240b: second B-stage adhesive layer 240b': second B-stage adhesive block 310: substrate 312: solder pad 320: bump 320a: junction bump 330: adhesive material 330a: thermosetting adhesive block 340: adhesive block 400 having B-stage characteristics: stacked chip package structure 400b: stacked chip package structure 400c: stacked crystal The package structure 410: bearing 420: bonding wire 430: adhesive layer A: surface B: surface D1: Size D2: Size 51: surface 52: surface 15

Claims (1)

〇001-t 17063-OPtwf.doc/n 201003806 十、申請專利範面： 種晶片封裝結構，包括： 第一基板，具有多個第一焊塾； ，繁一ί二基板，具有多個第二焊墊，該第二基板設置於 该弟一基板的上方； 中各节土^塊捏：置於該第—基板及該第二基板之間，其 電分別透過其★—凸塊與對應之第二焊墊 -，黏著於該第-基板上;以及 二基板之間，其中該第4=:广皆黏著層與該第 包覆該多個凸塊。 。考層與該第二B階黏著層 該4tt=範圍第1項所述之晶片封裝結構，其中 凸塊包括結線凸塊或電鑛凸塊。 O 該第1項所述之晶片職結構，其中 4 ‘由IΓ 4二B階黏著層為非導電。 該第^ 第1項所述之晶片封賴構，其中 階，包，= = 該些項所述之晶片封裝結構’其中 哕此筮如！明專利fe固第5項所述之晶片封裝結構，其中 该些紅B階㈣塊為導電。 7’如申μ專利範圍第5項所述之晶片封裝結構，其中 16 〇Ptwf.d〇c/n 201003806 黏著塊為#導電。 該些第—㈣麟之^封裝結構’其中 9. 如申請專利範 。“ 該些第二B _著塊電項所述之“封裝結構，其中 10. 如申請專利範 。 該些第二㈣黏著==€項所述之晶片封裝結構，其中 嗲第1ϋ月專利範圍第1項所述之晶片封裝結構，其中 該弟-基板與該第二基板皆為晶片。 甲 該第㈣轉’其中 H第—基板其中之—者為晶片。 蜂if申料利範15第1項所述之晶片封裝結構 ，其中 層的玻璃轉換溫度高於該第二㈣黏著層 访笛^4·τΓ申請專利範圍帛1項所述之晶片封裝結構，其中 Cj ^s P皆黏著層的玻態轉化溫度等於或低於該第二B階 黏者層的破璃轉換溫度。 15·如申凊專利範圍第i項所述之晶片封裝結構，更包 枯. —承载器；以及 載哭I條烊線★，其中該第—基板與該第二基板設置在該承 时TO ，且該第一基板透過該些焊線而電性連接至該承載 态0 Μ.如申睛專利範圍第1項所述之晶片封裝結構，其中 17 20 1 003 806〇〇〇1.t i7〇63-〇Ptwf.doc/n 各該焊線的一端被該第一 B階黏著層包覆。 17. 如申請專利範圍第1項所述之晶片封裝結構，其中 各該焊線的一端不被該第一 B階黏著層包覆。 18. 如申請專利範圍第1項所述之晶片封裝結構，其中 該第一 B階黏著層的厚度實質上等於該第二B階黏著層的 . 厚度。 19. 如申請專利範圍第1項所述之晶片封裝結構，其中 該第一 B階黏著層的尺寸小於該第二B階黏著層的尺寸。 20. 如申請專利範圍第19項所述之晶片封裝結構，其 中該第一 Β階黏著層包括多個第一 Β階黏著塊。〇001-t 17063-OPtwf.doc/n 201003806 X. Patent application: A chip package structure, comprising: a first substrate having a plurality of first pads; a plurality of substrates, having a plurality of second a soldering pad, the second substrate is disposed above the substrate of the second body; and each of the soil blocks is disposed between the first substrate and the second substrate, and the electricity is respectively transmitted through the ★-bump and the corresponding a second pad - adhered to the first substrate; and between the two substrates, wherein the fourth =: wide adhesion layer and the first cladding the plurality of bumps. . The test layer and the second B-stage adhesive layer, wherein the bump comprises a wire bump or an electric ore bump. O The wafer structure described in item 1 wherein 4 'is non-conductive by I Γ 4 2 B-adhesive layer. The wafer package structure of the first item, wherein the package, = = the chip package structure described in the above items, such as this! The chip package structure of claim 5, wherein the red B-stage (four) blocks are electrically conductive. 7' The wafer package structure of claim 5, wherein the 16 〇Ptwf.d〇c/n 201003806 adhesive block is # conductive. The first - (four) Lin ^ ^ package structure '. 9. If you apply for a patent. “The second B _ block of electricity described in the “package structure,” 10. As applied for a patent. The chip package structure according to the first aspect of the invention, wherein the chip-substrate and the second substrate are both wafers. A. The fourth (four) turn 'where the H first - the substrate is the wafer. The wafer package structure of the first aspect of the invention, wherein the glass transition temperature of the layer is higher than the wafer package structure described in the second (four) adhesive layer The glass transition temperature of the adhesive layer of Cj^s P is equal to or lower than the glass transition temperature of the second B-stage adhesive layer. 15. The wafer package structure as described in claim i of the patent scope, further comprising: a carrier; and a crying I 烊 line ★, wherein the first substrate and the second substrate are disposed in the bearing time TO And the first substrate is electrically connected to the carrier state through the bonding wires. The chip package structure according to claim 1, wherein 17 20 1 003 806 〇〇〇 1.t i7 〇63-〇Ptwf.doc/n One end of each of the bonding wires is covered by the first B-stage adhesive layer. 17. The wafer package structure of claim 1, wherein one end of each of the bonding wires is not covered by the first B-stage adhesive layer. 18. The wafer package structure of claim 1, wherein the first B-stage adhesive layer has a thickness substantially equal to a thickness of the second B-stage adhesive layer. 19. The wafer package structure of claim 1, wherein the first B-stage adhesive layer has a size smaller than a size of the second B-stage adhesive layer. 20. The wafer package structure of claim 19, wherein the first step adhesive layer comprises a plurality of first step adhesive blocks.
TW97126666A 2008-07-14 2008-07-14 Chip package structure TW201003806A (en)

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