TW201003805A - Micro-electro-mechanical pakage structure - Google Patents

Micro-electro-mechanical pakage structure Download PDF

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Publication number
TW201003805A
TW201003805A TW97126242A TW97126242A TW201003805A TW 201003805 A TW201003805 A TW 201003805A TW 97126242 A TW97126242 A TW 97126242A TW 97126242 A TW97126242 A TW 97126242A TW 201003805 A TW201003805 A TW 201003805A
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TW
Taiwan
Prior art keywords
substrate
mems
package structure
micro
electrically connected
Prior art date
Application number
TW97126242A
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Chinese (zh)
Inventor
Shih-Ping Hsu
Original Assignee
Phoenix Prec Technology Corp
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Priority to TW97126242A priority Critical patent/TW201003805A/en
Publication of TW201003805A publication Critical patent/TW201003805A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Micromachines (AREA)

Abstract

A micro-electro-mechanical package is proposed, characterized by embedding and electrically connecting a semiconductor chip in the first surface of a substrate, and disposing and electrically connecting a micro-electro-mechanical component on the first surface, such that the semiconductor chip can be embedded in the substrate to avoid aligning the micro-electro-mechanical component with the semiconductor chip, thereby reducing the package height and profile and also avoiding electrical interference therebetween for optimal electrical performance.

Description

201003805 凡、I«月說明： 【發明所屬之技術領域】 ， & ^有關於帛封裝結構，尤指-種微機電封裝 結構。 【先前技術】 —辟微機電（M_ -般是在石夕晶圓上常見的元件，有光 _ J•兀件（〇PtlCal)、麥克風（micr〇)、加速度計 (二一…、感測計(~)、奈米馬達(n_ (油小幫浦(卿p)及天線等各式各樣的元件。 習知的微機電封裝結構，係將微機電元件及半導體晶 • 1以並临debyside)方式設置於封録板的表面上明 •再以保濩罩或封裝膠體進行封裝保護。 如乐1A圖所不’係提供—具有線路之基板，該基 板10具有第一表面1〇 第_ 夂弟—表面l〇b，該第一表面1〇a 具有複數打線墊101及表面黏著塾1〇2，而該第二表面⑽ 植球整103’於該第—表面⑽接置有微機電元 、 半導體晶片12及被動元件13,其中該微機電元件 u具有複數第一電極墊lu，而該半導體晶片12具有複 數第二電極墊122,使該半導體晶片12之第二電極墊‘ 以焊線14電性連接至該微機電元件11之第—電極墊ln =線：⑷，再以封裝膠體15進行封裝，以保護該微 機电凡件11、半導體晶片]2、焊線H及打線墊1〇1 ,且 ==件1i係藉由黏著元件102,以電性連接該表面黏 者 ，°亥第一表面】Ob之該些植球墊】03各植設有第 ]10864 5 201003805 一砰竹0塊i6a，以與其他電子元件電性連接。 •二2 1β圖所示，係為習知微機電元件11以覆晶方 ,^連接至該基板10;該微機電元件u具有複數第— 笔極塾111，且該基板10具有複數相對 ，機電元件U之第一電極塾ln#由第二= -至該基板10之焊塾〗°4,且於該微機電: 二i2r二電極塾122以焊線14電性連接至該= i ，膠體15進行封裝’以保護該半導體晶片 杜上線·101，且該被動元件13係藉由黏著 • 70 以电性連接至該表面黏著墊102 ;俾以整入微 ‘機電元件及其他電路元件。 正口微 然而，該微機電元件n整合主動之半導體晶月a 及係如电阻、電容或電感之被動元件13時，使該微機電 几2 U、半導體晶片12及被動元件13佔用較大面積外， 且眾多元件之間的電性連接容易相互干擾，又電性連接之 =亦因透過打金線及基板佈線，易產生寄生電感、寄生 包合以及較大之阻抗，導致電性品質降低。 口此如何提出—種微機電封裝結構，以避免習知微 機電封褒結構之平面面積及高度過大，而不利於微小化製 裎’：及眾多電路元件之間的電性干擾，減少電路中所產 生之寄生電感、寄生電容及較大阻抗，實已成為虽需改進 的問題。 【發明内容】 110864 6 201003805 趣於上述習知技術之缺失，本發 供一種微機電封I έ士槿 目的係在於提 及被動元件。 午半導體晶片 本發明另一目的係在於提供— 減少微機電封fΑ 裰枝笔封裝結構，能 包27衣結構所佔據的面積。 本發明又-目的係在於提供—種微機 降低微機電封裝結構的高度。 $，t、.吉構，能 沾'，本發明再—目的係在於提供-種微機電封^士错处 減少電料接料叙^電容 ^封^構，施 升電性功能。 生电感及阻抗，以提 為達上述及其他目的，本發明揭 ?，係包括:基板，係具有第一表面及第二 日日片，係埋設於該基板中，並'"，丰V祖 機電元件，係設於竽第 该基板；以及微 m 以―表面上，且與該基板電性連接。 ^述之微機電封裝結構，該基板传為 路板，該半導體μ ㈣為具有線路之線 具有_篆^亡㈣卜電極塾’該基板之内部 夏數弟導電盲孔，該半導體曰η目女…如战 墊，使哕第一道+亡 千¥奴日日片具有禝數第一電極 極塾。¥笔目孔電性連接至該半導體晶片之第-電 ㈣ΐ依上述之結構’該第一表面具有複數打線塾，且兮 =〜元件具有複數相對應之第：電極墊，使該微機^ =_電極塾以焊線電性連接至該打線墊；或該第— :恭a有複數*干墊’且該微機電元件具有複數相對應之第 〜电極墊’使該微機電元件之第二電極塾藉由焊料凸塊以 】]〇86毪 7 201003805 电Ί·王逆按至該焊塾。 • ^本發明復提供另一實施結構，該基板復包括具有未貫 t穿之凹部，以供容置該微機電元件，該第一表面具有複1 打線墊，且該微機電元件具有複數相對應之第二電極墊， 使該微機電元件容置於該凹部中，並使該第二電極墊以俨 . 線電性連接至該打線墊。 ^ 復包括被動元件，係設於該基板之内部，且與該芙 :性連接，該基板之内部具有複數第二#電盲孔，使該第 r二導電盲孔電性連接至該被動元件；或該被動元 於該餘之第-表面上，該第一表面具有複數表面黏= 及黏者兀件，使該被動元件藉由該黏著元件以電性 該表面黏著墊。 及接主 再依上述之結構，該第二表面復具有複數電性接 墊，於該電性接觸墊上設有導電元件，該導電元件 面栅陣列uand grid array，LGA)、球柵陣列（bau、盯千 array，BGA)或針腳（pin)。 s ια 4 I發明係將該半導體晶片埋人於該基板中，而可 該半導體晶片及微機電元件並排佔用基板之表面的缺 失’以印名封裝結構之平面面積；且將該半導體拽、 基板内更能避免該半導體晶片及該微機電元件：電性： 接而導致兩者之間產生電性相互干擾，以: 造成的寄生電感、寄生電容以月田私且+ 电注連接所 了玍^•谷以及因拉長電性連接路 成的阻抗;於微機電封裝結構中採用埋設有 曰工“ 基板亦能輕易達成該微機電封裝結構整合為單^曰之 彳萬組之 110864 8 201003805 目的；又將該微機電元件容設於該基板之凹部中，以降低 整體之封裝高度。 【實施方式】 以下係藉由特定的具體實例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 - 暸解本發明之其他優點與功效。 -[第一實施例] 請參閱第2A至2C圖，係詳細說明本發明之微機電封 裝結構第一實施例之剖面示意圖。 如第2A圖所示，首先，提供埋設有半導體晶片21 之基板2 0，於本實施例中，該基板2 0係為具有線路之線 路板，於該基板20之内部具有複數第一導電盲孔201， 於該基板20中嵌埋有半導體晶片21，該半導體晶片21 具有複數第一電極墊211，使該第一導電盲孔201電性連 接至該半導體晶片21之第一電極墊211，俾使該半導體 晶片21埋設於該基板2 0中及電性連接該基板2 0，且該 1 基板20具有第一表面20a及第二表面20b，於該第一表 面20a具有複數焊墊202，而該第二表面20b具有複數電 性接觸墊203。 如第2B及2B’圖所示，於該基板20之第一表面20a 上設置並電性連接該微機電元件22，該微機電元件22具 有複數相對應該焊墊202之第二電極墊221，使該微機電 元件22之第二電極墊221藉由焊料凸塊23以電性連接至 該焊墊202，使該微機電元件22以覆晶（flip chip)方式 9 110864 201003805201003805 Where, I« month description: [Technical field of invention], & ^ There are about 帛 package structure, especially a kind of MEMS package structure. [Prior Art] - Micro-Electromechanical (M_ - is commonly used in Shi Xi wafers, there are light _ J • 兀 〇 (〇 PtlCal), microphone (micr 〇), accelerometer (two one..., sensing Various components such as meter (~), nano motor (n_ (oil small pump (qing p) and antenna.) The conventional micro-electro-mechanical package structure is the combination of micro-electromechanical components and semiconductor crystals. The debyside method is disposed on the surface of the sealing plate and is further protected by a protective cover or an encapsulant. If the lens is not provided, the substrate 10 has a first surface. _ 夂 — - surface l 〇 b, the first surface 1 〇 a has a plurality of wire pads 101 and surface adhesion 塾 1 〇 2, and the second surface (10) ball slab 103 ' at the first surface (10) An electromechanical element, a semiconductor wafer 12 and a passive component 13, wherein the microelectromechanical component u has a plurality of first electrode pads lu, and the semiconductor wafer 12 has a plurality of second electrode pads 122 such that the second electrode pads of the semiconductor wafers 12 The bonding wire 14 is electrically connected to the first electrode pad of the microelectromechanical element 11 ln = line: (4), and then sealed The colloid 15 is encapsulated to protect the MEMS member 11, the semiconductor wafer 2, the bonding wire H and the bonding pad 1〇1, and the =1 member 1i is electrically connected to the surface by the adhesive member 102. The first surface of °H]The ball-bearing mats of Ob] The 10th plant has the 1086 5 201003805 one-piece bamboo i6a, which is electrically connected with other electronic components. • The 2 2 1β figure shows that The conventional microelectromechanical element 11 is connected to the substrate 10 by a flip chip; the microelectromechanical element u has a plurality of first-pole poles 111, and the substrate 10 has a complex relative, and the first electrode of the electromechanical element U is 塾ln# From the second = - to the soldering of the substrate 10 ° 4, and in the micro-electromechanical: the two i2r two-electrode 塾 122 is electrically connected to the = i by the bonding wire 14, the colloid 15 is packaged 'to protect the semiconductor wafer Du is on line 101, and the passive component 13 is electrically connected to the surface adhesive pad 102 by adhesive bonding; 俾 to integrate the micro' electromechanical component and other circuit components. However, the microelectromechanical component n is integrated When the active semiconductor crystal moon a and the passive component 13 such as a resistor, a capacitor or an inductor, the micro-electromechanical couple 2 U The semiconductor wafer 12 and the passive component 13 occupy a large area, and the electrical connections between the plurality of components are easily interfered with each other, and the electrical connection is also susceptible to parasitic inductance and parasitic inclusion due to the gold wire and the substrate wiring. And the larger impedance, resulting in lower electrical quality. How to propose a micro-electromechanical package structure to avoid the planar area and height of the conventional micro-electromechanical sealing structure is too large, which is not conducive to miniaturization? Electrical interference between circuit components, reducing parasitic inductance, parasitic capacitance and large impedance generated in the circuit has become a problem that needs to be improved. SUMMARY OF THE INVENTION 110864 6 201003805 Interested in the absence of the above-mentioned prior art, a micro-electromechanical seal is provided for the purpose of introducing passive components. PM Semiconductor Wafer Another object of the present invention is to provide a reduced microelectromechanical package that can occupy the area occupied by the 27 garment structure. Still another object of the present invention is to provide a microcomputer that reduces the height of the microelectromechanical package structure. $,t,.吉吉,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The present invention discloses a substrate having a first surface and a second solar eclipse, embedded in the substrate, and '", Feng V, for the purpose of the above and other objects. The electromechanical component is disposed on the substrate; and the microm is on the surface and electrically connected to the substrate. The micro-electromechanical package structure, the substrate is transmitted as a road board, and the semiconductor μ (4) is a line having a line having a 篆 亡 亡 四 四 四 四 四 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该Female... such as the battle mat, so that the first + death thousand slaves Japanese film has a number of first electrode. The pen hole is electrically connected to the first electric (four) of the semiconductor wafer. According to the above structure, the first surface has a plurality of wire 塾, and the 兮=~ element has a plurality of corresponding: electrode pads, so that the microcomputer ^= The _ electrode 电 is electrically connected to the wire bonding pad by a bonding wire; or the first: the gong a has a plurality of * dry pad 'and the MEMS element has a plurality of corresponding first electrode pads 'making the MEMS element The two electrodes are pressed to the solder bump by the solder bumps.] 〇86毪7 201003805. The invention further provides another embodiment, the substrate comprising a recess having a through-hole for receiving the microelectromechanical component, the first surface having a complex wire pad, and the microelectromechanical component having a complex phase Corresponding to the second electrode pad, the microelectromechanical component is received in the recess, and the second electrode pad is electrically connected to the wire pad. The passive component is disposed inside the substrate and is connected to the device. The substrate has a plurality of second electrical blind holes therein, and the second conductive via is electrically connected to the passive component. Or the passive element is on the first surface of the remainder, the first surface has a plurality of surface adhesives and adhesive members, so that the passive component electrically adheres the surface to the surface by the adhesive component. According to the above structure, the second surface has a plurality of electrical pads, and the electrical contact pads are provided with conductive elements, the conductive element grid array, LGA, ball grid array (bau) , staring at array, BGA) or pin. The s ια 4 I invention is to embed the semiconductor wafer in the substrate, and the semiconductor wafer and the MEMS element may be side by side occupying the missing surface of the substrate to mark the planar area of the package structure; and the semiconductor raft, the substrate The semiconductor wafer and the MEMS element can be more avoided: electrical: the electrical interference between the two is caused, and the parasitic inductance and parasitic capacitance are caused by the connection of the moon and the electric charge. ^•Valley and the impedance of the electrical connection; the use of embedded in the MEMS package structure can also easily achieve the integration of the MEMS package structure into a single group of 110864 8 201003805 The MEMS device is further disposed in the recess of the substrate to reduce the overall package height. [Embodiment] Hereinafter, embodiments of the present invention will be described by using specific specific examples, and those skilled in the art may The contents disclosed in the specification are easily understood - to understand other advantages and effects of the present invention. - [First Embodiment] Please refer to Figures 2A to 2C for a detailed description of the present invention. A cross-sectional view of a first embodiment of an electrical package structure. As shown in FIG. 2A, first, a substrate 20 in which a semiconductor wafer 21 is embedded is provided. In this embodiment, the substrate 20 is a circuit board having a line. The substrate 20 has a plurality of first conductive vias 201, and a semiconductor wafer 21 is embedded in the substrate 20. The semiconductor wafer 21 has a plurality of first electrode pads 211, and the first conductive vias 201 are electrically connected to the substrate. The first electrode pad 211 of the semiconductor wafer 21 is embedded in the substrate 20 and electrically connected to the substrate 20, and the first substrate 20 has a first surface 20a and a second surface 20b. The first surface 20a has a plurality of pads 202, and the second surface 20b has a plurality of electrical contact pads 203. As shown in Figures 2B and 2B', the first surface 20a of the substrate 20 is electrically connected The microelectromechanical component 22 has a plurality of second electrode pads 221 corresponding to the pads 202, such that the second electrode pads 221 of the microelectromechanical components 22 are electrically connected to the solder by solder bumps 23. Pad 202, such that the microelectromechanical element 22 Crystal (flip chip) mode 9,110,864,201,003,805

電性連接該基板20，其中，該焊料凸塊23係可選自錫、 銀、金、錢、敍及鋅所組成群組之其中一者，且於該微機 電元件22與第一表面20a之間形成有底膠24，如第2B * 圖所示；或該微機電元件22先接置於該第一表面20a 上，而該第一表面20a具有複數打線墊202’，使該微機 電元件22之第二電極墊221以打線（wi re bonding)之焊 . 線25電性連接至該第一表面20a之打線墊202’，並以封 裝膠體26進行封裝，以保護該微機電元件22、焊線25 及打線墊202’，如第2B’圖所示。 如第2C圖所示，於該第二表面20b之電性接觸墊203 上形成有導電元件27’該導電元件27係為平面桃陣列 (land grid array，LGA)、球栅陣列（ball grid array, BGA) 或針腳（p i η)。 本發明提供一種微機電封裝結構，係包括：基板20， 係具有第一表面20a及第二表面20b ;半導體晶片21，係 埋設於該基板20中，並電性連接至該基板20 ;以及微機 .f *' 電元件2 2，係設於該第一表面2 0 a上，且與該基板2 0電 性連接。 依上述之微機電封裝結構，該基板2 0係為具有線路 之線路板，該半導體晶片21具有複數第一電極墊211， 且該基板20之内部具有複數第一導電盲孔201，使該第 一導電盲孔201電性連接至該半導體晶片21之第一電極 墊 211。 又依上述之結構，該第一表面20a具有複數焊墊 10 110864 201003805 202，且該微機電元件22具有複數相對應之第二電極墊 221，使該微機電元件22之第二電極墊221藉甴焊料凸塊 2 3以電性連接至該焊墊2 0 2 ;或該第一表面2 0 a具有複數Electrically connecting the substrate 20, wherein the solder bumps 23 are selected from the group consisting of tin, silver, gold, gold, zinc, and zinc, and the microelectromechanical element 22 and the first surface 20a are A primer 24 is formed therebetween, as shown in FIG. 2B*; or the microelectromechanical element 22 is first placed on the first surface 20a, and the first surface 20a has a plurality of wire pads 202' to make the MEMS The second electrode pad 221 of the component 22 is soldered by wiring. The wire 25 is electrically connected to the wire pad 202' of the first surface 20a, and is encapsulated by the encapsulant 26 to protect the microelectromechanical component 22 . , the bonding wire 25 and the wire bonding pad 202' are as shown in FIG. 2B'. As shown in FIG. 2C, a conductive element 27' is formed on the electrical contact pad 203 of the second surface 20b. The conductive element 27 is a land grid array (LGA) and a ball grid array. , BGA) or stitch (pi η). The present invention provides a microelectromechanical package structure, comprising: a substrate 20 having a first surface 20a and a second surface 20b; a semiconductor wafer 21 embedded in the substrate 20 and electrically connected to the substrate 20; and a microcomputer .f *' The electrical component 2 2 is disposed on the first surface 20 a and electrically connected to the substrate 20 . According to the above MEMS package structure, the substrate 20 is a circuit board having a line, the semiconductor wafer 21 has a plurality of first electrode pads 211, and the inside of the substrate 20 has a plurality of first conductive blind holes 201, so that the first A conductive via hole 201 is electrically connected to the first electrode pad 211 of the semiconductor wafer 21. According to the above structure, the first surface 20a has a plurality of pads 10 110864 201003805 202, and the microelectromechanical element 22 has a plurality of corresponding second electrode pads 221, so that the second electrode pads 221 of the microelectromechanical elements 22 are borrowed. The solder bump 2 3 is electrically connected to the pad 2 0 2 ; or the first surface 20 a has a plurality

I 打線墊202’，於該第一表面20a上接置該微機電元件22， 使該微機電元件22之第二電極墊221以打線（wire -bond i ng)之焊線2 5電性連接至該第一表面20a之打線整 .202’，並以封裝膠體26進行封裝。 [第二實施例] ， 請參閱第3A及3B圖，係詳細說明本發明之微機電封 裝結構第二實施例之剖面示意圖，本實施例大致與第一實 施例相同，惟本實施例之微機電封裝結構復包括有被動元 件。 如第3A及3A’圖所示，首先提供一係如第2C圖所示 之結構，且於該第一表面20a具有複數表面黏著墊204 及黏著元件204’，另提供至少一被動元件28，且該被動 元件28藉由該黏著元件204’電性連接至該黏著墊204， 俾能藉由該被動元件28以增加電性功能，該黏著元件 204’係可選自錫、銀、金、鉍、鉛及鋅所組成群組之其中 一者，如第3A圖所示；該半導體晶片21亦可因線路佈局 設計需求，嵌埋於該基板20之側邊20c，如第3A’圖所 示。 如第3B圖所示，或該被動元件28’係嵌埋於該基板 20之内部，且該基板20之内部具有複數第二導電盲孔 201 ’，使該第二導電盲孔20Γ電性連接至該被動元件 11 110864 201003805 ，同樣能藉由該被動元件28以增加電性功能，且將該 被動元件28’嵌埋於該基板20中，俾能避免佔用基板20 之第一表面的面積空間。 [第三實施例] 請參閱第4圖，係說明本發明之微機電封裝結構第三 實施例之剖面示意圖；係於基板20之第一表面20a形成 有未貫穿之凹部200，於該凹部200中容置該微機電元件 22，且該基板20之第一表面20a具有複數打線墊202’， 且該微機電元件22具有複數相對應之第二電極墊221， 並使該第二電極墊221以焊線25電性連接至該打線墊 202’，並以封裝膠體26進行封裝，以保護該微機電元件 22、焊線25及打線墊202’；由於該微機電元件22係容 設於該凹部200中，故能有效降低整體之封裝高度。 本發明係將該半導體晶片埋入於該基板中，而可避免 該半導體晶片及微機電元件並排佔用基板之表面的缺 失，以節省封裝結構之平面面積；且將該半導體晶片埋入 t 基板内更能避免該半導體晶片及該微機電元件因電性連 接而導致兩者之間產生電性相互干擾，以及其電性連接所 造成的寄生電感、寄生電容以及因拉長電性連接路徑所造 成的阻抗；於微機電封裝結構中採用埋設有半導體晶片之 基板亦能輕易達成該微機電封裝結構整合為單一模組之 目的；又將該微機電元件容設於該基板之凹部中，以降低 整體之封裝高度。 上述實施例僅例示性說明本發明之原理及其功效，而 12 ]10864 201003805 二射κ制本發明。任何熟習此項技藝之人士均可在不違 =本發明之精神及㈣下，對上述實施例進行 變。因此，本發明之栺利仅$ r R 广， < 格利保5又靶圍，應如後述之申請專利 範圍所列。 【圖式簡單說明】 帛1A及1B圖係為習知之半導體封裝件之剖視示意 圖； 、第2A12C圖係本發明微機電封裝結構之第一實施例 剖視示意圖； / 第2B’圖係為第2R Fi夕 、 乐β圖之另〜實施例之剖視圖示意； 以及 封裝結構之第二實施例 實施例之剖視圖示意； 第3Α及3Β圖係本發明微機電 之剖視示意圖； 第3Α圖係為第3Α圖之另、 以及I wire pad 202', the microelectromechanical component 22 is connected to the first surface 20a, and the second electrode pad 221 of the microelectromechanical component 22 is electrically connected by a wire-bonded wire 25 The wire is wound to the first surface 20a and is encapsulated by the encapsulant 26. [Second Embodiment] Referring to Figures 3A and 3B, a cross-sectional view of a second embodiment of a microelectromechanical package structure of the present invention will be described in detail. This embodiment is substantially the same as the first embodiment except for the embodiment. The electromechanical package structure includes passive components. As shown in FIGS. 3A and 3A', a structure as shown in FIG. 2C is first provided, and the first surface 20a has a plurality of surface adhesive pads 204 and an adhesive member 204', and at least one passive component 28 is provided. The passive component 28 is electrically connected to the adhesive pad 204 by the adhesive component 204 ′, and the passive component 28 can be used to increase the electrical function. The adhesive component 204 ′ can be selected from the group consisting of tin, silver, gold, and One of the groups of bismuth, lead and zinc is as shown in FIG. 3A; the semiconductor wafer 21 may also be embedded in the side 20c of the substrate 20 due to the layout design requirements, as shown in FIG. 3A'. Show. As shown in FIG. 3B, or the passive component 28' is embedded in the substrate 20, and the substrate 20 has a plurality of second conductive blind vias 201', such that the second conductive vias 20 are electrically connected. To the passive component 11 110864 201003805 , the passive component 28 can also be used to increase the electrical function, and the passive component 28 ′ is embedded in the substrate 20 , thereby avoiding occupying the area of the first surface of the substrate 20 . . [THIRD EMBODIMENT] Referring to Fig. 4, there is shown a cross-sectional view showing a third embodiment of the microelectromechanical package structure of the present invention; a first recessed portion 200 is formed on the first surface 20a of the substrate 20, and the recessed portion 200 is formed in the recessed portion 200. The microelectromechanical component 22 is disposed, and the first surface 20a of the substrate 20 has a plurality of wire pads 202', and the microelectromechanical component 22 has a plurality of corresponding second electrode pads 221, and the second electrode pads 221 The bonding wire 25 is electrically connected to the bonding pad 202 ′ and encapsulated by the encapsulant 26 to protect the MEMS element 22 , the bonding wire 25 and the bonding pad 202 ′; since the MEMS element 22 is accommodated therein In the recess 200, the overall package height can be effectively reduced. In the present invention, the semiconductor wafer is buried in the substrate, and the semiconductor wafer and the microelectromechanical device can be prevented from occupying the surface of the substrate side by side to avoid the planar area of the package structure; and the semiconductor wafer is buried in the t substrate. The semiconductor wafer and the MEMS element can be prevented from being electrically interfered with each other due to electrical connection, and the parasitic inductance, parasitic capacitance caused by the electrical connection, and the elongated electrical connection path are caused. Impedance; in the micro-electromechanical package structure, the substrate embedded with the semiconductor wafer can also easily achieve the purpose of integrating the micro-electromechanical package structure into a single module; and the micro-electromechanical component is accommodated in the recess of the substrate to reduce The overall package height. The above embodiments are merely illustrative of the principles and effects of the present invention, and 12] 10864 201003805. Any person skilled in the art can change the above embodiments without departing from the spirit of the invention and (d). Therefore, the profit of the present invention is only $ r R wide, < Glica 5 and target range, as listed in the patent application scope described later. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B are schematic cross-sectional views of a conventional semiconductor package; 2A12C is a cross-sectional view of a first embodiment of the microelectromechanical package structure of the present invention; / 2B' is 2A Fi, a cross-sectional view of another embodiment of the music diagram; and a cross-sectional view of a second embodiment of the package structure; FIGS. 3 and 3 are schematic cross-sectional views of the microelectromechanical device of the present invention; For the third picture, and

第4係本發明微機電封裝綠構之第三實施例之剖視 示意圖。 主要元件符號說明】 10、20 10a 、 20a l〇b 、 20b 101 、 202’ 102 、 204 102, 、 204, 基板 弟一表面 弟二表面 打線墊 表面黏著墊 黏著元件 110864 13 201003805 iua 植球墊 104 、 202 焊墊 105 、 24 底膠 11、22 微機電元件 111 、 211 第一電極塑* 12、21 半導體晶片 122 、 221 第二電極墊 13 、 28 、 28, 被動元件 14、25 焊線 15 > 26 封裝膠體 16a 第一焊料凸塊 16b 第二焊料凸塊 20c 側邊 200 凹部 201 第一導電盲孔 201’ 第二導電盲孔 203 電性接觸墊 204 黏著墊 23 焊料凸塊 27 導電元件 14 110864Fig. 4 is a schematic cross-sectional view showing a third embodiment of the micro-electromechanical package green structure of the present invention. Main component symbol description] 10, 20 10a, 20a l〇b, 20b 101, 202' 102, 204 102, 204, substrate one surface two brothers surface wire pad surface adhesive pad adhesion component 110864 13 201003805 iua ball pad 104 202 pads 105, 24 primer 11, 22 MEMS element 111, 211 first electrode plastic * 12, 21 semiconductor wafer 122, 221 second electrode pad 13, 28, 28, passive component 14, 25 bonding wire 15 &gt 26 encapsulant 16a first solder bump 16b second solder bump 20c side 200 recess 201 first conductive blind hole 201' second conductive blind hole 203 electrical contact pad 204 adhesive pad 23 solder bump 27 conductive element 14 110864

Claims (1)

201003805丁、f蜻專利範圍： L 一種微機電封裝結構，係包括： _ 基板，係具有第一表面及第二表面； 半‘肢日日片，係埋设於该基板中，並電性連接至 該基板；以及 棱機電元件，係設於該 ^ VBJ JL. 電性連接。 2.如申請專利範圍第1項之微機電封裝結構，其中，該 Ϊ板係為具有線路之線路板，該半導體晶片具有複^ 弟—電極墊。 3·如申請專利範圍第2項之微機電封裝結構，发中，a 2 具有複數第一導電盲孔’使該第^導電Ϊ 兒！·生連接至該半導體晶片之第一電極墊。 !:1請專利範圍第1項之微機電封裝結構，其中，哕 夂幾電兀件係以焊線或覆晶電性連接至 C範圍第4項之微機電封裝結；:=中，該 相對數:線整’且該微機電元件具有複數 =焊線電性連接至該打線塾。+之弟-電極塾 二申：專利範圍第4項之微機電封 複數焊墊，且該微機電元件具有U %罘—电極墊，使該微機電元 士由烊料凸塊以電性連接至該焊墊。之弟一氣極墊藉 如申請專利範圍第1項之微機電封装結構，其中，該 4. 5. 6. 110864 15 201003805 泰极後包括具有未貫穿 件。 貝牙之凹邛，以谷置該微機電元 8.如申請專利範圍第7項之 第一表面I女、巧包钌忒、..D構，其中，該 相對應之带托敌+ 包兀件/、有妓數 極墊，使該微機電元件容置於該凹部中， 9 Γ申：：—電極墊以焊線電性連接至該打線整。 •動 1::範圍第1項之微機電封裝結構，復包括被 基板電性：於該基板之内部或第-表面上’且與該 10·如申μ專利乾圍第9項之微機電封裝結構，其中，該 ί 具有複數第二導電盲孔，使該第二導電； 孔私性連接至該被動元件。 11·如:請專利範圍第9項之微機電封裝結構，其中，該 第"If面具有複數表面黏著墊及黏著元件，使該被動 兀件猎由該㈣元件電料接至該表面黏著墊。 12. ^中請專利範圍第1項之微機電封裝結構，其中，該 第二表面具有複數電性接觸墊。 13. 2請專利範圍第12項之微機電封裝結構，復包括 導電兀件，係設於該電性接觸墊上。 14. 如申胃1=專利範圍第13項之微機電封裝結構，其中， 口亥導电兀件係為平面柵陣列（land叮id array， LGA)、球柵陣列（baU grid array，BGA)或針腳 (pin)。 110864 16201003805 Ding, f蜻 Patent range: L A micro-electromechanical package structure, comprising: _ a substrate having a first surface and a second surface; a semi-limb day, embedded in the substrate and electrically connected to The substrate; and the prismatic electromechanical component are electrically connected to the VBJ JL. 2. The microelectromechanical package structure of claim 1, wherein the fascia is a circuit board having a wiring, the semiconductor wafer having a slab-electrode pad. 3. In the MEMS package structure of claim 2, in the hair, a 2 has a plurality of first conductive blind holes ‘to make the first conductive Ϊ! A raw electrode pad connected to the semiconductor wafer. !:1 Please request the micro-electromechanical package structure of the first item of the patent scope, in which the electrical components are electrically connected to the micro-electromechanical package of the fourth item of the C range by wire bonding or flip-chip bonding; The relative number: the line is 'and the MEMS element has a complex number = the wire is electrically connected to the wire 塾. + Brother - Electrode 塾二申: The micro-electromechanical sealing complex pad of the fourth item of the patent scope, and the MEMS element has a U % 罘-electrode pad, so that the MEMS element is electrically connected by the bump Connect to the pad. The brother-in-law is immersed in the micro-electromechanical package structure of the first scope of the patent, in which the 4. 5. 6. 110864 15 201003805 has a non-penetrating component. The concave tooth of the bere tooth, the microelectromechanical element is placed in the valley. 8. The first surface I, the female package, the ..D structure of the seventh item of the patent application scope, wherein the corresponding belt bears the enemy + package The element/there is a plurality of pole pads, so that the microelectromechanical component is received in the recess, and the electrode pad is electrically connected to the wire by a bonding wire. • Motion 1:: The MEMS package structure of the first item, including the electrical properties of the substrate: on the inside or the first surface of the substrate, and with the MEMS of the 10th item a package structure, wherein the ί has a plurality of second conductive blind holes to enable the second conductive; the holes are privately connected to the passive component. 11. For example, please refer to the MEMS packaging structure of the ninth patent, wherein the "If face has a plurality of surface adhesive pads and adhesive components, so that the passive component is connected to the surface by the (4) component electrical material pad. 12. The microelectromechanical package structure of claim 1, wherein the second surface has a plurality of electrical contact pads. 13. 2 The MEMS package structure of the 12th patent scope, including the conductive element, is disposed on the electrical contact pad. 14. For example, Shen Wei 1 = MEMS range of the 13th patent range, wherein the 兀 兀 conductive element is a land 叮 array ( LGA), a ball grid array (BGA grid array, BGA) Or a pin. 110864 16
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9236275B2 (en) 2011-12-01 2016-01-12 Industrial Technology Research Institute MEMS acoustic transducer and method for fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9236275B2 (en) 2011-12-01 2016-01-12 Industrial Technology Research Institute MEMS acoustic transducer and method for fabricating the same

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