TW201001535A - Method of semiconductor processing - Google Patents

Method of semiconductor processing Download PDF

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TW201001535A
TW201001535A TW097129876A TW97129876A TW201001535A TW 201001535 A TW201001535 A TW 201001535A TW 097129876 A TW097129876 A TW 097129876A TW 97129876 A TW97129876 A TW 97129876A TW 201001535 A TW201001535 A TW 201001535A
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photoresist
gas
semiconductor
plasma
processing method
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TW097129876A
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TWI485771B (en
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Tetsuo Ono
Go Saito
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Hitachi High Tech Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

In a semiconductor that has a structure in which a work function controlling metal conductor is provided on a high dielectric insulation film, fine processing is performed without deteriorating a device. In a method of semiconductor processing, in which the semiconductor has an insulation film containing Hf or Zr formed on a semiconductor substrate and a conductor film containing Ti or Ta or Ru formed on an insulation film, and the conductor film is processed by using a resist formed on the conductor film under a plasma atmosphere, the resist is removed under the plasma atmosphere of gas that contains hydrogen and does not contain oxygen.

Description

201001535 九、發明說明 【發明所屬之技術領域】 本發明係關於半導體加工方法’尤其係關於對於在高 介電常數絕緣膜上沈積有金屬之構造之半導體進行加工的 半導體加工方法。 【先前技術】 例如，在專利文獻1中係揭示在進行形成於半導體元 件之層間絕緣膜所使用之被稱爲i〇w_k膜的介電常數較低 的絕緣膜上的光阻劑去除時，使用由氫與稀有氣體之混合 氣體的電漿所取出的氫原子或氫分子的中性自由基之技術 內容。在此，在一般之使用氧電漿的光阻劑去除方法中， 係揭示由於l〇w-k膜因氧化等之劣化而使介電常數上升， 因此採用未使用氧而去除光阻劑的方法。此外，在該文獻 中亦揭示有：使基板的溫度由200°c上升至400°c而增加 光阻劑去除速度的技術、照射NH3電漿或CF4電漿而將光 阻劑表面之變性層去除的技術。 在專利文獻2中係記載一種在具備有W等高熔點金 屬電極之被稱爲金屬閘極（metal gate )的半導體元件中 ，一面防止W劣化，一面去除污染的洗淨方法。在此係 揭示一種在含有氫及水蒸氣的環境中，將晶圓進行熱氧化 ，之後，藉由未含有過氧化氫的液體，將晶圓洗淨的技術 。在該方法中’由於W層未被氧化，因此並不會發生藉 由洗淨而將 W氧化層去除的情形。此外，在該文獻之 -4 - 201001535 0 0 5 5、0 0 5 6段落中係記載在進行元件之乾式蝕刻後的光阻 劑去除時使用氧電漿的技術內容。 (專利文獻1)日本特開2005-268312號公報 (專利文獻2)日本特開2005-229130號公報 【發明內容】 (發明所欲解決之課題） 如專利文獻2所示，在習知技術中，在金屬閘極構造 之元件的光阻劑去除方面使用氧電漿。但是，隨著元件微 細化的進展而使加工線寬爲65nm以下的區域時，藉由光 阻劑去除時所使用的氧，Ti、Ta、Ru等金屬電極的側壁 被氧化，使其阻抗增加，而會產生元件劣化的問題。 元件的加工線寬較大時，由於前述側壁中之氧化層厚 度佔全體的比例較小，因此前述阻抗的增大並不會造成問 題。因此，在習知技術中，並未提及關於此點之解決方法 〇 本發明係鑑於如上所示之問題而硏創者，提供一種適 於對在高介電常數絕緣膜上沈積有金屬導體之構造的半導 體進行微細加工的加工方法。 (解決課題之手段） 本發明係爲了解決上述課題而採用以下之手段。 在具有形成在半導體基板上之含有H f或Z r的絕緣膜 、形成在該絕緣膜上之含有Ti或Ta或Ru的導體膜’使 -5- 201001535 用形成在該導體膜上的光阻劑，在電漿環境中對前述導體 膜進行加工的半導體加工方法中，將前述光阻劑在含氫而 未含氧的氣體的電漿環境中去除。 (發明之效果） 本發明由於具備有以上構成，因此在高介電常數絕緣 膜上沈積有金屬導體之構造的半導體中，可在不會使元件 劣化的情形下，施行微細加工。 【實施方式】 以下一面參照所附圖示，一面說明最佳實施形態。 第1圖係說明第1實施形態之半導體加工方法的說明 圖，第1圖（a)係作爲加工對象之半導體元件的剖面圖。半 導體元件係如第1圖（a)所示具備有·· Si基板101、依序形 成在Si基板101上之作爲高介電常數絕緣膜的HfSiON膜 1 02 ;作爲工作函數控制金屬的導體膜的TiN膜1 03 ;作 爲電極材料的W膜1 0 4 ;作爲蓋件（c ap )的S iN膜1 0 5 ; 及反射防止膜106。在此，利用高介電常數的HfSiON膜 102作爲FET的閘極絕緣膜（high-k膜），且利用TiN膜 103作爲金屬閘極，藉此可形成具備有high-k膜/金屬閘 極構造的F E T。 其中，各自的膜厚爲：HfSiON膜102爲2nm、TiN膜 1 03 爲 1 〇nm、w 膜 1 04 爲 5 0nm、SiN 膜 105 爲 5 0nm、反 射防止膜106爲80nm、光阻劑107爲200nm。 201001535 第1圖（a)係表示處理的初始狀態，藉由微影而被 化的光阻劑107位於最上層。 第1圖（b)係表示在施行調製（trimming )光阻齊 而使線寬變細的步驟之後，使用變細的光阻劑I 〇7 ’ 射防止膜106、SiN膜105、W膜104、TiN膜103施 式蝕刻後的形狀。 調製係在 Ar/02混合氣體的電漿環境下進行 SiN膜105的蝕刻係使用SF6/CHF3/Ar之混合氣體 漿。而且在W膜1 04與TiN的蝕刻，係以5ml /分鐘 量供給SF2氣體、20ml/分鐘的流量供給CI2氣體、 /分鐘的流量供給CHF3氣體、l〇〇ml/分鐘的流量 N2氣體，而使用壓力IPa的電漿。 第1圖（e)係表示藉由氫電漿去除光阻劑的光阻劑 步驟。在此，將基板溫度設定爲30°C，以5 〇ml/分 流量供給H2氣體，以50ml/分鐘的流量供給N2氣體 用壓力1 Pa的電漿。藉由該步驟，可去除光阻劑107 射防止膜106。 第1圖（c)係表示光阻劑去除結束後之形狀的示意 其中，以工作函數控制金屬的導體膜103而言，除了 以外，可使用TaN、TaSiN、Ru、RuO等。 第2圖係說明將半導體元件進行加工之加工裝置 漿鈾刻裝置）的說明圖。該裝置係被稱爲電子迴旋共 ECR)方式的裝置，將由電漿電源201所放出的電磁 過天線202、石英等透過電磁波的窗2 03而導入至真 圖案 107 對反 行乾 ，在 的電 的流 40ml 供給 去除 鐘的 ，使 與反 圖。 TiN (電 振（ 波通 空腔 201001535 室（減壓處理室）204內。腔室204內係以一定的壓力保 持蝕刻氣體，藉由前述電磁波將氣體電漿化，使反應性離 子入射至晶圓206 ’藉此進行蝕刻或光阻劑去除作用。 在保持晶圓206的試料台205係連接有用以將入射離 子加速的偏壓電源207。在該裝置中，係藉由電磁線圏 208而在腔室2 04內發生磁場。若以使電漿中的電子旋轉 (spin )頻率、與電漿電源20 i的頻率相一致的方式設定 磁場強度，電力會有效地被電漿吸收，可以低壓維持較高 的電漿密度。藉由改變流至電磁線圈2 0 8的電流値，可以 產生ECR的方式設定磁場強度。其中，用在蝕刻或光阻 劑去除的加工裝置係可使用例如感應耦合型（ICP )電漿 處理裝置等，而不限於ECR方式。 第3、4圖係說明本發明之效果的說明圖，第3圖係 表示習知技術之使用氧電漿的光阻劑去除之狀態圖，第4 圖係將使用氫電漿及氧電漿來去除光阻劑後之閘極配線的 阻抗率（平均單位剖面積的阻抗）進行比較之示意圖。其 中，圖中與第1圖所示部分爲相同的部分係標註相同的元 件符號且省略其說明。 在如第3圖所示使用氧電漿3 0 1的光阻劑去除中，係 在金屬的導體膜、亦即W膜104、TiN膜103之曝露在電 漿的側壁產生氧化層3 0 2。因此，當閘極配線寬爲1 〇〇nm 以下、尤其爲65nm以下時，如第4圖所示，氧化層302 的影響會變大，配線阻抗率會上升。 另一方面，當使用氫電漿來取代氧電漿時，金屬的導 -8- 201001535 體膜並未被氧化，因此配線阻抗率幾乎不會增加。其中， 當配線阻抗增加時，元件的消耗電力會增加，而且會妨礙 元件的高速動作。 基板溫度愈高，光阻劑去除速度愈大，但是若考慮到 金屬材料的變質等時，以20(TC以下爲佳。此外，以30°C 至100 °c爲更佳。 如上所示，藉由在進行具備有high-k膜及金屬材料（ 金屬閘極）之半導體元件的光阻劑去除時使用氫電漿，可 抑制元件（金屬閘極）劣化。 第5、6圖係說明第2實施形態的圖。在該例中，在 藉由氫電漿進行光阻劑去除時，藉由對矽基板（晶圓）施 加偏壓，提升處理速度。 如第2圖所示，電漿蝕刻裝置係具備有用以將入射至 晶圓206的離子加速的偏壓電源207。偏壓電源207的頻 率通常爲40 OKHz至20MHz左右的高頻。藉由該偏壓電源 ，將入射至晶圓206的離子加速，可提升光阻劑去除速度 〇 第5圖係顯示H2/ Ar之混合氣體電漿（IPa)中之晶 圓偏壓電力（40 OKHz )與光阻劑去除速度的關係圖。可知 光阻劑去除速度會隨著偏壓電力的增大而增加。 第6圖係顯示藉由晶圓偏壓電力之有無所造成之閘極 電極側壁之沈積物去除性的示意圖’第6圖（a)係表示未施 加晶圓偏壓的情形，第6圖（b)係表示已施加晶圓偏壓（ 5 0 W )的情形。 201001535 以形成金屬閘極601的金屬而言，當選擇TasiN等與 鹵素之化合物的蒸氣壓較低的材料時，係在蝕刻中在電極 側壁產生沈積物602。 未施加晶圓偏壓而進行光阻劑去除時，如第6圖（a)所 示，在光阻劑去除後會殘留沈積物6 0 2。當施加5 0 W作爲 晶圓偏壓時，如第6圖（b )所示可去除沈積物6 0 2。此係基 於藉由經加速之離子的能量而促進沈積物6 0 2的分解反應 的同時，藉由物理性濺鍍而將沈積物6 0 2去除所致。 其中，離子能量係與晶圓偏壓電壓的振幅V p p ( V ) 大致成正比。在第5圖所示之例中，偏壓電力爲50W時 ，Vpp爲350V，偏壓電力爲100W時，Vpp爲600V。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor processing method, particularly to a semiconductor processing method for processing a semiconductor having a metal deposition structure on a high dielectric constant insulating film. [Prior Art] For example, Patent Document 1 discloses that when a photoresist is removed on an insulating film having a low dielectric constant called an i〇w_k film which is formed on an interlayer insulating film of a semiconductor element, The technical content of a hydrogen atom or a neutral radical of a hydrogen molecule taken out from a plasma of a mixed gas of hydrogen and a rare gas. Here, in the method of removing a photoresist using oxygen plasma in general, it is revealed that the dielectric constant is increased due to deterioration of oxidation or the like of the l〇w-k film, and therefore a method of removing the photoresist without using oxygen is employed. In addition, the literature also discloses a technique for increasing the temperature of the substrate from 200 ° C to 400 ° C to increase the removal rate of the photoresist, and irradiating the NH 3 plasma or CF 4 plasma to deform the surface of the photoresist. The technique of removal. Patent Document 2 describes a cleaning method for removing contamination while preventing W degradation in a semiconductor element including a metal gate having a high-melting-point metal electrode such as W. Here, a technique for thermally oxidizing a wafer in an environment containing hydrogen and water vapor, and then cleaning the wafer by a liquid containing no hydrogen peroxide is disclosed. In this method, since the W layer is not oxidized, the W oxide layer is removed by washing. Further, in the paragraphs of -4 - 201001535 0 0 5 5 and 0 0 5 6 of the document, the technical contents of using oxygen plasma in the removal of the photoresist after dry etching of the element are described. (Patent Document 1) Japanese Laid-Open Patent Publication No. 2005-229130 (Patent Document 2) JP-A-2005-229130 SUMMARY OF INVENTION [Problems to be Solved by the Invention] As shown in Patent Document 2, in the prior art, Oxygen plasma is used in the removal of photoresist from the components of the metal gate structure. However, when the processing line width is 65 nm or less in the progress of the miniaturization of the element, the side wall of the metal electrode such as Ti, Ta, or Ru is oxidized by the oxygen used for the removal of the photoresist, so that the impedance is increased. There is a problem of component degradation. When the processing line width of the element is large, since the thickness of the oxide layer in the side wall is small as a whole, the increase in the aforementioned impedance does not cause a problem. Therefore, in the prior art, no solution to this point has been mentioned. The present invention has been made in view of the above-mentioned problems, and provides a metal conductor suitable for depositing on a high dielectric constant insulating film. A semiconductor processing method for performing microfabrication. (Means for Solving the Problem) The present invention employs the following means in order to solve the above problems. a photoresist film containing Ti or Ta or Ru formed on the insulating film having an insulating film containing Hf or Zr formed on the semiconductor substrate, and using -4: 201001535 for a photoresist formed on the conductor film In the semiconductor processing method for processing the conductor film in a plasma environment, the photoresist is removed in a plasma environment containing hydrogen and no oxygen. (Effect of the Invention) According to the present invention, in the semiconductor having the structure in which the metal conductor is deposited on the high dielectric constant insulating film, fine processing can be performed without deteriorating the element. [Embodiment] Hereinafter, preferred embodiments will be described with reference to the accompanying drawings. Fig. 1 is an explanatory view showing a semiconductor processing method according to a first embodiment, and Fig. 1(a) is a cross-sectional view showing a semiconductor element to be processed. As shown in Fig. 1(a), the semiconductor device is provided with a Si substrate 101, a HfSiON film 102 as a high dielectric constant insulating film sequentially formed on the Si substrate 101, and a conductor film for controlling a metal as a work function. The TiN film 103; the W film 1 0 4 as an electrode material; the S iN film 1 0 5 as a cover member (c ap ); and the anti-reflection film 106. Here, a high dielectric constant HfSiON film 102 is used as a gate insulating film (high-k film) of the FET, and a TiN film 103 is used as a metal gate, whereby a high-k film/metal gate can be formed. Constructed FET. The thickness of each of the films is 2 nm for the HfSiON film 102, 1 〇 nm for the TiN film 103, 50 nm for the w film 104, 50 nm for the SiN film 105, and 80 nm for the anti-reflection film 106, and the photoresist 107 is 200nm. 201001535 Fig. 1(a) shows the initial state of the process, and the photoresist 107 which is formed by the lithography is located at the uppermost layer. Fig. 1(b) shows the use of a thinned photoresist I 〇 7 ' radiation preventing film 106, SiN film 105, W film 104 after the step of trimming the photoresist to make the line width thin. The shape of the TiN film 103 after etching. The preparation was performed by etching the SiN film 105 in a plasma atmosphere of an Ar/02 mixed gas using a mixed gas slurry of SF6/CHF3/Ar. Further, in the etching of the W film 104 and TiN, SF2 gas was supplied in an amount of 5 ml/min, CI2 gas was supplied at a flow rate of 20 ml/min, CHF3 gas was supplied at a flow rate of /min, and a flow rate N2 gas of 10 ml/min was supplied. Use a plasma of pressure IPa. Figure 1 (e) shows the step of removing the photoresist from the photoresist by hydrogen plasma. Here, the substrate temperature was set to 30 ° C, H 2 gas was supplied at a flow rate of 5 〇 ml / minute, and a plasma of a pressure of 1 Pa for N 2 gas was supplied at a flow rate of 50 ml / minute. By this step, the photoresist 107 radiation preventing film 106 can be removed. Fig. 1(c) is a view showing the shape after completion of the removal of the photoresist. Among them, TaN, TaSiN, Ru, RuO or the like can be used in addition to the conductor film 103 for controlling the metal by the work function. Fig. 2 is an explanatory view showing a processing apparatus for processing a semiconductor element. This device is a device called an electron cyclotron (ECR) system. The electromagnetic antenna 202, quartz, etc., which are emitted from the plasma power source 201, are transmitted through the window 203 of the electromagnetic wave to the true pattern 107. The stream of 40ml is supplied to remove the clock, making it with the inverse map. TiN (electrical vibration (wave pass cavity 201001535 room (reduced pressure treatment chamber) 204. The chamber 204 maintains an etching gas at a constant pressure, and the gas is plasmatized by the electromagnetic wave to cause reactive ions to enter the crystal. The circle 206' is thereby subjected to etching or photoresist removal. The sample stage 205 holding the wafer 206 is connected to a bias power source 207 for accelerating incident ions. In this device, the magnet wire 208 is used. A magnetic field is generated in the chamber 024. If the magnetic field strength is set in such a manner that the electrons in the plasma rotate at a frequency corresponding to the frequency of the plasma power source 20 i, the power is effectively absorbed by the plasma, and the voltage can be low. Maintaining a higher plasma density. The magnetic field strength can be set by changing the current 流 flowing to the electromagnetic coil 206. The processing device used for etching or photoresist removal can use, for example, inductive coupling. An ICP plasma processing apparatus or the like is not limited to the ECR method. Figs. 3 and 4 are explanatory views for explaining the effects of the present invention, and Fig. 3 is a view showing the photoresist removal using the oxygen plasma of the prior art. State diagram, Fig. 4 is a schematic diagram comparing the impedance ratio (average unit sectional area impedance) of the gate wiring after removing the photoresist using hydrogen plasma and oxygen plasma. Among them, the part shown in Fig. 1 and Fig. 1 The same components are denoted by the same reference numerals and the description thereof will be omitted. In the photoresist removal using the oxygen plasma 301 as shown in Fig. 3, the metal conductor film, that is, the W film 104, TiN The film 103 is exposed to the sidewall of the plasma to form an oxide layer 320. Therefore, when the gate wiring width is 1 〇〇 nm or less, particularly 65 nm or less, as shown in FIG. 4, the influence of the oxide layer 302 may change. On the other hand, when hydrogen plasma is used instead of oxygen plasma, the metal film -8-201001535 is not oxidized, so the wiring impedance rate hardly increases. When the wiring impedance is increased, the power consumption of the device increases, and the high-speed operation of the device is hindered. The higher the substrate temperature, the higher the removal rate of the photoresist, but when considering the deterioration of the metal material, etc., the ratio is 20 (TC or less). Good. In addition, from 30 ° C to 100 ° C More preferably, as described above, by using a hydrogen plasma when removing a photoresist having a semiconductor element having a high-k film and a metal material (metal gate), deterioration of the element (metal gate) can be suppressed. 5 and 6 are views showing the second embodiment. In this example, when the photoresist is removed by hydrogen plasma, the processing speed is increased by applying a bias voltage to the germanium substrate (wafer). 2, the plasma etching apparatus is provided with a bias power source 207 for accelerating ions incident on the wafer 206. The frequency of the bias power source 207 is usually a high frequency of about 40 OKHz to 20 MHz. The power source accelerates the ions incident on the wafer 206 to improve the photoresist removal speed. The fifth figure shows the wafer bias power (40 OKHz) and the photoresist in the H2/Ar mixed gas plasma (IPa). Diagram of the removal rate of the agent. It is known that the photoresist removal rate increases as the bias power increases. Fig. 6 is a view showing the deposit removability of the sidewall of the gate electrode caused by the presence or absence of the wafer bias power. Fig. 6(a) shows the case where the wafer bias is not applied, Fig. 6 (Fig. 6) b) indicates the case where the wafer bias (50 W) has been applied. 201001535 In the case of forming a metal of the metal gate 601, when a material having a lower vapor pressure of a compound such as TasiN or a halogen is selected, a deposit 602 is generated on the side wall of the electrode during etching. When the photoresist is removed without applying a wafer bias, as shown in Fig. 6(a), deposits 60 2 remain after the photoresist is removed. When 50 W is applied as the wafer bias, the deposit 6 0 2 can be removed as shown in Fig. 6(b). This is based on the removal of deposits 602 by physical sputtering while promoting the decomposition reaction of the deposits by the energy of the accelerated ions. The ion energy is approximately proportional to the amplitude V p p ( V ) of the wafer bias voltage. In the example shown in Fig. 5, when the bias power is 50 W, Vpp is 350 V, and when the bias power is 100 W, Vpp is 600 V.

Vpp愈大，光阻劑去除速度即愈大，但是隨著Vpp的 增加，作爲閘極絕緣膜的Hf Si ON膜102及其下層的Si基 板1 0 1會因離子照射而受到損傷。若考慮到元件特性的測 定結果及光阻劑的去除速度，偏壓電壓的振幅Vpp係以 1500V以下爲佳。此外，以 500V(80W)至 l〇〇V(15W )爲更佳。 第7圖係說明第3實施形態的圖。在第7圖之例中， 係使用在金屬閘極金屬TiN膜107之上沈積有poly-Si膜 70 1的電極作爲閘極電極。藉由該電極構造，poly-Si膜 7 0 1係比第1圖所示的W更難以氧化，因此因氧電漿所導 致的劣化較小，但是由於TiN膜1 07的金屬部分受到氧化 ，因此仍然會產生元件的劣化。因此，在該構造元件中， 藉由氫電漿所進行的光阻劑去除係具有抑制元件特性劣化 -10- 201001535 的效果。 第8圖係表示蝕刻所使用之Η2/ΑΓ Ar的比例與光阻劑去除速度的關係圖。 未使用氧而去除光阻劑時，係有前述 載的方法，亦即使用氫原子或氫分子的中 。但是，該方法由於光阻劑去除能力比使 低，在金屬閘極加工後的光阻劑去除中， 此外，光阻劑去除所使用的氣體係陵 、H2/稀有氣體以外，在nh3等含氫氣體 同的效果。其中，將氫與N2或稀有氣體 合比係主要考慮到安全性的氫的稀釋。 第8圖係如前所述表示H2/ Ar之混i 比例與光阻劑去除速度的關係圖，當Ar 時，光阻劑去除速度會降低。因此，稀有 合比例係以5 0%以下爲佳。 其中，在含氫氣體混合CF4、CHF3、 鹵素的氣體時，含有金屬的沈積物的去除 素氣體的混合比例增加，即會發生蝕刻， 30%以下爲佳。此外，以5%至10%爲更佳 如以上說明所示，藉由本發明之實施 種爲了電晶體之高速化所提出之適於具有 金屬閘極之構造之半導體元件之微細加工 尤其，在製造具備有在被稱爲high-k 等介電常數較高的閘極絕緣膜上，沈積有 之混合氣體中之 專利文獻1所記 性自由基的方法 用電漿的方法較 容易出現殘渣。 隹了 h2、h2/ n2 的電漿亦具有相 加以混合時的混 含氣體中之Ar的 的比例超過 5 0 % 氣體或N2的混 nf3、SF6等含有 性會提升。若鹵 因此混合比係以 〇 形態，可提供一 被稱爲high-k/ 的加工方法。 膜的HfO或ZrO TiN 、 TaN 、 Ru -11 - 201001535 或Ru0等以控制工作函數爲目的的金屬之構造的閘極電極 之半導體元件中，在進行乾式蝕刻後的光阻劑去除時，藉 由使用含氫而未含氧的氣體的電漿，在不會使前述沈積有 TiN、TaN、Ru或RuO等金屬之構造的閘極電極氧化的情 形下，即可去除光阻劑。 【圖式簡單說明】 第1圖係說明第1實施形態之半導體加工方法的說明 圖。 第2圖係說明將半導體元件進行加工之加工裝置（電 漿蝕刻裝置）的說明圖。 第3圖係表示使用氧電漿之光阻劑去除之狀態圖。 第4圖係將使用氫電漿及氧電漿而將光阻劑去除後之 閘極配線的阻抗率進行比較之示意圖。說明設備監視控制 裝置的圖。 第5圖係說明第2實施形態的圖。 第6圖係說明第2實施形態的圖。 第7圖係說明第3實施形態的圖。 第8圖係表示混合氣體中的Ar的比例與光阻劑去除 速度的關係圖。 【主要元件符號說明】 1 0 1 : S i基板 1 02 : HfSiON 膜 -12- 201001535 103 : TiN 膜 1 04 : W 膜 105 : SiN 膜 106 :反射防止膜 1 〇 7 :光阻劑 1 0 8 :氫離子 2 0 1 :電漿電源 2 0 2 :天線 203 ：窗 2 0 4 :真空腔室 20 5 :試料台 206 :晶圓 2 0 7 :偏壓電源 2 〇 8 :電磁線圈 30 1 :氧離子 3 0 2 :氧化層 601 ： TaSiN 膜 6 0 2 :沈積物 701 ： poly-Si ΜThe larger the Vpp, the larger the photoresist removal rate, but as the Vpp increases, the Hf SiON film 102 as a gate insulating film and the underlying Si substrate 10 1 are damaged by ion irradiation. In consideration of the measurement result of the element characteristics and the removal rate of the photoresist, the amplitude Vpp of the bias voltage is preferably 1500 V or less. In addition, it is more preferable to use 500V (80W) to l〇〇V (15W). Fig. 7 is a view for explaining a third embodiment. In the example of Fig. 7, an electrode in which a poly-Si film 70 1 is deposited on a metal gate metal TiN film 107 is used as a gate electrode. With this electrode structure, the poly-Si film 7 0 1 is more difficult to oxidize than W shown in Fig. 1, and therefore the deterioration due to the oxygen plasma is small, but since the metal portion of the TiN film 107 is oxidized, Therefore, deterioration of components still occurs. Therefore, in this structural element, the photoresist removal by hydrogen plasma has an effect of suppressing deterioration of element characteristics -10- 201001535. Fig. 8 is a graph showing the relationship between the ratio of Η2/ΑΓ Ar used for etching and the removal rate of the photoresist. When the photoresist is removed without using oxygen, the above-described method is employed, that is, a hydrogen atom or a hydrogen molecule is used. However, this method is low in the removal ability of the photoresist, in the removal of the photoresist after the metal gate processing, and in addition to the gas system used for photoresist removal, H2/rare gas, etc., in nh3 and the like The same effect of hydrogen gas. Among them, the ratio of hydrogen to N2 or a rare gas is mainly based on the dilution of safe hydrogen. Fig. 8 is a graph showing the relationship between the ratio of H2/Ar and the removal rate of the photoresist as described above. When Ar is used, the removal rate of the photoresist is lowered. Therefore, the rare proportion is preferably less than 50%. Among them, when a gas containing CF4, CHF3 or halogen is mixed with a hydrogen-containing gas, the mixing ratio of the gas containing the deposit of the metal increases, that is, etching occurs, preferably 30% or less. Further, 5% to 10% is more preferably as described above, and the microfabrication of a semiconductor element suitable for a structure having a metal gate is proposed by the embodiment of the present invention for speeding up the transistor, in particular, in manufacturing. There is a method in which a plasma is used in a gate insulating film having a high dielectric constant such as high-k, and a method of using a plasma in the mixed gas deposited in the mixed gas is more likely to cause residue. When the plasma of h2, h2/n2 is mixed, the ratio of Ar in the mixed gas is more than 50%. The compatibility of gas or N2, such as nf3 and SF6, is improved. If the halogen is thus in the form of 〇, a processing method called high-k/ can be provided. In the semiconductor element of the gate electrode of the metal structure such as HfO or ZrO TiN , TaN , Ru -11 - 201001535 or Ru0 for controlling the work function, when the photoresist after dry etching is removed, A photoresist using a gas containing hydrogen and not containing oxygen can remove the photoresist without oxidizing the gate electrode having a structure in which a metal such as TiN, TaN, Ru or RuO is deposited. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is an explanatory view showing a semiconductor processing method according to a first embodiment. Fig. 2 is an explanatory view showing a processing apparatus (plasma etching apparatus) for processing a semiconductor element. Fig. 3 is a view showing a state in which a photoresist is removed using an oxygen plasma. Fig. 4 is a view showing the comparison of the impedance ratios of the gate wirings after the photoresist removal using hydrogen plasma and oxygen plasma. A diagram illustrating the device monitoring control device. Fig. 5 is a view for explaining the second embodiment. Fig. 6 is a view for explaining the second embodiment. Fig. 7 is a view for explaining a third embodiment. Fig. 8 is a graph showing the relationship between the ratio of Ar in the mixed gas and the removal rate of the photoresist. [Description of main component symbols] 1 0 1 : S i substrate 1 02 : HfSiON film-12- 201001535 103 : TiN film 1 04 : W film 105 : SiN film 106 : anti-reflection film 1 〇 7 : photoresist 1 0 8 : Hydrogen ion 2 0 1 : Plasma power supply 2 0 2 : Antenna 203 : Window 2 0 4 : Vacuum chamber 20 5 : Sample stage 206 : Wafer 2 0 7 : Bias power supply 2 〇 8 : Electromagnetic coil 30 1 : Oxygen ion 3 0 2 : oxide layer 601 : TaSiN film 6 0 2 : deposit 701 : poly-Si Μ

Claims (1)

201001535 十、申請專利範圍 1. 一種半導體加工方法，係具有形成在半導體基板上 之含有Hf或Zr的絕緣膜、及形成在該絕緣膜上之含有Ti 或Ta或Ru的導體膜，使用形成在該導體膜上的光阻劑， 在電漿環境中對前述導體膜進行加工的半導體加工方法， 其特徵爲： 將前述光阻劑在含氫而未含氧的氣體的電漿環境中去 除。 2. 如申請專利範圍第1項之半導體加工方法，其中， 前述含氫而未含氧的氣體係H2、H2與稀有氣體之混合氣 體、NH3、H2與N2與鹵素之混合氣體的任一者。 3 ·如申請專利範圍第1項之半導體加工方法，其中， 前述含氫而未含氧的氣體係H2、H2與稀有氣體之混合氣 體、在NH3、112與N2混合有CF4或CHF』SF6或NF3之 氣體的任一者。 4.如申請專利範圍第1項之半導體加工方法，其中， 前述導體膜係由工作函數控制金屬所構成，在前述導體膜 上係具備有由W所構成的電極層。 5 ·如申請專利範圍第1項之半導體加工方法，其中， 使用光阻劑而進行加工的前述導體膜的最小尺寸爲65nm 以下。 6 ·如申請專利範圍第1項之半導體加工方法，其中， 對前述半導體基板，施加用以朝向該半導體基板將電漿中 的離子加速的偏壓電壓。 -14 - 201001535 7.如申請專利範圍第6項之半導體加工方法，其中， 前述偏壓電壓的振幅爲1500V以下。 8 .如申請專利範圍第1項之半導體加工方法，其中， 光阻劑去除步驟中的晶圓溫度爲2 0 〇 °c以下。 9 一種半導體加工方法’係具備有：減壓處理室；對 該減壓處理室供給處理氣體的氣體供給手段；在前述減壓 處理室內載置並保持半導體基板的試料台；以及對被供糸合 至前述減壓處理室的處理氣體供給高頻能量而產生電漿的 電漿產生手段，藉由所產生的電獎而對前述半導體基板施 行電漿蝕刻處理的半導體加工方法，其特徵爲： 在前述試料台上載置依序形成有：含有Hf或Zr的高 介電常數絕緣膜、含有Ti或Ta或RU的工作函數控制金 屬的導體膜、及光阻劑的半導體基板，使用前述光阻劑， 對前述導體膜進行加工之後’在供給含氫而未含氧的氣體 作爲前述處理氣體的狀態下在處理室內產生電漿，而去除 前述光阻劑。 1 0 · —種半導體加工方法’係具備有··減壓處理室； 對該減壓處理室供給處理氣體的氣體供給手段；在前述減 壓處理室內載置並保持半導體基板的試料台；以及對被供 給至前述減壓處理室的處理氣體供給高頻能量而產生電娥 的電漿產生手段，藉由所產生的電漿而對前述半導體基板 施行電漿蝕刻處理的半導體加工方法，其特徵爲： 在前述試料台上載置依序形成有：含有…或Zr的高介 電常數絕緣膜、含有TiSTa*Ru的工作函數控制金屬的導 201001535 體膜、及光阻劑的半導體基板，使用前述光阻劑，對前 導體膜進行加工之後，在供給含氫而未含氧的氣體作爲 述處理氣體，而且對前述試料台施加基板偏壓的狀態下 處理室內產生電漿，而去除前述光阻劑。 述 W- 刖 在 -16 -201001535 X. Patent Application No. 1. A semiconductor processing method comprising an insulating film containing Hf or Zr formed on a semiconductor substrate, and a conductor film containing Ti or Ta or Ru formed on the insulating film, which is formed by using A photoresist processing method on a conductor film, wherein the photoresist film is processed in a plasma environment, wherein the photoresist is removed in a plasma environment containing hydrogen and oxygen-free gas. 2. The semiconductor processing method according to claim 1, wherein the hydrogen-containing and non-oxygen-containing gas system H2, a mixed gas of H2 and a rare gas, and any one of a mixed gas of NH3, H2 and N2 and a halogen . 3. The semiconductor processing method according to claim 1, wherein the hydrogen-containing and non-oxygen-containing gas system H2, a mixed gas of H2 and a rare gas, and a mixture of NH3, 112 and N2 have CF4 or CHF SF6 or Any of the gases of NF3. 4. The semiconductor processing method according to claim 1, wherein the conductor film is made of a work function control metal, and an electrode layer made of W is provided on the conductor film. 5. The semiconductor processing method according to claim 1, wherein the minimum size of the conductor film processed by using the photoresist is 65 nm or less. The semiconductor processing method according to claim 1, wherein a bias voltage for accelerating ions in the plasma toward the semiconductor substrate is applied to the semiconductor substrate. [14] The semiconductor processing method of claim 6, wherein the amplitude of the bias voltage is 1500 V or less. 8. The semiconductor processing method according to claim 1, wherein the wafer temperature in the photoresist removal step is 20 〇 ° C or less. A semiconductor processing method includes: a reduced pressure processing chamber; a gas supply means for supplying a processing gas to the reduced pressure processing chamber; a sample stage on which the semiconductor substrate is placed and held in the reduced pressure processing chamber; and a supply rack A semiconductor processing method for applying a plasma etching treatment to the semiconductor substrate by means of a generated electric prize by supplying a high-frequency energy to the processing gas of the decompression processing chamber to generate a plasma, and the semiconductor processing method is characterized in that: A high dielectric constant insulating film containing Hf or Zr, a conductor film containing a working function control metal of Ti or Ta or RU, and a semiconductor substrate of a photoresist are sequentially formed on the sample stage, and the photoresist is used. After the conductor film is processed, a plasma is generated in the processing chamber while a gas containing hydrogen and no oxygen is supplied as the processing gas, and the photoresist is removed. a semiconductor processing method includes a decompression processing chamber, a gas supply means for supplying a processing gas to the decompression processing chamber, and a sample stage in which the semiconductor substrate is placed and held in the decompression processing chamber; A semiconductor processing method for applying a plasma etching treatment to the semiconductor substrate by generating plasma by supplying high-frequency energy to the processing gas supplied to the decompression processing chamber to generate electricity, and the plasma processing method is characterized by the generated plasma. In the above-described sample stage, a high dielectric constant insulating film containing ... or Zr, a semiconductor film of a work function control metal containing a TiSTa*Ru, and a semiconductor film of a photoresist, and the like are used. The photoresist is processed after the front conductor film is processed, and a gas containing hydrogen and not containing oxygen is supplied as the processing gas, and plasma is generated in the processing chamber while the substrate bias is applied to the sample stage, and the photoresist is removed. Agent. W- 刖 at -16 -
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