200952069 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種在電容耦合型之電漿處理裝置中對 被處理基板施行蝕刻加工的電漿處理方法，尤其係關於強 化蝕刻遮罩所用阻劑圖案之蝕刻耐性而達成薄膜加工之精 度提升·安定化的電漿處理方法及電腦可讀取記憶媒體。 © 【先前技術】 在半導體元件或FPD (Flat Panel Display，平面顯示 器）之製造製程所使用的蝕刻係將藉由微影技術所形成的 阻劑圖案作爲遮罩，將被處理基板（半導體晶圓、玻璃基 板等）表面的薄膜加工成所希望的電路圖案。自以往以來 ，在單片式蝕刻大多採用電容耦合型的電漿蝕刻裝置。 一般而言，電容耦合型的電漿蝕刻裝置係在作爲真空 腔室所構成的處理容器內平行配置上部電極與下部電極， 在下部電極之上載置被處理基板，在兩電極間施加高頻。 如此一來，在兩電極之間發生因處理氣體之高頻放電所產 生的電漿，藉由電漿中的自由基或離子，對基板表面以所 希望圖案施行蝕刻加工。 但是，在目前最尖端LSI製程中，在光微影使用ArF 準分子雷射曝光技術，在阻劑使用適於ArF準分子雷射光 之波長（1 9 3 n m )的化學放大系阻劑（A r F阻劑）。但是 ，ArF阻劑容易獲得高感度、高解析度’另一方面，其電 漿耐性或蝕刻耐性較弱，而且由於以超微細的尺寸予以圖 -5- 200952069 案化，因此在電漿蝕刻時發生阻劑圖案倒毀、表面粗糙、 圖案側壁變得凹凸不平，而會造成招致所謂LER ( Line Edge Roughness)或 LWR( Line Width Roughness)等凹凸變形 或蛇行變形的問題。 以往’以用以提高ArF阻劑之蝕刻耐性的技法而言， 已知一種藉由電子束照射、UV照射、h2或HBr電漿照射 、離子束照射等，來將阻劑進行改質的方法。 (專利文獻1)日本特開2005-243681 【發明內容】 (發明所欲解決之課題） 但是，上述之習知的阻劑改質法均使用專用的處理容 器（腔室），隨之造成裝置成本增大與產率降低。此外， 在曝光前，若使用電子束照射法、UV照射法或離子束照 射法，阻劑的光透過性會依膜質變化而改變，容易使曝光 性能惡化。另一方面，會有在曝光後，若使用離子束照射 法，由於離子撞撃，阻劑圖案容易受到損傷，若使用電子 束照射法或UV照射法，阻劑圖案容易發生錐狀的收縮變 形或CD變化等問題。此外，H2或HBr電漿照射法係在腔 室內殘留氫，難以取得製程的重現性，在運用安定性或量 產性方面具有課題。 本發明係鑑於該習知技術之問題點而硏創者，目的在 於提供一種利用電容耦合型的電漿處理裝置，藉由簡便且 有效的阻劑改質法來強化阻劑圖案的蝕刻耐性，而使薄膜 -6- 200952069 加工的精度•安定性提升的電漿處理方法及電 億媒體。 (解決課題之手段） 爲達成上述目的，本發明之第1觀點中的 法係在可爲真空的處理容器內將第1電極與第 預定間隔作平行配置，與前述第1電極相對向 Φ 極支持被處理基板，將前述處理容器內進行真 定壓力，在前述第1電極與前述第2電極之間 供給含有蝕刻劑氣體的第1處理氣體，對前述 第2電極施加第1高頻而在前述處理空間生成 刻劑氣體的電漿，在前述電漿之下，將前述基 工膜以形成在該被加工膜之上的阻劑圖案作爲 蝕刻的電漿處理方法，其特徵爲：在前述處理 對前述基板在前述被加工膜之蝕刻處理更爲之 〇 阻劑改質處理而言，具有：將前述處理容器內 氣成預定壓力的工程；在前述第1電極與前述 間的處理空間供給第2處理氣體的工程；對前 或前述第2電極施加前述第1高頻，在前述處 前述第2處理氣體之電漿的工程；及以提升前 之蝕刻耐性的方式，在前述處理容器內在遠離 場所’對曝露在電漿的預定DC施加構件施加 流電壓’將由前述DC施加構件所被釋放出的 前述阻劑圖案的工程。 腦可讀取記 電漿處理方 2電極隔著 而以第2電 空排氣成預 的處理空間 第1電極或 前述第1触 板上的被加 遮罩而進行 容器內，以 前所進行的 進行真空排 第2電極之 述第1電極 理空間生成 述阻劑圖案 gij述基板的 負極性的直 電子打入至 200952069 上述第1觀點中的電漿處理方法係在對基板上的被加 工膜進行蝕刻加工之前，利用同一硬體而在基板上的阻劑 圖案打入電子而將電子浸入部分（表層部或內部深處）進 行改質。一面利用同一硬體，一面與原本的蝕刻加工獨立 進行，因此可任意選定處理條件，尤其可任意選定施加至 DC施加構件之負極性直流電壓的絕對値，可任意控制改 質層的厚度。 最好以由DC施加構件所被釋放出的電子以l〇〇〇eV 以上的能量被打入至前述阻劑圖案的方式來選定負極性直 流電壓的絕對値，最好爲1 000V以上，藉此可獲得厚度數 十nm以上的改質層。 更好係以由DC施加構件所被釋放出的電子以1 500eV 以上的能量被打入至阻劑圖案的方式來選定負極性直流電 壓的絕對値，最好爲1500V以上，藉此可獲得厚度i〇〇nm 以上的改質層。 此外，在上述阻劑改質處理中，對第1電極以所希望 的功率施加電漿生成用的第1高頻，當對第2電極施加離 子引入控制用的第2高頻時’朝向使第2電極上的離子鞘 被打入至阻劑圖案的電子能量降低的方向作用。因此，形 成在第2電極上的自偏壓係儘量低即可，以ι〇〇ν以下爲 佳。此外，第2高頻的功率係儘量低即可，最好在5 0 W 以下’更好係實質上爲〇W’或者對第2電極並未施加高 頻。 此外，在本發明之較佳一態樣中，在上述阻劑改質處 -8- 200952069 理之後、被加工膜之鈾刻處理之前，在同一處理容器內， 進行將阻劑圖案以與圖案面呈平行的橫方向切削成所希望 的尺寸的修整（trimming )處理。該修整處理係一種電漿 蝕刻加工，包含：將處理容器內進行真空排氣成預定壓力 的工程；在第1電極與第2電極之間的處理空間供給含有 蝕刻劑氣體的第3處理氣體的工程：對第1電極或第2電 極施加第1高頻而在處理空間生成第3處理氣體之電漿的 φ 工程；及在所生成的電漿之下，將阻劑圖案蝕刻至所希望 圖案的工程。此時，處理對象的阻劑圖案係接受前工程的 阻劑改質處理而提升改質層的蝕刻耐性或電漿耐性，因此 肩部掉落等變形會較少，而可以所希望的縮小率來接受高 精度的修整加工。 在本發明之電漿處理方法中，DC施加構件典型而言 係與基板呈正對面相向的第1電極，但是亦可將與基板呈 斜向相向的構件（例如容器側壁）使用或兼用爲DC施加 φ 構件。 第1電極的材質係可適當使用含有Si的導電材料， 但是可以對被加工膜之蝕刻的製程爲基準而選定任意材質 。此外，當第1電極由含有Si的導電材料所構成時，除 了防止在該電極面沈積聚合物而安定保持直流性的導電性 以外，亦可作爲阻劑改質處理用的第2處理氣體而適當使 用含有鹵素氣體的氣體（例如氟碳化合物（fluorocarbon )氣體）。 本發明之第2觀點中的電漿處理方法係在可爲真空的 -9- 200952069 處理容器內將第1電極與第2電極隔著預定間隔作平行配 置’與前述第1電極相對向而以第2電極支持被處理基板 ’將前述處理容器內進行真空排氣成預定壓力，在前述第 1電極與前述第2電極之間的處理空間供給含有蝕刻劑氣 體的第1處理氣體，對前述第1電極或第2電極施加第1 高頻而在前述處理空間生成前述處理氣體的電漿，在前述 電漿之下’將前述基板上的被加工膜以形成在該被加工膜 之上的阻劑圖案作爲遮罩而進行蝕刻的電漿處理方法，其 _ 特徵爲：（1)在前述處理容器內對前述基板正在進行前 述被加工膜之蝕刻的中途，以使前述阻劑圖案之蝕刻耐性 提升的方式，在前述處理容器內在遠離前述基板的場所被 曝露在電漿之預定的D C施加構件施加負極性的直流電壓 ，將由前述DC施加構件所被釋放出的電子打入至前述基 板上的阻劑圖案；（2 )與前述被加工膜的蝕刻並行，以 前述阻劑圖案在與圖案面呈平行的橫方向被切削成所希望 的尺寸的方式，來選定前述處理容器內的氣體壓力及蝕刻 Q 時間。 如上所示，本發明之第2觀點中的電漿處理方法係一 面對基板上的被加工膜施行原本的電漿蝕刻處理’ 一面在 同一處理容器內在同一電漿之下對基板上的蝕刻遮罩所使 用的阻劑圖案打入電子，依改質效果而使其蝕刻耐性強化 ，而使遮罩選擇比提升，並且以氣體壓力及蝕刻時間爲參 數，而對阻劑圖案施行所希望的修整處理。 本發明之第3觀點中的電漿處理方法係在可爲真空的 -10- 200952069 處理容器內將第1電極與第2電極隔著預定間隔作平行配 置，與前述第1電極相對向而以第2電極支持被處理基板 ，將前述處理容器內進行真空排氣成預定壓力，在前述第 1電極與前述第2電極之間的處理空間供給含有蝕刻劑氣 體的處理氣體，對前述第1電極或第2電極施加第1高頻 而在前述處理空間生成前述處理氣體的電漿，在前述電漿 之下，將前述基板上的被加工膜以形成在該被加工膜之上 ❹ 的阻劑圖案作爲遮罩而進行蝕刻的電漿處理方法，其特徵 爲：在前述處理容器內對前述基板正在進行前述被加工膜 之蝕刻的中途，以使前述阻劑圖案之蝕刻耐性提升的方式 ’在前述處理容器內在遠離前述基板的場所被曝露在電漿 之預定的DC施加構件施加負極性的直流電壓，將由前述 D C施加構件所被釋放出的電子打入至前述基板上的阻劑 圖案。 如上所示’本發明之第3觀點中的電漿處理方法係一 Φ 面對基板上的被加工膜施行原本的電漿蝕刻處理，一面在 同一處理容器內在同一電漿之下對基板上的蝕刻遮罩所使 用的阻劑圖案打入電子’依改質效果而使其蝕刻耐性強化 ，而使遮罩選擇比提升。 此外’本發明中的電腦可讀取記憶媒體係記憶有在電 腦上進行動作之控制程式的電腦記憶媒體，其特徵爲：前 述控制程式係在執行時，以進行本發明之上述電漿處理方 法的方式來控制電漿處理裝置。 -11 - 200952069 (發明之效果） 根據本發明之電漿處理方法或電腦可讀取記憶媒體， 藉由如上所述之構成及作用，利用電容耦合型的電漿蝕刻 裝置，藉由簡便且有效的阻劑改質法來強化阻劑圖案的蝕 刻耐性，可使薄膜加工的精度.安定性提升。 【實施方式】 以下參照附圖’說明本發明之較佳實施形態。 0 在第1圖顯示在本發明之電漿處理方法中所使用之電 漿處理裝置之構成。該電漿處理裝置係作爲電容耦合型的 電漿蝕刻裝置所構成，具有例如鋁或不銹鋼等金屬製圓筒 型腔室（處理容器）10。腔室10係被安全接地。 在腔室10內係以水平配置有載置作爲被處理基板之 例如半導體晶圓W的圓板狀基座1 2作爲下部電極。該基 座1 2係由例如鋁所構成，由腔室1 〇的底部朝垂直上方延 伸的絶緣性筒狀支持部14所支持。在沿著該筒狀支持部 u 14的外周由腔室10底部朝垂直上方延伸的導電性筒狀支 持部（內壁部）16與腔室10的側壁之間形成有環狀的排 氣路18,在該排氣路18的入口安裝有環狀的排氣環（擋 板（baffle )) 20，在排氣路18的底部設有排氣口 22。 在排氣口 22係隔著排氣管24連接有排氣裝置26。排氣裝 置26係具有渦輪分子栗等真空泵，可將腔室10內的處理 空間減壓至所希望的真空度。在腔室1 〇的側壁係安裝有 將半導體晶圓W的搬入出口作開閉的閘閥2 8。 -12- 200952069 高頻電源30隔著整合器32及下部供電棒36與基座 12作電性連接。在此，高頻電源30係輸出有助於對基座 12上之半導體晶圓W引入離子之頻率（通常爲13.5 6MHz以 下）的高頻LF。整合器32係構成爲：在高頻電源30側的 阻抗與負荷（主要爲電極、電漿、腔室）側的阻抗之間取得 匹配（matching )，而且可自動地調整匹配點（matching point ) ° 0 基座12係具有比半導體晶圓W略大的直徑或口徑。 在基座12之上係載置有處理對象的半導體晶圓W，以包 圍該半導體晶圓W的方式設有聚焦環（補正環）38。 在基座12的上面係設有晶圓吸附用的靜電吸盤40。 該靜電吸盤40係在膜狀或板狀的介電質之中夾持片狀或 網目狀DC電極。被配置在腔室10之外的直流電源42透 過開關44及高壓供電線46而與該DC電極作電性連接。 由直流電源42將直流電壓施加至DC電極，藉此可藉庫侖 〇 力將半導體晶圓W吸附保持在靜電吸盤40上。 在基座12的內部係設有例如朝圓周方向延伸的環狀 冷媒室48。在該冷媒室48，係由冷卻器單元（未圖示） 經由配管5 0、5 2而循環供給預定溫度的冷媒，例如冷卻 水。藉由冷媒的溫度，可控制靜電吸盤40上之半導體晶 圓W的溫度。接著，爲了使半導體晶圓w與基座1 2熱結 合’來自傳熱氣體供給部（未圖示）的傳熱氣體例如He 氣體係透過氣體供給管54及基座12內部的氣體通路56 而被供給至靜電吸盤40與半導體晶圓w的接觸界面。 -13- 200952069 在腔室1 〇的頂棚係設有與基座1 2平行相對面而兼作 淋洗頭的上部電極60。該上部電極（淋洗頭）60係具有 與基座12相對面的電極板62;及將該電極板62可由其背 後（上）裝卸地予以支持的電極支持體64，在電極支持體 64的內部設有氣體擴散室66，將由該氣體擴散室66貫穿 至基座12側之多數氣體排出孔68形成在電極支持體64 及電極板62。電極板62與基座12之間的空間成爲電漿生 成空間或處理空間PS。氣體擴散室66係透過氣體供給管 70而連接於處理氣體供給部72。 在上部電極60中，在處理時曝露在電漿的電極板62 的材質極爲重要。該電極板62在該實施形態中係具有作 爲DC施加構件的功能，因此電極表面可維持直流的導電 性，而且以即使藉由來自電漿之離子的入射而被濺鍍，亦 不會對製程造成不良影響的材質爲佳，例如可適於使用Si 、SiC等含Si導電材或C (碳）。電極支持體64係由例 如經耐酸鋁處理的鋁所構成即可。在上部電極60與腔室 1〇之間係被***有環狀的絶緣體65，上部電極60係在電 氣浮接狀態下被安裝在腔室10。 在上部電極60，透過整合器76及上部供電棒78而電 性連接有高頻電源74。該高頻電源74係輸出有助於生成 電漿之頻率（通常爲40MHz以上）的高頻HF。整合器76 係構成爲：在高頻電源74側之阻抗與負荷（主要爲電極 、電漿、腔室）側之阻抗之間取得匹配，而且可自動地調 整匹配點。 -14- 200952069 被配置在腔室10之外的可變直流電源80的輸出端子 係透過開關82及直流供電線84而與上部電極60作電性 連接。可變直流電源80係構成爲可輸出例如-2000至 + 1 000V的直流電壓VDC。 被設在直流供電線8 4之中途的濾波器電路8 6係構成 爲：將來自可變直流電源80的直流電壓 VDC以貫穿（ through )施加至上部電極60，另一方面將由基座12通過 φ 處理空間PS及上部電極60而進入至直流供電線84的高 頻朝接地線流通而不會朝可變直流電源80側流通。 此外，在腔室10內，在以面向處理空間PS之適當部 位而言，例如擋板20的上面或導電性支持構件16的頂部 附近或上部電極60的半徑方向外側，被安裝有例如由Si 、S i C等導電性材料所構成的環狀的D C接地零件（直流 接地電極）88。該DC接地零件88係透過接地線90而被 常時接地。 〇 該電漿處理裝置內的各部例如排氣裝置26、高頻電源 30、74、開關44、82、處理氣體供給部72、可變直流電 源80、冷卻單元（未圖示）、傳熱氣體供給部（未圖示） 等之各個的動作及裝置全體的動作（順序）係藉由由例如 微電腦所構成的控制部1 1 〇 (第1 9圖）所控制。 在該電漿處理裝置中，爲了對基座12上的半導體晶 圓W進行蝕刻加工，由處理氣體供給部72將含有餽刻劑 氣體的處理氣體以預定流量導入至腔室1〇內，藉由排氣 裝置26將腔室10內的壓力調節爲設定値。此外，由高頻 •15- 200952069 電源74將電漿生成用的第1高頻HF(40MHz以上）透過 整合器76及上部供電棒78而施加至上部電極60的同時 ，由高頻電源30將離子引入控制用的第2高頻LF( 13.56MHz以下）透過整合器32及下部供電棒36而施加 至基座12。此外，將開關44形成爲導通（on)，藉由靜 電吸附力，在靜電吸盤40與半導體晶圓W之間的接觸界 面封入傳熱氣體（He氣體）。由淋洗頭60所排出的處理 氣體係在兩電極12、60間藉由高頻的放電而電槳化，藉 υ 由以該電漿所生成的自由基或離子，半導體晶圓 W上的 被蝕刻膜會被蝕刻成所希望圖案。 該電漿處理裝置係由高頻電源74對上部電極60施加 40MHz以上（更好爲60MHz以上）之適於生成電漿之較 高頻率的第1高頻HF，藉此將電漿以較佳的解離狀態予 以高密度化，即使在較爲低壓的條件下亦可形成高密度電 漿。與此同時，對基座12施加13.56MHz以下之適於引入 離子之較低頻率的第2高頻LF，藉此可對半導體晶圓W Q 的被蝕刻膜施行選擇性較高的異向性蝕刻。不過，電漿生 成用的第1高頻HF係不管在什麼樣的電漿製程下均必須 使用，但是離子引入控制用的第2高頻LF會有依製程而 未被使用的情形。 此外，在電漿蝕刻當中，藉由對上部電極60由可變 直流電源80施加直流電壓（通常爲-900V〜0V的範圍內 )，均可使電漿著火安定性、阻劑選擇性、蝕刻速度、蝕 刻均一性等提升。 -16- 200952069 在如上所述之電漿蝕刻中，在用以將半導體晶圓 w 表面之被加工膜圖案化的蝕刻遮罩係使用在該被加工膜之 上預先藉由光微影所形成的阻劑圖案。在此，光微影爲了 獲得高解析度而在曝光用束採用例如ArF準分子雷射光（ 波長193nm)時，係使用適於其之高感度的化學放大系阻 劑（ArF阻劑）。 φ (第1實施形態） 接著，說明本發明之第1實施形態中的電漿處理方法 。在該實施形態中，對於被搬入至腔室10之處理對象的 半導體晶圓W，在如上所述之對被加工膜進行電漿蝕刻處 理之前，依序對阻劑圖案進行阻劑改質處理與修整處理作 爲前處理。 關於第2圖，說明多層阻劑法中之修整處理之一例。 圖中，最上層（第1層）的膜100係ArF阻劑的阻劑圖案 〇 ，第2層的膜102係B ARC (反射防止膜：第1被蝕刻膜 )，第3層的膜104係作爲最終遮罩的SiN層（第2被蝕 刻膜），最下層的膜1 06係原本（最終）的被加工膜例如 Si〇2層（第3被蝕刻膜）。在SiN膜104及BARC102之 成膜係採用CVD (化學真空蒸鍍法）或藉由旋塗（spin_ on)的塗布法，在光阻1〇0的圖案化係使用光微影。 如第2圖的（A)所示，修整處理係將以光微影所形成 的阻劑圖案1 00以與圖案面呈平行的橫方向切削而成形爲 如第2圖的（B)所示之略細之所希望尺寸之圖案的加工。 -17- 200952069 若將該成形爲較細的阻劑圖案100作爲遮罩而將B ARC 102 及SiN膜104依序蝕刻，即可如第2圖的（C)所示，將與 阻劑圖案1〇〇相同細的圖案作成或轉印在SiN膜104。之 後雖省略圖示，藉由灰化來去除阻劑圖案1〇〇及BARC102 的殘膜，以SiN圖案104爲遮罩來對基底膜（Si02層） 106進行鈾刻。 在阻劑製程中欲由最初以所希望的窄細尺寸形成阻劑 圖案時，在光微影工程中（尤其顯影時）會有引起阻劑倒 壞的情形。在該情形下，在光微影工程之後，會採用藉由 如上所述的修整處理來將阻劑圖案縮窄至目的尺寸的手法 。該修整處理係可利用用以蝕刻原本的被加工膜的電漿鈾 刻裝置來實施。 但是，以往由於ArF阻劑的蝕刻耐性（電漿耐性）較 弱，因此藉由進行供修整處理之用的電漿蝕刻，阻劑圖案 100 —面發生肩部破壞等形狀變化，一面過度易於切削， 修整的加工精度不佳。 因此，在該實施形態中，在修整處理之前，在相同的 電獎處理裝置（第1圖）內，進行用以強化阻劑圖案10 0 之蝕刻耐性的阻劑改質處理。如第3圖所示，該阻劑改質 處理係對阻劑圖案1 〇〇打入高能量的電子e·，使ArF阻劑 的樹脂由表層最好至內部深處爲止較深地變質，作爲一種 電漿處理來進行。 亦即，由處理氣體供給部72將預定的處理氣體以適 當流量導入至腔室10內，藉由排氣裝置26，將腔室10內 -18- 200952069 第 78 將 整 關 與 ) 由 流 爲.. 電 鞘 與 子 電 放 著 鞘 另 失 的壓力調節爲設定値，由高頻電源74，將電漿生成用的 1高頻HF ( 40MHz以上）透過整合器76及上部供電棒 施加至上部電極60。此外，視需要，由高頻電源30， 離子引入控制用的第2高頻LF( 13.56MHz以下）透過 合器32及下部供電棒36而施加至基座12。此外，將開 44設爲導通（on)，藉由靜電吸附力，在靜電吸盤40 半導體晶圓W之間的接觸界面封入傳熱氣體（He氣體 0 。由淋洗頭60所排出的處理氣體在兩電極12、60間藉 高頻放電而作解離·電離而生成電漿PR。 在此，如第4圖所示，若由可變直流電源80將直 電壓Vdc以負極性的高壓（如後所述，最好以絕對値 1 000V以上’更好以絕對値爲1 500V以上）施加至上部 極60’形成在上部電極60與電漿PR之間的上部離子 SHu會變厚’其護皮電壓（sheath voltage) Vu係成爲 直流電壓VDC大致相等的大小。藉此，電漿pR中的離 ❹ (+ )在上部離子鞘SHu的電場中被加速而撞擊到上部 極60 (電極板62)時的離子衝撞能量會增加，藉由7 電而由電極板62所被釋放出的2次電子e·會變多。接 ’由電極板62所被釋放出的2次電子e·係在上部離子 SHu的電場中朝向離子的反方向被加速而穿過電漿pr， 外橫穿下部離子鞘SHL，以預定的高能量被打入至如第 圖所示基座12上之半導體晶圓W表面的阻劑圖案100 此時’ 2次電子e·雖以等速度通過無電場的電漿PR中 但是在下部離子鞘SHl內係在反方向的電場被減速而流 -19- 200952069 電子能量的一部分。因此’被形成在基座12上的下部離 子鞘SHl的護皮電壓Vl或自偏壓vd。。係愈低愈好’通常 以100 V以下爲宜。因此，以將被施加至基座12的第2高 頻LF( 13.56MHz以下）的功率選定爲50W以下爲佳，更 佳爲0W。 根據該實施形態中的阻劑改質處理法’由第4圖的原 理，愈加大施加至上部電極60的負極性直流電壓vdc的 絕對値，愈加大被打入至半導體晶圓W上之阻劑圖案的 電子能量，可加大阻劑圖案中之電子浸入深度’亦即可加 大改質深度。 在第5圖中以SEM照片顯示該實施形態中藉阻劑改 質處理之實驗所得之改質效果。主要的處理條件係如下所 不 。 阻劑：丙烯酸酯基質用的ArF阻劑 處理前的阻劑膜厚：261 nm 處理氣體：CF4= lOOsccm 腔室內的壓力：1 OOmTorrBACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma processing method for etching a substrate to be processed in a capacitively coupled plasma processing apparatus, and more particularly to a resistor for enhancing an etching mask. The etching resistance of the pattern is achieved, and the precision of the film processing is improved, the plasma processing method is stabilized, and the computer can read the memory medium. © [Prior Art] The etching method used in the manufacturing process of a semiconductor device or a FPD (Flat Panel Display) uses a resist pattern formed by lithography as a mask to process a substrate (semiconductor wafer). The film on the surface of the glass substrate, etc. is processed into a desired circuit pattern. In the past, a capacitive coupling type plasma etching apparatus has been used for monolithic etching. In general, in a capacitively coupled plasma etching apparatus, an upper electrode and a lower electrode are arranged in parallel in a processing chamber formed as a vacuum chamber, and a substrate to be processed is placed on a lower electrode, and a high frequency is applied between the electrodes. As a result, a plasma generated by high-frequency discharge of the processing gas occurs between the electrodes, and the substrate surface is etched in a desired pattern by radicals or ions in the plasma. However, in the current state-of-the-art LSI process, ArF excimer laser exposure technology is used in photolithography, and a chemical amplification resist (A) suitable for ArF excimer laser light (1 3 3 nm) is used in the resist. r F resist). However, the ArF resist is easy to obtain high sensitivity and high resolution. On the other hand, its plasma resistance or etching resistance is weak, and since it is in the ultra-fine size, it is shown in Fig.-5-200952069, so during plasma etching. The occurrence of the resist pattern is reversed, the surface is rough, and the side walls of the pattern become uneven, which causes problems such as so-called LER (Line Edge Roughness) or LWR (Line Width Roughness) deformation or meandering. Conventionally, in order to improve the etching resistance of an ArF resist, a method of modifying a resist by electron beam irradiation, UV irradiation, h2 or HBr plasma irradiation, ion beam irradiation, or the like is known. . (Patent Document 1) Japanese Laid-Open Patent Publication No. 2005-243681 [Problems to be Solved by the Invention] However, the conventional resist modification method described above uses a dedicated processing container (chamber), which causes a device. The cost increases and the yield decreases. Further, before the exposure, if the electron beam irradiation method, the UV irradiation method, or the ion beam irradiation method is used, the light transmittance of the resist changes depending on the film quality, and the exposure performance is easily deteriorated. On the other hand, after exposure, if the ion beam irradiation method is used, the resist pattern is easily damaged due to ion collision, and if the electron beam irradiation method or the UV irradiation method is used, the resist pattern is likely to undergo cone-shaped shrinkage deformation. Or CD changes and other issues. Further, in the H2 or HBr plasma irradiation method, hydrogen remains in the chamber, and it is difficult to obtain reproducibility of the process, and there is a problem in the application of stability or mass productivity. The present invention has been made in view of the problems of the prior art, and an object of the present invention is to provide a plasma processing apparatus using a capacitive coupling type, which enhances the etching resistance of a resist pattern by a simple and effective resist modification method. The plasma processing method and electric billion media that improve the precision and stability of the film -6-200952069 processing. (Means for Solving the Problem) In order to achieve the above object, in a first aspect of the present invention, a first electrode is disposed in parallel with a predetermined interval in a vacuum processing container, and the first electrode is opposed to the Φ pole. Supporting the substrate to be processed, performing a predetermined pressure in the processing chamber, supplying a first processing gas containing an etchant gas between the first electrode and the second electrode, and applying a first high frequency to the second electrode The processing space generates a plasma of the marking gas, and the underlying film is formed by using the resist pattern formed on the processed film as an etched plasma processing method under the foregoing plasma, characterized in that: The process for modifying the etching of the substrate on the processed film further includes: a process of forming a gas in the processing chamber to a predetermined pressure; and supplying the processing space between the first electrode and the first The second processing gas is used to apply the first high frequency to the front or the second electrode, the plasma of the second processing gas in the foregoing, and the etching resistance before the lifting. In the processing container remote from the inner spaces 'applying member applying a predetermined DC voltage to flow in the plasma-exposed' by applying the DC component of the project it is released in the resist pattern. The brain readable plasma processing unit 2 electrode is placed in the container by the second electric air venting into the pre-processing space first electrode or the mask on the first touch panel, and the container is previously performed. Carrying out the vacuum discharge of the second electrode, the first electrode space is formed, and the resist pattern is described. The negative electron of the substrate is introduced into 200952069. The plasma processing method according to the first aspect is a processed film on the counter substrate. Before the etching process, electrons are injected into the resist pattern on the substrate by the same hard body, and the electrons are immersed in the surface portion (deep portion or deep inside) to be modified. Since the same hard body is used independently of the etching process, the processing conditions can be arbitrarily selected, and in particular, the absolute enthalpy of the negative DC voltage applied to the DC applying member can be arbitrarily selected, and the thickness of the reforming layer can be arbitrarily controlled. Preferably, the absolute enthalpy of the negative DC voltage is selected so that the electrons released by the DC application member are driven into the resist pattern by an energy of 10 〇〇〇 eV or more, preferably 1 000 V or more. This makes it possible to obtain a modified layer having a thickness of several tens of nm or more. More preferably, the absolute enthalpy of the negative DC voltage is selected by the electrons emitted from the DC application member being driven into the resist pattern at an energy of 1 500 eV or more, preferably 1500 V or more, whereby the thickness can be obtained. Modification layer above i〇〇nm. Further, in the above-described resist modification process, the first high frequency for plasma generation is applied to the first electrode at a desired power, and the second high frequency for ion introduction control is applied to the second electrode. The ion sheath on the second electrode is driven in a direction in which the electron energy of the resist pattern is lowered. Therefore, the self-biasing formed on the second electrode is as low as possible, and preferably ι ν or less. Further, the power of the second high frequency may be as low as possible, preferably at 50 W or less, more preferably 〇W' or no high frequency applied to the second electrode. In addition, in a preferred aspect of the present invention, the resist pattern is patterned and patterned in the same processing container after the above-mentioned resist modification at -8-200952069, before the uranium engraving of the processed film. The face is cut in a parallel transverse direction into a trimming process of the desired size. The trimming process is a plasma etching process including a process of evacuating a vacuum into a predetermined pressure in a processing container, and supplying a third processing gas containing an etchant gas in a processing space between the first electrode and the second electrode. Engineering: φ engineering of applying a first high frequency to the first electrode or the second electrode to generate a plasma of the third processing gas in the processing space; and etching the resist pattern to a desired pattern under the generated plasma Engineering. At this time, the resist pattern of the processing object is subjected to the resist modification treatment of the pre-engineering process to improve the etching resistance or the plasma resistance of the modified layer, so that the deformation such as the shoulder drop is less, and the desired reduction ratio can be achieved. To accept high-precision finishing. In the plasma processing method of the present invention, the DC application member is typically a first electrode that faces the substrate in a direction opposite to the substrate, but may be used as a member (for example, a container side wall) that faces the substrate obliquely or as a DC application. φ member. As the material of the first electrode, a conductive material containing Si can be suitably used. However, any material can be selected based on the process of etching the film to be processed. Further, when the first electrode is made of a conductive material containing Si, it can be used as a second processing gas for resist modification treatment, in addition to preventing deposition of a polymer on the electrode surface and maintaining conductivity of DC. A gas containing a halogen gas (for example, a fluorocarbon gas) is suitably used. In the plasma processing method according to the second aspect of the present invention, the first electrode and the second electrode are arranged in parallel with each other at a predetermined interval in the processing container of the vacuum -9-200952069, and the first electrode is opposed to the first electrode. The second electrode supports the substrate to be processed: vacuum evacuates the inside of the processing chamber to a predetermined pressure, and supplies a first processing gas containing an etchant gas to the processing space between the first electrode and the second electrode. a first high frequency is applied to the first electrode or the second electrode, and a plasma of the processing gas is generated in the processing space, and a processed film on the substrate is formed under the plasma to form a resistance on the processed film. A plasma processing method for etching a mask pattern as a mask, wherein: (1) etching the resist film in the middle of etching the substrate to the substrate in the processing container In a manner of lifting, a DC voltage applied to a predetermined DC application member exposed to the plasma in a place away from the substrate in the processing container is applied to the DC application member. The released electrons are driven into the resist pattern on the substrate; (2) in parallel with the etching of the processed film, the resist pattern is cut into a desired size in a lateral direction parallel to the pattern surface. The method is to select the gas pressure and the etching Q time in the aforementioned processing container. As described above, the plasma processing method according to the second aspect of the present invention performs the etching process on the substrate under the same plasma in the same processing container by performing the original plasma etching treatment on the processed film on the substrate. The resist pattern used in the mask is driven into electrons, and the etching resistance is enhanced according to the modification effect, and the mask selection ratio is increased, and the gas pressure and the etching time are taken as parameters, and the resist pattern is performed as desired. Trimming treatment. In the plasma processing method according to the third aspect of the present invention, the first electrode and the second electrode are arranged in parallel at a predetermined interval in a processing chamber of -10 200952069 which is vacuum, and the first electrode is opposed to the first electrode. The second electrode supports the substrate to be processed, evacuates the inside of the processing chamber to a predetermined pressure, and supplies a processing gas containing an etchant gas to the processing space between the first electrode and the second electrode, and the first electrode is applied to the first electrode. Or applying a first high frequency to the second electrode to generate a plasma of the processing gas in the processing space, and forming a film on the substrate on the substrate to form a resist on the film to be processed under the plasma. A plasma processing method for etching a pattern as a mask, characterized in that in the processing container, the etching of the resist pattern is performed in the middle of etching the processed film; The predetermined DC application member exposed to the plasma in a place away from the substrate in the processing container is applied with a DC voltage of a negative polarity, which is to be To the electrons emitted into the resist pattern on the substrate. As described above, the plasma processing method according to the third aspect of the present invention is characterized in that: Φ faces the processed film on the substrate to perform the original plasma etching treatment, and is on the substrate under the same plasma in the same processing container. The resist pattern used in the etching mask is driven into the electrons to enhance the etching resistance and improve the mask selection ratio. Further, the computer readable memory medium of the present invention is a computer memory medium in which a control program for operating on a computer is stored, wherein the control program is executed to perform the above-described plasma processing method of the present invention. The way to control the plasma processing unit. -11 - 200952069 (Effects of the Invention) The plasma processing method or the computer readable memory medium according to the present invention is simple and effective by the capacitive coupling type plasma etching apparatus by the configuration and action as described above. The resist modification method enhances the etching resistance of the resist pattern, and the precision and stability of the film processing can be improved. [Embodiment] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. 0 Fig. 1 shows the configuration of a plasma processing apparatus used in the plasma processing method of the present invention. This plasma processing apparatus is constituted by a capacitive coupling type plasma etching apparatus, and has a cylindrical chamber (processing vessel) 10 made of metal such as aluminum or stainless steel. The chamber 10 is safely grounded. In the chamber 10, a disk-shaped susceptor 1 2 on which a semiconductor wafer W as a substrate to be processed is placed is placed horizontally as a lower electrode. The base 12 is made of, for example, aluminum, and is supported by an insulating cylindrical support portion 14 extending vertically upward from the bottom of the chamber 1 。. An annular exhaust path is formed between the conductive cylindrical support portion (inner wall portion) 16 extending vertically upward from the bottom of the chamber 10 along the outer circumference of the cylindrical support portion u 14 and the side wall of the chamber 10. 18, an annular exhaust ring (baffle) 20 is attached to the inlet of the exhaust passage 18, and an exhaust port 22 is provided at the bottom of the exhaust passage 18. An exhaust device 26 is connected to the exhaust port 22 via an exhaust pipe 24. The exhaust unit 26 has a vacuum pump such as a turbol pump to depressurize the processing space in the chamber 10 to a desired degree of vacuum. A gate valve 28 for opening and closing the loading and unloading port of the semiconductor wafer W is attached to the side wall of the chamber 1A. -12- 200952069 The high frequency power source 30 is electrically connected to the susceptor 12 via the integrator 32 and the lower power supply rod 36. Here, the high frequency power source 30 outputs a high frequency LF which contributes to the introduction of ions (usually 13.5 6 MHz or less) to the semiconductor wafer W on the susceptor 12. The integrator 32 is configured to obtain a matching between the impedance on the high-frequency power source 30 side and the impedance on the side of the load (mainly the electrode, the plasma, and the chamber), and automatically adjust the matching point. ° 0 The susceptor 12 has a diameter or a diameter that is slightly larger than the semiconductor wafer W. A semiconductor wafer W to be processed is placed on the susceptor 12, and a focus ring (correction ring) 38 is provided to surround the semiconductor wafer W. An electrostatic chuck 40 for wafer adsorption is attached to the upper surface of the susceptor 12. The electrostatic chuck 40 holds a sheet-like or mesh-like DC electrode in a film-like or plate-shaped dielectric. The DC power source 42 disposed outside the chamber 10 is electrically connected to the DC electrode through the switch 44 and the high voltage power supply line 46. A DC voltage is applied to the DC electrode by the DC power source 42, whereby the semiconductor wafer W can be adsorbed and held on the electrostatic chuck 40 by Coulomb force. An annular refrigerant chamber 48 extending in the circumferential direction is provided inside the susceptor 12, for example. In the refrigerant chamber 48, a refrigerant of a predetermined temperature, for example, cooling water, is circulated and supplied by a cooler unit (not shown) via pipes 50 and 52. The temperature of the semiconductor wafer W on the electrostatic chuck 40 can be controlled by the temperature of the refrigerant. Next, in order to thermally bond the semiconductor wafer w to the susceptor 12, a heat transfer gas such as a He gas system from a heat transfer gas supply unit (not shown) passes through the gas supply pipe 54 and the gas passage 56 inside the susceptor 12 It is supplied to the contact interface of the electrostatic chuck 40 and the semiconductor wafer w. -13- 200952069 The upper surface of the chamber 1 is provided with an upper electrode 60 which serves as a shower head in parallel with the pedestal 1 2 . The upper electrode (washing head) 60 has an electrode plate 62 facing the susceptor 12; and an electrode support 64 for detachably supporting the electrode plate 62 from the back (upper) thereof, in the electrode holder 64 A gas diffusion chamber 66 is provided inside, and a plurality of gas discharge holes 68 penetrating the gas diffusion chamber 66 to the susceptor 12 side are formed in the electrode support 64 and the electrode plate 62. The space between the electrode plate 62 and the susceptor 12 becomes a plasma generating space or a processing space PS. The gas diffusion chamber 66 is connected to the processing gas supply unit 72 through the gas supply pipe 70. In the upper electrode 60, the material of the electrode plate 62 exposed to the plasma during the treatment is extremely important. In this embodiment, the electrode plate 62 has a function as a DC application member, so that the surface of the electrode can maintain direct current conductivity, and even if it is sputtered by the incidence of ions from the plasma, the process will not be performed. A material which causes adverse effects is preferable, and for example, a Si-containing conductive material such as Si or SiC or C (carbon) can be suitably used. The electrode support 64 may be composed of, for example, aluminum treated with alumite. An annular insulator 65 is inserted between the upper electrode 60 and the chamber 1A, and the upper electrode 60 is attached to the chamber 10 in an electrically floating state. The upper electrode 60 is electrically connected to the high frequency power source 74 via the integrator 76 and the upper power supply rod 78. The high-frequency power source 74 outputs high-frequency HF that contributes to the frequency of generating plasma (usually 40 MHz or more). The integrator 76 is configured to match between the impedance on the side of the high-frequency power source 74 and the impedance on the side of the load (mainly the electrode, the plasma, and the chamber), and the matching point can be automatically adjusted. -14- 200952069 The output terminal of the variable DC power supply 80 disposed outside the chamber 10 is electrically connected to the upper electrode 60 via the switch 82 and the DC power supply line 84. The variable DC power source 80 is configured to output a DC voltage VDC of, for example, -2000 to + 1 000V. The filter circuit 86 disposed in the middle of the DC power supply line 8 4 is configured to apply a DC voltage VDC from the variable DC power source 80 to the upper electrode 60 in a through-through manner, and pass through the susceptor 12 on the other hand. The high frequency of the φ processing space PS and the upper electrode 60 and entering the DC power supply line 84 flows toward the ground line and does not flow toward the variable DC power source 80 side. Further, in the chamber 10, for example, by a suitable portion facing the processing space PS, for example, the upper surface of the shutter 20 or the vicinity of the top of the conductive support member 16 or the radially outer side of the upper electrode 60, for example, by Si An annular DC grounding component (DC grounding electrode) 88 made of a conductive material such as S i C. The DC grounding component 88 is constantly grounded through the grounding wire 90. Each part in the plasma processing apparatus, for example, the exhaust unit 26, the high-frequency power sources 30 and 74, the switches 44 and 82, the processing gas supply unit 72, the variable DC power source 80, the cooling unit (not shown), and the heat transfer gas The operation of each of the supply unit (not shown) and the operation (sequence) of the entire apparatus are controlled by a control unit 1 1 〇 (Fig. 9) composed of, for example, a microcomputer. In the plasma processing apparatus, in order to perform etching processing on the semiconductor wafer W on the susceptor 12, the processing gas supply unit 72 introduces the processing gas containing the feed agent gas into the chamber 1 at a predetermined flow rate. The pressure in the chamber 10 is adjusted to a set enthalpy by the venting means 26. Further, the first high frequency HF (40 MHz or more) for plasma generation is applied to the upper electrode 60 through the integrator 76 and the upper power supply rod 78 by the high frequency ?15-200952069 power supply 74, and is also applied by the high frequency power supply 30. The second high frequency LF (13.56 MHz or less) for ion introduction control is applied to the susceptor 12 through the integrator 32 and the lower power supply rod 36. Further, the switch 44 is formed to be on, and a heat transfer gas (He gas) is sealed at a contact interface between the electrostatic chuck 40 and the semiconductor wafer W by electrostatic adsorption. The process gas system discharged from the shower head 60 is electrically padded between the two electrodes 12, 60 by high-frequency discharge, by the radicals or ions generated by the plasma, on the semiconductor wafer W. The film to be etched is etched into the desired pattern. In the plasma processing apparatus, the first high frequency HF suitable for generating a higher frequency of the plasma is applied to the upper electrode 60 by the high frequency power source 74 by 40 MHz or more (more preferably 60 MHz or more), whereby the plasma is preferably used. The dissociation state is increased in density, and high-density plasma can be formed even under relatively low pressure conditions. At the same time, a second high frequency LF of 13.56 MHz or less suitable for introducing a lower frequency of ions is applied to the susceptor 12, whereby a highly selective anisotropic etching of the film to be etched of the semiconductor wafer WQ can be performed. . However, the first high-frequency HF for plasma generation must be used regardless of the plasma process, but the second high-frequency LF for ion introduction control may not be used depending on the process. Further, in the plasma etching, by applying a DC voltage (usually in the range of -900 V to 0 V) to the upper electrode 60 from the variable DC power source 80, the plasma ignition stability, the resist selectivity, and the etching can be performed. Speed, etching uniformity, etc. are improved. -16- 200952069 In the plasma etching as described above, an etching mask for patterning a film to be processed on the surface of the semiconductor wafer w is used in advance on the film to be formed by photolithography Resist pattern. Here, in order to obtain high resolution, in order to obtain high resolution, for example, ArF excimer laser light (wavelength: 193 nm) is used for the exposure beam, and a chemical amplification resist (ArF resist) suitable for its high sensitivity is used. φ (First Embodiment) Next, a plasma processing method according to a first embodiment of the present invention will be described. In this embodiment, the resist wafer pattern is subjected to a resist modification treatment on the semiconductor wafer W to be processed in the chamber 10 before the plasma etching treatment is performed on the film to be processed as described above. With the trimming process as a pre-processing. Regarding Fig. 2, an example of the trimming treatment in the multilayer resist method will be described. In the figure, the film 100 of the uppermost layer (first layer) is a resist pattern Ar of an ArF resist, the film 102 of the second layer is B ARC (antireflection film: first film to be etched), and the film 104 of the third layer The SiN layer (the second film to be etched) which is the final mask, and the film (106) of the lowermost layer is the original (final) film to be processed, for example, the Si 2 layer (the third film to be etched). In the film formation of the SiN film 104 and the BARC 102, photolithography is used in the patterning of the photoresist 1 〇 by CVD (Chemical Vacuum Evaporation) or by spin coating (spin_on). As shown in FIG. 2(A), the trimming process is performed by cutting the resist pattern 100 formed by photolithography in a lateral direction parallel to the pattern surface, and forming it as shown in FIG. 2(B). Slightly thin processing of the desired size pattern. -17- 200952069 If the B ARC 102 and the SiN film 104 are sequentially etched by forming the thin resist pattern 100 as a mask, as shown in (C) of FIG. 2, the resist pattern is formed. The same fine pattern is formed or transferred to the SiN film 104. Thereafter, although not shown, the resist pattern 1〇〇 and the residual film of the BARC 102 are removed by ashing, and the base film (SiO 2 layer) 106 is uranium-etched using the SiN pattern 104 as a mask. In the resist process, when a resist pattern is initially formed in a desired narrow size, there is a case where the resist is deteriorated in the photolithography process (especially during development). In this case, after the photolithography, a method of narrowing the resist pattern to the intended size by the trimming process as described above is employed. This trimming process can be carried out using a plasma uranium etching apparatus for etching an original processed film. However, conventionally, the etching resistance (plasma resistance) of the ArF resist is weak. Therefore, by performing plasma etching for the trimming process, the resist pattern 100 has a shape change such as shoulder breakage, and is excessively easy to cut. The finishing accuracy of the trimming is not good. Therefore, in this embodiment, the resist modification treatment for enhancing the etching resistance of the resist pattern 100 is performed in the same credit processing apparatus (Fig. 1) before the trimming process. As shown in Fig. 3, the resist modification treatment is to inject a high-energy electron e· into the resist pattern 1 so that the resin of the ArF resist deteriorates deeply from the surface layer to the inner depth. It is carried out as a plasma treatment. That is, the predetermined processing gas is introduced into the chamber 10 by the processing gas supply unit 72 at an appropriate flow rate, and by the exhaust unit 26, the chamber 10 is -18-200952069, and the flow is .. The voltage of the sheath and the sub-electrode with the sheath is set to 値, and the high-frequency power source 74 is used to apply the high-frequency HF (40 MHz or more) for plasma generation to the upper portion through the integrator 76 and the upper power supply rod. Electrode 60. Further, if necessary, the high-frequency power source 30, the second high-frequency LF (13.56 MHz or less) for ion introduction control, and the lower power supply rod 32 are applied to the susceptor 12. Further, the opening 44 is set to be on, and the heat transfer gas is sealed at the contact interface between the semiconductor wafer W of the electrostatic chuck 40 by the electrostatic adsorption force (He gas 0. The processing gas discharged from the shower head 60) The plasma PR is generated by dissociation and ionization between the two electrodes 12 and 60 by high-frequency discharge. Here, as shown in FIG. 4, if the DC voltage 80 is used, the direct voltage Vdc is a negative voltage (for example, As described later, it is preferable that the upper electrode SHu formed between the upper electrode 60 and the plasma PR is thickened by applying an absolute 値1 000 V or more to the upper electrode 60' to the upper electrode 60'. The sheath voltage Vu is approximately equal in magnitude to the DC voltage VDC. Thereby, the ❹(+) in the plasma pR is accelerated in the electric field of the upper ion sheath SHu to impinge on the upper pole 60 (electrode plate 62) When the ion collision energy is increased, the secondary electrons e· released by the electrode plate 62 by 7 are increased. The second electron e is released from the electrode plate 62. The electric field of the upper ion SHu is accelerated toward the opposite direction of the ion and passes through the plasma pr, crossing the outside The lower ion sheath SHL is driven into the resist pattern 100 on the surface of the semiconductor wafer W on the susceptor 12 as shown in the figure at a predetermined high energy. At this time, the electrons are transmitted at an equal speed through the electric field. The electric field in the plasma PR but in the lower ion sheath SH1 is decelerated to flow a part of the electron energy of -19-200952069. Therefore, the sheath voltage Vl of the lower ion sheath SH1 formed on the susceptor 12 or The self-bias voltage is preferably as low as 100 V or less. Therefore, it is preferable to select the power of the second high-frequency LF (13.56 MHz or less) to be applied to the susceptor 12 to 50 W or less. More preferably, it is 0 W. According to the resist modification treatment method of the embodiment, the absolute enthalpy of the negative DC voltage vdc applied to the upper electrode 60 is increased as the principle of Fig. 4 is increased, and the semiconductor crystal is driven into the semiconductor crystal. The electron energy of the resist pattern on the circle W can increase the electron immersion depth in the resist pattern, and the depth of the modification can be increased. In the fifth image, the SEM photograph shows the modification of the resist in the embodiment. The effect of the modification obtained by the experiment. The main processing conditions are as follows. No. Reagent: ArF resist for acrylate substrate Resist film before treatment Thickness: 261 nm Process gas: CF4 = lOOsccm Pressure in chamber: 1 OOmTorr
高頻電力：60MHz/13MHz= 1 000/3 0W 直流電壓 VDC: 0V、-500V、-1000V、-1500V(4 種） 處理時間：6 0秒 如第5圖所示，藉由上述阻劑改質處理所得之最終改 質層的厚度係在 VDC=〇V時爲 Onm，VDC=-500V時爲 22nm，VDC = - 1 000V 時爲 83nm，VDC = - 1 500V 時爲 1 73nm。此外’初期狀態（處理前）之距離阻劑表面的改 -20- 200952069 質厚度係在VDC=0V時爲〇nm’ VDC=-500V時爲19nm， VDC=-1000V 時爲 62nm，VDC=-1500V 時爲 120nm。 如第5圖所示藉由阻劑改質處理而使阻劑膜厚（尤其 改質層）增大係基於阻劑的高分子吸收電子的能量而引起 組成變化或構造變化、交聯反應等所致。此外’之所以在 處理氣體使用氟碳化合物氣體（CF4)，係因爲重視將易 於沈積在上部電極60之電極板62的聚合物藉由氟的蝕刻 ❹ 作用予以去除而將電極面保持清淨之故。若僅考慮到上部 電極60中之離子照射及2次電子放出，亦可使用Ar等稀 有氣體或〇2、\2等氣體。 順帶一提，經將以Vdc= - 1 500V進行阻劑改質處理後 的阻劑圖案斜向切削而進行段差測定，可得第6圖所示之 測定結果，在與第5圖的SEM照片相同的深度（1 73 nm ) 確認出段差（界面）。 此外，藉由傅立葉轉換紅外光譜法（FTIR )調查阻劑 G 改質處理前後的紅外線吸收光譜，結果如第7A圖及第7B 圖所示，支持藉由阻劑改質處理（改質效果愈大）’金剛 烷基（Cw-H17)、內酯基（C4H502 )等會大幅減少，化學 反應繼續進展。 一般而言，電子被打入至阻劑時之電子能量與電子浸 入深度之間，在理論上已知以如第8圖所示之函數（曲線 圖）而呈大致正比關係。根據該理論，電子能量爲60OeV 時的浸入深度爲約30nm，電子能量爲lOOOeV時的浸入深 度爲約50nm，電子能量爲1 5 00eV時的浸入深度爲約 -21 - 200952069 1 20nm ° 此外，在第9圖中，以曲線圖顯示在對阻劑圖案打入 電子中電子停止的深度與所停止電子之比例的關係（模擬 )。根據該曲線圖，電子能量爲5 00eV時，至少浸入約 30nm(最大約50nm)，電子能量爲lOOOeV時，至少浸入 約60nm (最大約90nm )，電子能量爲1 5 00e V時，至少 浸入約110nm(最大約170nm)。 在第10圖中顯示藉由上述模擬所得之電子浸入深度 (第9圖）與上述實驗結果之改質深度（第5圖）的關係 。如圖所示，在兩者之間具有良好的符合關係。 其中，由第4圖的原理可知，在該實施形態的阻劑改 質處理中，被打入至基座12上之半導體晶圓W表面之阻 劑圖案100的電子能量係藉由上部離子鞘S Hu的護皮電壓 Vu與下部離子鞘SHl的護皮電壓VL的差分（Vu-VL)予 以界定。在此，上部護皮電壓Vu係與被施加至上部電極 6〇的負極性直流電壓VDC大致相等，下部護皮電壓VL係 與生成在基座12上的自偏壓電壓Vde大致相等。因此， 若基座12上的自偏壓電壓Vde爲例如100V，若欲將阻劑 圖案中的改質深度確實地形成爲60nm以上時，係將負極 性直流電壓VDC的絕對値設定爲1 100V以上即可，若欲將 改質深度確實地形成爲11 Onrn以上時，係將負極性直流電 壓VDC的絕對値設定爲1600V以上即可。 若對基座12未施加離子引入控制用的第2高頻LF時 ’自偏壓電壓Vde係小至與負極性直流電壓VDC相比爲可 -22- 200952069 忽略的程度，若將其視爲0 V，若欲將例如改質深度確實 地形成爲1 1 Onm以上時，則將負極性直流電壓VDC的絕對 値設定爲1 500V以上即可。 在第11圖中，在該實施形態中，將對半導體晶圓w 上的阻劑圖案施行如上所述的阻劑改質處理之後，再進行 修整處理時的結果（圖案剖面形狀）與比較例作對比而以 S EM照片作顯示。該修整處理中的主要處理條件係如下所 ❹ 示。 處理氣體=N2/〇2 = 100/2 0sccm 腔室內的壓力：1 OmTorrHigh-frequency power: 60MHz/13MHz= 1 000/3 0W DC voltage VDC: 0V, -500V, -1000V, -1500V (4 types) Processing time: 60 seconds As shown in Figure 5, change with the above resist The thickness of the final modified layer obtained by the quality treatment is Onm at VDC=〇V, 22 nm at VDC=-500V, 83 nm at VDC=-1 000V, and 173 nm at VDC=-1 500V. In addition, the initial surface (before treatment) distance resist surface change -20- 200952069 The thickness is nmnm' VDC=-500V is 19nm, VDC=-1000V is 62nm, VDC=- 120nm at 1500V. As shown in Fig. 5, the resist film thickness (especially the modified layer) is increased by the resist modification treatment to cause composition change or structural change, cross-linking reaction, etc. due to the energy of the electrons absorbed by the resist-based polymer. Caused. Further, the reason why the fluorocarbon gas (CF4) is used in the treatment gas is to remove the polymer which is easily deposited on the electrode plate 62 of the upper electrode 60 by the etching action of fluorine to keep the electrode surface clean. . If only the ion irradiation in the upper electrode 60 and the secondary electron emission are considered, a rare gas such as Ar or a gas such as 〇2 or \2 may be used. Incidentally, the stepwise measurement is performed by obliquely cutting the resist pattern after the resist modification treatment with Vdc = -1 500 V, and the measurement results shown in Fig. 6 can be obtained, and the SEM photographs in Fig. 5 are obtained. The same depth (1 73 nm) confirms the step (interface). In addition, the infrared absorption spectrum of the resist G before and after the modification treatment was investigated by Fourier transform infrared spectroscopy (FTIR). The results are shown in Fig. 7A and Fig. 7B, which support the modification by the resist (the effect of the modification is more Large) 'Adamantyl (Cw-H17), lactone group (C4H502), etc. will be greatly reduced, and the chemical reaction will continue to progress. In general, the electron energy and the electron immersion depth when electrons are driven into the resist are theoretically known to have a substantially proportional relationship with a function (curve) as shown in Fig. 8. According to this theory, the immersion depth when the electron energy is 60 OeV is about 30 nm, the immersion depth when the electron energy is 1000 eV is about 50 nm, and the immersion depth when the electron energy is 1 500 00 eV is about -21 to 200952069 1 20 nm ° In Fig. 9, the relationship (simulation) of the depth at which electrons are stopped in the electrons entering the resist pattern and the ratio of the stopped electrons is shown in a graph. According to the graph, when the electron energy is 500 eV, at least about 30 nm (up to about 50 nm) is immersed, and when the electron energy is 1000 eV, at least about 60 nm (up to about 90 nm) is immersed, and when the electron energy is 1 500 00 V, at least about immersed. 110 nm (up to approximately 170 nm). Fig. 10 shows the relationship between the electron immersion depth (Fig. 9) obtained by the above simulation and the modified depth (Fig. 5) of the above experimental results. As shown, there is a good relationship between the two. It can be seen from the principle of FIG. 4 that in the resist modification process of the embodiment, the electron energy of the resist pattern 100 that is driven onto the surface of the semiconductor wafer W on the susceptor 12 is supported by the upper ion sheath. The difference (Vu-VL) between the sheath voltage Vu of S Hu and the sheath voltage VL of the lower ion sheath SH1 is defined. Here, the upper sheath voltage Vu is substantially equal to the negative DC voltage VDC applied to the upper electrode 6A, and the lower sheath voltage VL is substantially equal to the self-bias voltage Vde generated on the susceptor 12. Therefore, if the self-bias voltage Vde on the susceptor 12 is, for example, 100 V, if the modified depth in the resist pattern is to be formed to be 60 nm or more, the absolute 値 of the negative DC voltage VDC is set to be 1 100 V or more. In order to accurately form the modified depth to 11 Onrn or more, the absolute 値 of the negative DC voltage VDC can be set to 1600V or more. When the second high frequency LF for ion introduction control is not applied to the susceptor 12, the self-bias voltage Vde is as small as the negative DC voltage VDC is -22-200952069, if it is regarded as 0 V. If it is desired to form the modified depth to be 1 1 Onm or more, the absolute value of the negative DC voltage VDC may be set to 1 500 V or more. In the eleventh embodiment, in the embodiment, the resist pattern on the semiconductor wafer w is subjected to the above-described resist modification treatment, and then the result of the trimming process (pattern cross-sectional shape) and a comparative example are compared. For comparison, use S EM photos for display. The main processing conditions in this trimming process are as follows. Process gas = N2 / 〇 2 = 100 / 2 0sccm Pressure in the chamber: 1 OmTorr
高頻電力：60MHz/l 3MHz = 1 OOO/OW 處理時間：17秒 如第1 1圖的（B)所示，如上所述之未進行阻劑改質處 理而已進行修整處理時（比較例），可知阻劑圖案會一面 發生肩部破壞的形狀變化，一面相較於目的尺寸（內側以 © 虛線所示之輪廓）更爲被過度切削。 相對於此，若以直流電壓VDC = - 1 5 0 0V進行上述阻劑 改質處理之後，再以上述條件進行修整處理時，如第 Π 圖的（D)所示，可知阻劑圖案的形狀變化較少，而且被施 行接近於目的尺寸的修整成形。亦即，可知以在用以修整 成形的電漿蝕刻中阻劑圖案不會引起肩部破壞的程度，該 蝕刻耐性或電漿耐性即已充分。 不過，若以直流電壓Vdc = -0V進行上述阻劑改質處 理之後，再以上述條件進行修整處理（參考例），如第11 -23- 200952069 圖的（C)所示，會出現比未進行上述阻劑改質處理時更爲 不佳的結果。亦即’在直流電壓Vdc=-〇V時的上述阻劑 改質處理中，由於幾乎無法在半導體晶圓w上的阻劑圖 案打入電子，因此不僅未形成改質層’而且由於在處理氣 體使用氟碳化合物氣體（CF4 )，因而以氟的自由基使阻 劑圖案以等向被切削而縮小圖案尺寸。 在該實施形態中，亦已進行第2圖的（C)中對SiN膜 1 0 4的蝕刻加工的實驗。主要的蝕刻條件係如下所示。 處理氣體=CF4/CHF3/Ar/02/= 225/1 25/600/60sccm 腔室內的壓力：75mTorr 溫度：上部電極/腔室側壁/下部電極= 60/60/30°C 高頻電力：40MHz/13MHz= 1 00/1 000W 直流電壓VDC: -300V 處理時間：3 0秒 以實驗結果而言，上述SiN蝕刻結束後，將半導體晶 圓W上的殘餘阻劑圖案藉由灰化予以剝離（去除），結 果可得第12A圖所示之SiN膜圖案（SEM照片）。該SiN 膜圖案的LWR的最大値爲7.7，平均値爲5.9。 在第1 2B圖中，作爲比較例，顯示未進行實施形態的 阻劑改質處理而進行上述SiN膜之蝕刻加工所得的SiN膜 圖案（平面照片）。該SiN膜圖案的LWR的最大値爲9.2 ，平均値爲6.9。 如上所示，可確認出藉由該實施形態之電漿處理方法 ，可在多層阻劑法中有效減低作爲最終遮罩之SiN圖案的 -24- 200952069 LWR。 上述之第1實施形態係具有可將施加至上部電程 的直流電壓vDC的最適値區分成阻劑改質處理用與原 刻用而獨立選定的優點。 在本發明之電漿處理方法中所使用的電容耦合型 處理裝置’並非限定爲如第1圖所示對上部電極60 電漿生成用的第1高頻HF，且對基座（下部電極）1 © 加離子引入控制用的第2高頻RF的上下部雙頻施加 ’亦可爲例如對基座（下部電極）12重疊施加第1 HF與第2高頻RF的下部雙頻重疊施加方式、或僅對 電極或下部電極施加第1高頻HF的單頻施加方式等。 在第13圖中顯示採用下部雙頻重疊施加方式的 親合型電漿處理裝置的構成例。圖中，對於具有與第 之電漿處理裝置爲相同之構成或功能的零件或構成要 標註相同的元件符號。 ❹ (第2實施形態） 以下說明之本發明之第2實施形態係將阻劑改質 在進行主蝕刻加工的同時，亦即在主蝕刻加工進行途 併進行阻劑改質處理，以強化阻劑圖案的蝕刻耐性而 遮罩選擇比。 以該實施形態之一實驗例而言，在如上所述之多 劑法（第2圖）中，在BARC 102的蝕刻的同時’對 圖案12進行阻劑改質處理（第1工程）’接著實施 I 6 0 本蝕 電漿 施加 2施 方式 高頻 上部 電容 1圖 素係High-frequency power: 60MHz/l 3MHz = 1 OOO/OW Processing time: 17 seconds As shown in (B) of Fig. 1, as described above, when the resist modification process has not been performed and the trimming process has been performed (Comparative Example) It can be seen that the resist pattern has a shape change of shoulder damage on one side, and is more excessively cut than the target size (the inner side is indicated by a dotted line in ©). On the other hand, when the above-described resist modification treatment is performed after the DC voltage VDC = -1 5 0 0 V, and the trimming treatment is performed under the above conditions, the shape of the resist pattern is known as shown in (D) of the first drawing. The change is less, and trimming is performed close to the size of the target. That is, it is understood that the etching resistance or the plasma resistance is sufficient to the extent that the resist pattern does not cause shoulder damage in the plasma etching for trimming. However, if the above-mentioned resist modification process is performed with the DC voltage Vdc = -0V, the trimming process is performed under the above conditions (reference example), as shown in (C) of the 11th-23-200952069 figure, A more unsatisfactory result when the above-mentioned resist modification treatment is carried out. That is, in the above-described resist modification process at the DC voltage Vdc=-〇V, since it is almost impossible to insert electrons into the resist pattern on the semiconductor wafer w, not only the modified layer is not formed but also due to processing Since the gas uses the fluorocarbon gas (CF4), the resist pattern is cut in the same direction by the radical of fluorine to reduce the pattern size. In this embodiment, an experiment of etching the SiN film 104 in the second drawing (C) has also been carried out. The main etching conditions are as follows. Process gas=CF4/CHF3/Ar/02/= 225/1 25/600/60sccm Pressure in chamber: 75mTorr Temperature: upper electrode/chamber side wall/lower electrode = 60/60/30°C High frequency power: 40MHz /13MHz= 1 00/1 000W DC voltage VDC: -300V Processing time: 30 seconds According to the experimental results, after the SiN etching is completed, the residual resist pattern on the semiconductor wafer W is peeled off by ashing ( Removal), as a result, the SiN film pattern (SEM photograph) shown in Fig. 12A was obtained. The SiN film pattern had an LWR with a maximum 値 of 7.7 and an average 値 of 5.9. In the first embodiment, a SiN film pattern (planar photograph) obtained by etching the SiN film without performing the resist modification treatment of the embodiment is shown as a comparative example. The LN of the SiN film pattern had a maximum 値 of 9.2 and an average 値 of 6.9. As described above, it was confirmed that the plasma treatment method of this embodiment can effectively reduce the -24-200952069 LWR which is the SiN pattern of the final mask in the multilayer resist method. In the first embodiment described above, it is advantageous in that the optimum value of the DC voltage vDC applied to the upper path can be independently selected for the resist reforming process and for the original use. The capacitive coupling type processing apparatus used in the plasma processing method of the present invention is not limited to the first high frequency HF for plasma generation of the upper electrode 60 as shown in Fig. 1, and the susceptor (lower electrode) 1 © Upper and lower dual-frequency application of the second high-frequency RF for ion introduction control' may be, for example, a lower dual-frequency overlapping application method in which the first HF and the second high-frequency RF are superimposed on the susceptor (lower electrode) 12 Or a single-frequency application method in which the first high-frequency HF is applied to the electrode or the lower electrode. Fig. 13 shows a configuration example of an affinity plasma processing apparatus employing a lower dual-frequency overlapping application method. In the drawings, the same components or components as those having the same configuration or function as those of the first plasma processing apparatus are denoted by the same reference numerals.第 (Second Embodiment) In the second embodiment of the present invention described below, the resist is modified to perform the main etching process, that is, the main etching process is performed, and the resist modification process is performed to enhance the resistance. The etching resistance of the agent pattern is masked to the selection ratio. According to an experimental example of the embodiment, in the multi-dose method (Fig. 2) described above, the resist 12 is subjected to a resist modification treatment (first project) while etching the BARC 102. Implementation I 6 0 This etched plasma is applied by 2 modes of high frequency upper capacitance 1 pixel system
處理 中一 提升 層阻 阻劑 SiN -25- 200952069 膜104的蝕刻（第2工程），量測出SiN蝕刻中的遮罩選 擇比。在該實驗中係使用下部雙頻重疊施加方式的電漿處 理裝置（第13圖）。 第1工程（BARC飩刻/阻劑改質處理）中之主要條件 係如下所示。 阻劑：丙烯酸酯基質用的ArF阻劑 BARC :有機膜 處理氣體：C F 4 / 〇 2 = 2 5 0 / 1 3 s c c m 腔室內的壓力：30mTorr 溫度：上部電極/腔室側壁/下部電極= 60/60/30°C 高頻電力：40MHz/13MHz= 400/0W 直流電壓 VDC : 0V、-500V、-1000V、-1500V、-1800V ( 5 種） 處理時間：2 0秒 第2工程（SiN蝕刻）中之主要條件係如下所示。 處理氣體=CF4/CHF3/Ar/02= 225/ 1 25/600/60sccin 腔室內的壓力：75mT〇rr 溫度：上部電極/腔室側壁/下部電極= 60/60/3 0t 高頻電力：40MHz/13MHz= 1 00/1 000W 直流電壓VDC : -3 00V 處理時間：3 0秒 在第1 4圖中’以S E Μ照片顯示以上述實驗所得的圖 案剖面形狀。在上述實驗中’將在第1工程（B ARC触刻/ 阻劑改質處理）中被施加至上部電極6 0的直流電壓v D c 作爲參數’將V d c = 〇 V的情形（A)作爲比較基準（標準： 200952069 STD )。圖中，虛線的線La、Lc係分別表示比較基準（ S TD )中之第1工程結束後之阻劑圖案1 〇 〇之頂部的位準 及基底膜（SiN膜）104之上面的位準。虛線的線Lb係表 示第1工程前之BARC 1 02之上面的位準。此外，虛線的 線Ld、Le係分別表示比較基準（STD )中之第2工程結束 後之阻劑圖案100之頂部的位準及BARC 102與SiN膜104 之界面的位準。Processing One Lifting Layer Resistor SiN -25- 200952069 The etching of the film 104 (second work) measures the mask selection ratio in the SiN etching. In this experiment, a plasma processing apparatus of a lower dual-frequency overlap application method (Fig. 13) was used. The main conditions in the first project (BARC engraving / resist modification treatment) are as follows. Resistor: ArF resist for acrylate substrate BARC : Organic film treatment gas: CF 4 / 〇 2 = 2 5 0 / 1 3 sccm Pressure inside chamber: 30 mTorr Temperature: upper electrode / chamber side wall / lower electrode = 60 /60/30°C High-frequency power: 40MHz/13MHz= 400/0W DC voltage VDC: 0V, -500V, -1000V, -1500V, -1800V (5 types) Processing time: 20 seconds Second project (SiN etching The main conditions in the system are as follows. Process gas=CF4/CHF3/Ar/02= 225/ 1 25/600/60sccin Pressure in chamber: 75mT〇rr Temperature: upper electrode/chamber side wall/lower electrode = 60/60/3 0t High frequency power: 40MHz /13MHz= 1 00/1 000W DC voltage VDC : -3 00V Processing time: 30 seconds In Figure 14 , the pattern cross-sectional shape obtained by the above experiment is shown by SE Μ photo. In the above experiment, the DC voltage v D c applied to the upper electrode 60 in the first project (B ARC etch/resist modifier) was taken as the parameter 'V dc = 〇V (A) As a benchmark (standard: 200952069 STD). In the figure, the dotted lines La and Lc respectively indicate the level of the top of the resist pattern 1 后 after the end of the first project in the comparison reference (S TD ) and the level above the base film (SiN film) 104. . The dotted line Lb indicates the level above the BARC 102 before the first project. Further, the broken lines Ld and Le respectively indicate the level of the top of the resist pattern 100 after the completion of the second project in the comparison reference (STD) and the level of the interface between the BARC 102 and the SiN film 104.
〇 第2工程（SiN蝕刻）中的遮罩選擇比係在VDC二0V 時爲 2.11，VDC=-500V 時爲 1.95，VDC=-1000V 時爲 1.89，VDC=-1500V 時爲 2.51，VDC=-1800V 時爲 3.01。 亦即，確認出VDc的絕對値爲1 500V以上（電子能量爲 1 5 00eV以上），遮罩選擇比顯著提升，VDC的絕對値愈大 ，遮罩選擇比愈高。 此外，如第14圖所示，可知在VDC=-500V〜-1800V ，係由阻劑圖案1 0 0的表層至內部深處形成有阻劑改質層 〇 107，可在圖案剖面形狀（SEM照片）中視認出改質層 107與非改質層1〇8的界面109，Vdc的絕對値愈大，改 質層107的厚度（尤其縱方向的厚度）愈會增加。 第1 5圖係藉由畫像處理（2値化處理）’更加明確表 示阻劑圖案12中之改質層107與非改質層108者。 在第1 6圖中，以實驗結果而言’以SEM照片顯示上 述第1工程結束後的阻劑圖案〔ARC〕、上述第2工程結 束後的阻劑圖案〔SiN〕、灰化結束後的SiN圖案〔Ash〕 。如圖所示’在任何階段中’均可視認' 出當將V D c的絕對 -27- 200952069 値形成爲1 5 00以上時，圖案側壁的凹凸變形會顯著變少 〇 順帶一提，作爲最終遮罩的SiN圖案〔Ash〕的LWR 係在3σ的平均値，VDC=0V時爲9.1 ’ VDC=-500V時爲 12.1，VDC=-1000V 時爲 13.1，VDC=-1500V 時爲 9.4’The mask selection ratio in the second project (SiN etching) is 2.11 at VDC 2V, 1.95 at VDC=-500V, 1.89 at VDC=-1000V, and 2.51 at VDC=-1500V, VDC=- It is 3.01 at 1800V. That is, it is confirmed that the absolute enthalpy of VDc is 1 500 V or more (electron energy is 1 500 00 eV or more), the mask selection ratio is remarkably improved, the absolute maximum VDC is increased, and the mask selection ratio is higher. Further, as shown in Fig. 14, it can be seen that in the VDC = -500 V to -1800 V, a resist reforming layer 〇 107 is formed from the surface layer of the resist pattern 100 to the inside, and the pattern cross-sectional shape (SEM) can be obtained. In the photo), the interface 109 of the modified layer 107 and the non-modified layer 1〇8 is recognized, and the absolute maximum Vdc is increased, and the thickness of the modified layer 107 (especially the thickness in the longitudinal direction) is increased. Fig. 15 shows the modified layer 107 and the non-modified layer 108 in the resist pattern 12 more clearly by the image processing (2 値 process). In Fig. 16, the results of the experiment show that the resist pattern (ARC) after the end of the first project, the resist pattern [SiN] after the completion of the second project, and the ashing are completed by SEM photographs. SiN pattern [Ash]. As shown in the figure, 'is visible at any stage'. When the absolute -27-200952069 V of VD c is formed to be more than 1 500, the unevenness of the sidewall of the pattern will be significantly reduced, and by the way, as a final The LWR of the SiN pattern [Ash] of the mask is at an average 値 of 3σ, 9.1 ' at VDC=0V, 12.1 at VDC=-500V, 13.1 at VDC=-1000V, and 9.4' at VDC=-1500V.
Vdc = -1800V 時爲 8.3。 (第3實施形態） 0 接著，本發明之第3實施形態係將阻劑改質處理及修 整處理在進行主蝕刻加工的同時，亦即在主蝕刻加工進行 途中，不僅阻劑改質處理，亦一倂進行修整處理，以達成 工程數刪減，亦即處理效率提升。 在該實施形態中，以一實驗例而言，在如上所述之多 層阻劑法（第2圖）中，在與B ARC 1 02的蝕刻的同時， 對阻劑圖案1 〇 〇進行阻劑改質處理與修整處理（第1工程 )’接著實施SiN膜104的蝕刻（第2工程），在修整後 ◎ 量測阻劑圖案1 〇〇的線寬尺寸，而量測出SiN蝕刻中的遮 罩選擇比。在該實驗中係使用下部雙頻重疊施加方式的電 漿蝕刻裝置（第13圖）。 第1工程（BARC蝕刻/阻劑改質處理/修整處理）中 之主要條件係如下所示。 阻劑：丙烯酸酯基質用的ArF阻劑 BARC :有機膜 處理氣體=CF4/〇2 = 250/13sccm -28- 200952069 腔室內的壓力：30mTorr、100mTorr(2種） 溫度：上部電極/腔室側壁/下部電極= 60/60/30°C 高頻電力：40MHz/13MHz= 400/0W 直流電壓 Vdc: 〇V、-1800V(2 種） 處理時間：20秒、47秒（2種） 第2工程（SiN蝕刻）中之主要條件係如下所示。 處理氣體=CF4/CHF3/Ar/〇2 = 225/125/600/60sccm 〇 腔室內的壓力：75mTorr 溫度：上部電極/腔室側壁/下部電極= 60/60/3 0°C 高頻電力：60MHz/13MHz= 1 00/1000W 直流電壓VDC : -300V 處理時間：3 0秒 在第17圖中，以SEM照片顯示在上述實驗中所得之 圖案剖面形狀。在上述實驗中，將在第1工程（BARC蝕 刻/阻劑改質處理/修整處理）中被施加至上部電極60的直 © 流電壓Vdc、氣體壓力、處理時間設爲參數’將VDC= 0V 、氣體歴力=30mTorr、處理時間=20秒的情形（a)設爲主 比較基準（STD)，將VDC=-1800V、氣體壓力= 30mTorr 、處理時間=20秒的情形（b)設爲準比較基準（STD’ ) 〇 圖中虛線的線La、Le係分別表示主比較基準（STD ) 中之第1工程結束後之阻劑圖案1 2之頂部的位準及基底 膜（SiN層）1〇4之上面的位準。虛線的線Lb係表示第1 工程前之BARC102之上面的位準。此外，虛線的線Ld、 -29- 200952069When Vdc = -1800V, it is 8.3. (Third Embodiment) Next, in the third embodiment of the present invention, the resist modification treatment and the trimming treatment are performed not only on the middle of the main etching process but also in the middle of the main etching process, that is, the resist modification process and the trimming process. The finishing process is also carried out to achieve the reduction of the number of works, that is, the efficiency of the treatment. In this embodiment, in an experimental example, in the multilayer resist method (Fig. 2) as described above, the resist pattern 1 is resisted while being etched with B ARC 102. The reforming process and the trimming process (first project) are followed by etching of the SiN film 104 (second work), and after trimming, measuring the line width dimension of the resist pattern 1 ,, and measuring the SiN etching Mask selection ratio. In this experiment, a plasma etching apparatus using a lower dual-frequency overlap application method (Fig. 13) was used. The main conditions in the first project (BARC etching/resist modifier modification/trimming treatment) are as follows. Resist: ArF Resistor for Acrylate Matrix BARC : Organic Membrane Treatment Gas = CF4 / 〇 2 = 250 / 13 sccm -28 - 200952069 Pressure in chamber: 30 mTorr, 100 mTorr (2 types) Temperature: Upper electrode / chamber sidewall / Lower electrode = 60/60/30°C High-frequency power: 40MHz/13MHz= 400/0W DC voltage Vdc: 〇V, -1800V (2 types) Processing time: 20 seconds, 47 seconds (2 types) 2nd project The main conditions in (SiN etching) are as follows. Process gas=CF4/CHF3/Ar/〇2 = 225/125/600/60sccm Pressure in the chamber: 75mTorr Temperature: upper electrode/chamber side wall/lower electrode = 60/60/3 0°C High frequency power: 60 MHz / 13 MHz = 1 00 / 1000 W DC voltage VDC : -300 V Processing time: 30 seconds In Fig. 17, the cross-sectional shape of the pattern obtained in the above experiment is shown by SEM photograph. In the above experiment, the direct current-flow voltage Vdc, the gas pressure, and the processing time applied to the upper electrode 60 in the first work (BARC etching/resistor reforming/dressing process) were set as the parameter 'will be VDC=0V. In the case where the gas pressure = 30 mTorr and the processing time = 20 seconds (a) is set as the main comparison reference (STD), and the case (b) in which VDC = -1800 V, gas pressure = 30 mTorr, and processing time = 20 seconds is set as Comparison Standard (STD') The lines La and Le of the broken lines in the diagram indicate the level of the top of the resist pattern 1 2 and the base film (SiN layer) 1 after the end of the first project in the main comparison reference (STD). The level above 〇4. The dotted line Lb indicates the level above the BARC 102 before the first project. In addition, the dotted line Ld, -29- 200952069
Le係分別表示主比較基準（STD )中之第2工程結束後之 阻劑圖案100之頂部的位準及BARC102與SiN膜104之 界面的位準。 如第1 7圖之上段所示，阻劑圖案1 〇0的寬幅尺寸在 初期狀態下爲131nm，在第1工程結束後’若爲條件（a)’ 即縮小爲1 23nm，若爲條件（b)，即縮小爲1 1 8nm ’若爲條 件（c)，亦即VDC=-1800V、氣體壓力=l〇〇mTorr、處理時 間=2 0秒，即縮小爲9 9 n m，若爲條件（d) ’亦即V D c = - ◎ 1800V、氣體壓力= 100mTorr、處理時間=47秒’即縮小 爲 8 3 n m 〇 如上所示，在第1工程中，藉由提高氣體壓力、加長 處理時間，可知不僅修整量顯著增大’而且藉此使得縱方 向損失尤其增加，而且獲得肩部掉落較少之良好的圖案剖 面形狀。 在此，藉由提高氣體壓力，而使阻劑圖案100的修整 量增大係基於氟自由基增加而使橫方向的自由基鈾刻增速 〇 之故，若處理時間長’則橫方向的蝕刻量會與時間成正比 增加。 此外，在阻劑圖案1 00中’之所以即使橫方向的切削 量增加，縱方向的切削量亦未增加’係基於縱方向與橫方 向在改質程度會有所不同之故。亦即，藉由本發明之阻劑 改質處理，高能量的電子大致垂直地被打入至半導體晶圓 W表面的阻劑圖案100’並且離子亦大致垂直地被打入的 效果亦相乘，相較於橫方向’阻劑圖案1 00以縱方向更爲 -30- 200952069 強固地進行改質之故，而且隨著時間經過，改質程度會更 加加強之故。不過，阻劑圖案100的周緣部（邊緣）由於 離子集中，因此易於切削，結果會以縱方向形成爲與側壁 大致爲相同平面。 其中，在第1工程中，僅對基座（下部電極）12施加 電漿生成用的第1高頻HF，並未施加離子引入控制用的 第2高頻LF，但是會發生根據第1高頻HF的施加的自偏 〇 壓，電漿中的正離子會藉由離子鞘的電場而被拉入至半導 體晶圓W，而入射至阻劑圖案1 00。 第2工程中的遮罩選擇比係如第1 7圖之下段所示， 爲條件（a)時爲2.1 1，爲條件（b)時爲3.01，爲條件（c)時爲 3.09，爲條件（d)時爲3·45。由該結果可知VDC條件（絕對 値爲1 500V以上）爲用以提升遮罩選擇比之主要要件，亦 即用以提高阻劑圖案1 〇〇之蝕刻耐性的支配性要件。此外 ，可知第1工程的處理時間愈長，遮罩選擇比愈會提升， 〇 亦即阻劑圖案1 〇〇的蝕刻耐性會變得更爲強固。 在第18圖中，以該實施形態中之實驗結果而言，以 SEM照片顯示上述第1工程結束後的阻劑圖案〔ARC〕、 上述第2工程結束後的阻劑圖案〔SiN〕、灰化結束後的 SiN圖案〔Ash〕。如圖所示，在條件（b)(c)(d)之間，在任 何階段中均可視認出第1工程中的壓力愈高、處理時間愈 長，則愈提升圖案側壁的平坦性。 順帶一提，作爲最終遮罩之SiN圖案〔Ash〕的LWR ，以3 σ的平均値，條件（a)時爲9.1、條件（b)時爲8.3、 -31 - 200952069 條件（C)時爲8.1、條件（d)時爲7.1。 在第19圖顯示爲了進行上述實施形態中之電漿處理 方法，將上述電漿處理裝置（第1圖、第13圖）之各部 的控制及全體的順序進行控制的控制部1 1 〇的構成例。 該構成例的控制部1 1 〇係具有：透過匯流排1 50而相 連接的處理器（CPU ) 152、記憶體（RAM ) 154、程式儲 放裝置（HDD) 156、軟碟機或光碟等磁碟驅動器（DRV )158、鍵盤或滑鼠等輸入元件（KEY) 160、顯示裝置（ DIS) 162、網路.介面（COM) 164、及周邊介面（I/F) 166° 處理器（CPU ) 152係可由被裝設在磁碟驅動器（ DRV) 158的FD或光碟等記億媒體168讀取所需的程式 碼，且儲放在HDD 156。或者亦可由網路透過網路•介面 164來下載所需程式。接著，處理器（CPU) 152係將各 階段或各場面所需之程式碼由HDD156在工作記憶體（ RAM) 154上展開而執行各步驟，進行所需之運算處理， 透過周邊介面166來控制裝置內的各部（尤其排氣裝置26 、高頻電源30、74、處理氣體供給部72、可變直流電源 80、開關82等）。用以實施上述實施形態中所說明之電 漿處理方法的程式均以該電腦系統予以執行。 在上述之實施形態中，係將上部電極6 0利用在D C施 加構件，但是在本發明中， 在腔室內以與基座呈鉛直的方向或斜向的方向相對向 而將曝露在電漿的任意導電構件使用在DC施加構件或兼 200952069 用作D C施加構件，亦可在上部電極6 0以外，將例如腔室 側壁等利用在DC施加構件。施加至DC施加構件的直流 電壓並非必須始終保持在一定電壓位準，亦可將例如低頻 的交流電壓相重疊。 本發明中的被處理基板並非侷限於半導體晶圓，亦可 爲平面顯示器用的各種基板或、光罩、CD基板、印刷基 板等。此外，本發明尤其適當地適用於使用ArF阻劑的電 〇 漿蝕刻加工，但是亦可適用於使用其他阻劑之電漿蝕刻加 工等電漿處理或微細加工。 【圖式簡單說明】 第1圖係顯示在本發明之電漿處理方法所使用之電漿 處理裝置之構成的縱剖面圖。 第2圖係以模式顯示進行修整處理時之加工順序的剖 面圖。 Ο 第3圖係用以以模式說明將電子打入至半導體晶圓上 之阻劑圖案之阻劑改質處理之作用的剖面圖。 第4圖係用以以模式說明將電子打入至半導體晶圓上 之阻劑圖案之阻劑改質處理之原理的側面圖。 第5圖係以SEM照片顯示在第1實施形態中之阻劑 改質處理之實驗所得之改質效果的示意圖。 第6圖係利用斜向切削的段差測定而確認出第1實施 形態中以阻劑改質處理的實驗所得之改質效果的圖。 第7A圖係利用傅立葉轉換紅外光譜法（FTIR )而確 -33- 200952069 認出第1實施形態中以阻劑改質處理的實驗所得之改質效 果的圖。 第7 B圖係利用傅立葉轉換紅外光譜法（F ΤIR )而確 認出第1實施形態中以阻劑改質處理的實驗所得之改質效 果的圖。 第8圖係以曲線圖顯示電子被打入至阻劑時的電子能 量與電子浸入深度之理論上關係的圖。 第9圖係針對在對阻劑圖案打入電子中電子停止的深 度與所停止電子之比例的關係，以曲線圖顯示藉由模擬所 求出之結果的圖。 第10圖係顯示上述模擬與上述實驗結果的符合關係 圖。 第1 1圖係將第1實施形態中在阻劑改質處理後已進 行修整處理時之圖案剖面形狀與比較例作對比而以SEM 照片所顯示的圖。 第1 2 A圖係將第1實施形態中在阻劑改質處理後已進 行SiN膜之蝕刻時之圖案平面形狀以SEM照片所顯示的 圖。 第1 2B圖係將在第1實施形態中未進行阻劑改質處理 而已進行SiN膜之蝕刻時（比較例）之圖案平面形狀以 SEM照片所顯示的圖。 第13圖係顯示在本發明之電漿處理方法所使用之電 漿處理裝置之其他構成的縱剖面圖。 第14圖係以SEM照片顯示第2實施形態中以實驗所 200952069 得之各工程結束後之圖案剖面形狀的示意圖。 第15圖係藉由畫像處理將第14圖之圖案剖面形狀（ SEM照片）中之改質層與非改質層2値化而清楚表示的圖 〇 第1 6圖係以s EM照片顯示第2實施形態中各階段之 圖案之平面形狀的示意圖。 第1 7圖係以SEM照片顯示第3實施形態中以實驗所 〇 得之各工程結束後之圖案剖面形狀的示意圖。 第18圖係以SEM照片顯示第3實施形態中各階段之 圖案之平面形狀的示意圖。 第1 9圖係顯示實施形態中之控制部之構成例的方塊 圖。 【主要元件符號說明】 1 〇 :腔室（處理容器） Φ 12:基座（下部電極） 1 4 :筒狀支持部 16:導電性筒狀支持部（內壁部） 1 8 :排氣路 20 :排氣環 22 :排氣口 24 :排氣管 26 :排氣裝置 28 :閘閥 -35- 200952069 30:離子引入用的局頻電源 32 :整合器 3 6 :下部供電棒 38 :聚焦環（補正環） 40 :靜電吸盤 4 2 :直流電源 44 :開關 4 6 :高壓供電線 4 8 :冷媒室 5 0、5 2 :配管 5 4 :氣體供給管 6 0 :上部電極 6 2 :電極板 64 :電極支持體 6 5 :絶緣體 6 6 :氣體擴散室 6 8 :氣體排出孔 70 :氣體供給管 72 :處理氣體供給部 74:電漿生成用的高頻電源 76 :整合器 7 8 :上部供電棒 8 0 :可變直流電源 8 2 :開關 -36- 200952069 8 4 :直流供電線 86 :濾波器電路 8 8 : DC接地零件（直流接地電極）The Le system indicates the level of the top of the resist pattern 100 after the completion of the second project in the main comparison standard (STD) and the level of the interface between the BARC 102 and the SiN film 104, respectively. As shown in the upper part of Fig. 17, the wide dimension of the resist pattern 1 〇0 is 131 nm in the initial state, and after the first project is completed, it is reduced to 1 23 nm if the condition (a) is satisfied. (b), that is, reduced to 1 18 nm 'if condition (c), that is, VDC = -1800 V, gas pressure = l 〇〇 mTorr, processing time = 20 seconds, that is, reduced to 9 9 nm, if the condition (d) 'VD c = - ◎ 1800V, gas pressure = 100mTorr, processing time = 47 seconds' is reduced to 8 3 nm 〇 As shown above, in the first project, by increasing the gas pressure and lengthening the processing time It can be seen that not only is the trimming amount significantly increased, but also the longitudinal loss is particularly increased, and a good pattern cross-sectional shape with less shoulder drop is obtained. Here, by increasing the gas pressure, the trimming amount of the resist pattern 100 is increased based on the increase in the fluorine radicals to increase the velocity of the radical uranium in the transverse direction, and if the processing time is long, the lateral direction is The amount of etching increases in proportion to time. Further, in the resist pattern 100, the amount of cutting in the longitudinal direction does not increase even if the amount of cutting in the lateral direction increases, which is different depending on the longitudinal direction and the lateral direction. That is, with the resist modification treatment of the present invention, the high-energy electrons are driven substantially vertically into the resist pattern 100' on the surface of the semiconductor wafer W, and the effect of the ions being substantially vertically driven is also multiplied. Compared with the horizontal direction, the resist pattern 100 is more strongly modified in the longitudinal direction from -30 to 200952069, and the degree of modification will be strengthened as time passes. However, since the peripheral portion (edge) of the resist pattern 100 is concentrated by ions, it is easy to cut, and as a result, it is formed in the longitudinal direction to be substantially the same plane as the side wall. In the first project, only the first high-frequency HF for plasma generation is applied to the susceptor (lower electrode) 12, and the second high-frequency LF for ion introduction control is not applied, but the first high-frequency LF is generated. The self-biasing of the application of the frequency HF, the positive ions in the plasma are drawn into the semiconductor wafer W by the electric field of the ion sheath, and are incident on the resist pattern 100. The mask selection ratio in the second project is as shown in the lower part of Fig. 17. It is 2.1 for the condition (a), 3.01 for the condition (b), and 3.09 for the condition (c). (d) is 3.45. From this result, it can be seen that the VDC condition (absolute 値 1500 V or more) is a dominant requirement for improving the mask selection ratio, that is, the etch resistance for improving the resist pattern 1 〇〇. In addition, it can be seen that the longer the processing time of the first project, the more the mask selection ratio is increased, and the etching resistance of the resist pattern 1 〇〇 becomes stronger. In the eighteenth aspect, the resist pattern (ARC) after the end of the first project, the resist pattern [SiN] after the completion of the second project, and the ash are shown by SEM photographs in the SEM photograph. The SiN pattern [Ash] after the end of the formation. As shown in the figure, between conditions (b), (c) and (d), the higher the pressure in the first project and the longer the treatment time, the higher the flatness of the side walls of the pattern is observed. Incidentally, as the LWR of the SiN pattern [Ash] of the final mask, the average 値 of 3 σ is 9.1 for the condition (a), and 8.3, -31 - 200952069 for the condition (b). 8.1. When condition (d) is 7.1. In the ninth embodiment, the control unit 1 1 〇 for controlling the order of the respective portions of the plasma processing apparatus (Figs. 1 and 13) and the entire order of the plasma processing method in the above-described embodiment is shown. example. The control unit 1 1 of the configuration example has a processor (CPU) 152, a memory (RAM) 154, a program storage device (HDD) 156, a floppy disk drive, a compact disk, and the like connected to each other via the bus bar 150. Disk drive (DRV) 158, keyboard or mouse input component (KEY) 160, display device (DIS) 162, network interface (COM) 164, and peripheral interface (I/F) 166 ° processor (CPU The 152 can be read by the FD or optical disk mounted on the disk drive (DRV) 158, and stored in the HDD 156. Alternatively, the network can also download the required program through the network interface 164. Next, the processor (CPU) 152 expands the code required for each stage or scene from the HDD 156 on the working memory (RAM) 154 to perform each step, performs necessary arithmetic processing, and controls through the peripheral interface 166. Each part in the apparatus (especially the exhaust unit 26, the high-frequency power source 30, 74, the processing gas supply unit 72, the variable DC power source 80, the switch 82, etc.). The programs for carrying out the plasma processing method described in the above embodiments are all executed by the computer system. In the above embodiment, the upper electrode 60 is used in the DC application member, but in the present invention, the chamber is exposed to the plasma in a direction perpendicular to the susceptor or in a direction oblique to the susceptor. Any of the conductive members may be used as a DC application member in the DC application member or 200952069, and a DC application member may be used, for example, in the other than the upper electrode 60. The DC voltage applied to the DC application member does not have to be always maintained at a certain voltage level, and an alternating voltage such as a low frequency may be overlapped. The substrate to be processed in the present invention is not limited to a semiconductor wafer, and may be various substrates for a flat panel display, a photomask, a CD substrate, a printing substrate, and the like. Further, the present invention is particularly suitably applied to an electric etch etching process using an ArF resist, but it is also applicable to plasma processing or microfabrication such as plasma etching processing using other resists. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a longitudinal sectional view showing the configuration of a plasma processing apparatus used in the plasma processing method of the present invention. Fig. 2 is a cross-sectional view showing the processing sequence when the trimming process is performed in a mode. Ο Fig. 3 is a cross-sectional view for explaining the action of the resist modification process of the resist pattern of driving electrons onto the semiconductor wafer in a mode. Figure 4 is a side elevational view showing the principle of resist modification of a resist pattern for driving electrons onto a semiconductor wafer in a mode. Fig. 5 is a view showing the effect of the modification obtained by the experiment of the resist modification treatment in the first embodiment in an SEM photograph. Fig. 6 is a view showing the effect of the modification obtained by the experiment of the resist modification treatment in the first embodiment by the step measurement of the oblique cutting. Fig. 7A is a diagram showing the effect of the modification obtained by the experiment of the resist modification treatment in the first embodiment by using Fourier transform infrared spectroscopy (FTIR) to confirm -33-200952069. Fig. 7B is a diagram showing the effect of the modification obtained by the experiment of the resist modification treatment in the first embodiment by Fourier transform infrared spectroscopy (F Τ IR ). Fig. 8 is a graph showing a theoretical relationship between electron energy and electron immersion depth when electrons are driven into a resist. Fig. 9 is a graph showing the results obtained by simulation in a graph showing the relationship between the depth at which electrons are stopped in the electrons entering the resist pattern and the ratio of the stopped electrons. Fig. 10 is a graph showing the relationship between the above simulation and the above experimental results. In the first embodiment, the cross-sectional shape of the pattern which has been subjected to the trimming treatment after the resist modification treatment in the first embodiment is shown by an SEM photograph in comparison with a comparative example. Fig. 1 2A is a view showing the pattern plane shape when the SiN film is etched after the resist modification treatment in the first embodiment, as shown in the SEM photograph. Fig. 1B is a view showing the pattern plane shape of the pattern of the comparative example when the resist film is not subjected to the resist modification treatment in the first embodiment (Comparative Example). Fig. 13 is a longitudinal sectional view showing another configuration of a plasma processing apparatus used in the plasma processing method of the present invention. Fig. 14 is a view showing a cross-sectional shape of a pattern after completion of each project obtained in Experiment No. 200952069 in the second embodiment in an SEM photograph. Fig. 15 is a diagram clearly showing the modified layer and the non-modified layer 2 in the pattern cross-sectional shape (SEM photograph) of Fig. 14 by image processing. Fig. 16 shows the s EM photograph. 2 Schematic diagram of the planar shape of the pattern at each stage in the embodiment. Fig. 17 is a schematic view showing the cross-sectional shape of the pattern after completion of each of the experiments obtained in the experiment in the third embodiment by SEM photograph. Fig. 18 is a view showing the planar shape of the pattern at each stage in the third embodiment in an SEM photograph. Fig. 19 is a block diagram showing an example of the configuration of a control unit in the embodiment. [Explanation of main component symbols] 1 〇: chamber (processing container) Φ 12: pedestal (lower electrode) 1 4 : cylindrical support portion 16: conductive cylindrical support portion (inner wall portion) 1 8 : exhaust path 20: Exhaust ring 22: Exhaust port 24: Exhaust pipe 26: Exhaust device 28: Gate valve-35- 200952069 30: Local frequency power supply for ion introduction 32: Integrator 3 6: Lower power supply rod 38: Focus ring (correction ring) 40 : electrostatic chuck 4 2 : DC power supply 44 : switch 4 6 : high voltage power supply line 4 8 : refrigerant chamber 5 0, 5 2 : piping 5 4 : gas supply pipe 6 0 : upper electrode 6 2 : electrode plate 64: Electrode support 6 5 : Insulator 6 6 : Gas diffusion chamber 6 8 : Gas discharge hole 70 : Gas supply pipe 72 : Process gas supply unit 74 : High-frequency power source for plasma generation 76 : Integrator 7 8 : Upper power supply rod 80: Variable DC power supply 8 2: Switch-36- 200952069 8 4 : DC power supply line 86: Filter circuit 8 8 : DC grounding part (DC grounding electrode)
9 0 :接地線 100 :阻劑圖案 102 : B ARC 1 04 : SiN 膜 φ 106 :基底膜（Si02層） 1 0 7 :改質層 1 〇 8 :非改質層 1 09 :界面 1 1 〇 :控制部 1 5 0 :匯流排 152 :處理器（CPU) 154 :記憶體（RAM ) 〇 156:程式儲放裝置（HDD) 158 :磁碟驅動器（DRV ) 160 :輸入元件（KEY ) 162 :顯示裝置（DIS ) 164 :網路.介面（COM ) 166:周邊介面（I/F) 168 :記憶媒體 HF :高頻 LF :高頻 -37- 200952069 PR :電漿 P S :處理空間 SHl :下部離子鞘 SHu :上部離子鞘 W :半導體晶圓 -389 0 : Grounding wire 100 : Resistive pattern 102 : B ARC 1 04 : SiN film φ 106 : Base film (SiO 2 layer) 1 0 7 : Modified layer 1 〇 8 : Non-modified layer 1 09 : Interface 1 1 〇 : Control unit 1 50: Bus 152: Processor (CPU) 154: Memory (RAM) 〇 156: Program storage device (HDD) 158: Disk drive (DRV) 160: Input element (KEY) 162: Display device (DIS) 164: Network. Interface (COM) 166: Peripheral interface (I/F) 168: Memory medium HF: High frequency LF: High frequency - 37- 200952069 PR: Plasma PS: Processing space SHl: Lower Ion sheath SHu: upper ion sheath W: semiconductor wafer-38