TW200950052A - Package structure having semiconductor component embedded therein and fabrication method thereof - Google Patents

Package structure having semiconductor component embedded therein and fabrication method thereof Download PDF

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Publication number
TW200950052A
TW200950052A TW097120144A TW97120144A TW200950052A TW 200950052 A TW200950052 A TW 200950052A TW 097120144 A TW097120144 A TW 097120144A TW 97120144 A TW97120144 A TW 97120144A TW 200950052 A TW200950052 A TW 200950052A
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Taiwan
Prior art keywords
layer
frame
package
dielectric layer
semiconductor
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TW097120144A
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Chinese (zh)
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TWI384606B (en
Inventor
Chao-Wen Shih
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Phoenix Prec Technology Corp
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Priority to TW097120144A priority Critical patent/TWI384606B/en
Publication of TW200950052A publication Critical patent/TW200950052A/en
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Publication of TWI384606B publication Critical patent/TWI384606B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

A method of fabricating a package structure having a semiconductor component embedded therein is proposed, characterized by forming a substrate body by bonding a semiconductor chip in the opening of a support frame and filling up a first dielectric layer, and thereafter, forming a first circuit layer for electrically connecting to the semiconductor chip without having to use a solder bump for connection, thereby facilitating miniaturization of the package structure. This invention further provides the package structure having an embedded semiconductor component as described above.

Description

200950052 兀、赞明說明： •【發明所屬之技術領域】 *' 本發明係有關於一種封裝处構及苴制、土 埋半導體元件之封裝結構及其^法。’尤指一種歲 【先前技術】 : 現行覆晶（Flip Chip)技術，主 -作用面上設有電極墊，同時於封穿 ^^體晶片的 •極墊之電性接觸墊，^又土板§又有相對應該電 ❹焊錫結構或其他導電黏著材料，㈣㈣之間形成 黏著材料提供該半導用料錫結構或導電 日月與封裝基板之間的電性搵 及機械連接’·相關技術如第W1G圖所示。…生連接 板太，f〇1A圖所不’百先提供一表面為介電層102之美 板本體10，係具有位於該介電層ϊ0?向 之基 及位於該介電㈣2上之複數電性接:墊 斤不，接著於該介電層 ❿防焊層1卜且於該防烊層 表面上心成一 接觸整103之開孔11〇β 7複數對應各該電性 η。之如孔第二=示，之後於該防輝層11表面、該開孔 IT 110 103^ =成有-v電層12’再於該導電層i2表面形成有阻層 ==3中形成有複數開口區13°，以議 琢各δ玄開孔11 〇及電性接縮執] 包『生接觸墊1〇3表面上 如第㈣所示，藉由該導電層12作為電鑛之電流傳 110725 6 200950052 导峪樘以於該開口區130中電纪 .勝以電性連接該電性接觸 =3成“焊錫之導電材 之1F B所*，然後移除該阻層及其所覆s 製程使該導電材料u融； :―14，，俾以完成-封裝基板卜 ^錫球之焊料凸塊 : 二第1G圖所示，係應用該封裝基板1之覆曰封驻处 構”亥封裝基板i具有相對之第：封I-❹lb’於該第—表面la a : 一表面 15具有一作用面ϊς ^坪卄凸塊14，—半導體晶片 焊料凸塊u，之導電3凸塊=用面…具有複數相對應該 包覆該導電凸塊’使该焊料凸塊14,經迴焊以 封裝基板卜且於士亥封:亥半導體晶片15電性連接該 充底勝（underfi⑴16 與半導體晶月15之間填 ❹該焊料凸塊〜此將佔用該封=迴嬋而接置於 之面積，而無法達到高 U 1 4 —表面la 間距之目的。 义佈線及焊料兀件14,之間的細 之作用：15:2=之第-表面1a與半導體晶片15 凸塊u,及底及底膠16,而該焊料 法達到薄小封農之目的曰加封裳結構之整體高度，因而無 又忒半導體晶片15藉由該焊料凸塊14,及該封裝基 ]10725 7 200950052 m却之導線，使信號可傳輸 •電路板電性導通，其電訊傳 以之^斗球而與 ..故相對地降低電性功能。 w長’且阻抗亦較高’ 距以達咼密度佈線、薄小封 Γ1的間 重要課題。 ^封破及降低阻抗，已成為業界之 【發明内容】 ο 供L方' 上述白知技術之缺失，本發明之-目的俜在於槎 供一種钱埋本塞邮+ X· _>* 1 j加、n & 裡甘人埋牛V瓶兀件之封裝結構 密度佈線。 八衣法俾此達到向 本發明又—目的係在於提供 封奘έ士棋β甘在,】、_!_ 4里甘入J里平導體7L件之 俾能達到輕薄&小之封裝結構。 封穿^及乂细目的係'在於提供—種嵌埋半導趙元件之 徑，以提高電性功能。_ ^且“電訊傳導路 ❹件之二二及^他目的’本發明提供—種嵌埋半導體元 I ’係包括：支撐框，係具有相對之第一及第 ;'面’且具有貫穿該第-及第二框面之框口；半導體晶 ^係設於該框π中，且具有相對之作用面及非作用面， ”亥作用面與該支撐框之第一框 數電㈣.帛八♦ 且該作用面具有複 介ίΓ二，係填充於該框口中，俾使該第- 半導體晶片形成-基板本體，且該 有相對之第一及第二表面’以對應該支標框之 及苐一框面，第一線路層，係設於該第一介電層上， 110725 200950052 m弟-介電層中具有複數第一 二::：:广係_基:本體:= ，以電性連接該第-線路層東路層上，且具有第二導電盲孔 月述之結構中，該支撐框得 係可與支擇框之第-框面齊平了為鋼，且該第一介電層 w述之結構中，該增層結構復可包括有至少 八 ❹200950052 兀, 赞明说明: • [Technical field to which the invention belongs] *' The present invention relates to a package structure and a package structure of a buried semiconductor device and a method thereof. 'In particular, one year old [previous technology]: The current flip chip technology, the electrode pad is provided on the main-active surface, and the electrical contact pad of the pole pad is sealed at the same time. The board § has a corresponding electric solder structure or other conductive adhesive material, and (4) (4) form an adhesive material to provide the semi-conductive tin structure or electrical enthalpy and mechanical connection between the conductive solar cell and the package substrate. As shown in the W1G chart. The raw connection board is too large, and the first board body 10 having a surface of the dielectric layer 102 is provided with a plurality of electrodes located on the base of the dielectric layer and on the dielectric (four) 2 Sexual connection: the padding is not carried out, and then the soldering layer 1 on the dielectric layer and the opening 11 on the surface of the anti-corrosion layer is in contact with the opening 103 〇β 7 in plurality corresponding to the electrical η. For example, the second hole of the hole is shown, and then the surface of the anti-glare layer 11 is formed with the -v electrical layer 12' and the resistive layer is formed on the surface of the conductive layer i2. The opening area is 13°, in order to discuss the δ 玄 孔 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 Pass 110725 6 200950052 Guide for the opening area 130. The electric contact is electrically connected to the electrical contact = 3% "1F B of the conductive material of the solder*, and then the resist layer and its coating are removed. s process makes the conductive material u melt; : "14,, 俾 to complete - the soldering bump of the package substrate ^ solder ball: 2, the first GG shows the application of the package substrate 1 The package substrate i has a first surface: a seal I-❹ lb' on the first surface la a : a surface 15 has an active surface 卄 卄 卄 bump 14 , a semiconductor wafer solder bump u, a conductive 3 bump = using a surface ... having a plurality of oppositely covering the conductive bumps ' such that the solder bumps 14 are reflowed to encapsulate the substrate and electrically connected to the sigma semiconductor chip 15 Bottom wins (underfi(1)16 and semiconductor crystal moon 15 fill the solder bumps~ this will occupy the area of the seal = return and not reach the high U 1 4 - surface la spacing. The effect of the soldering member 14 is as follows: 15:2 = the first surface 1a and the semiconductor wafer 15 bump u, and the bottom and the bottom adhesive 16, and the solder method achieves the purpose of thin and small agriculture. The overall height of the structure, and thus the semiconductor wafer 15 by the solder bumps 14, and the package base] 10725 7 200950052 m wire, so that the signal can be transmitted • the circuit board is electrically connected, and its telecommunications pass ^ Fighting the ball and the relative reduction of the electrical function. w long 'and the impedance is also higher'. Between the density of the wiring, thin and small seal 1 important issues. ^ Sealing and reducing the impedance, has become the industry SUMMARY OF THE INVENTION ο For the L-party's lack of the above-mentioned white technology, the purpose of the present invention is to provide a money for the buried mail + X · _ > * 1 j plus, n & Ligan people buried cattle V The package structure density wiring of the bottle parts. The eight clothes method is further achieved by the present invention. Sealed chess chess β Gan,, _!_ 4 Li Gan into the J flat conductor 7L pieces can reach the thin &small; small package structure. Sealing ^ and 乂 detail of the line 'is provided - type embedded Buried semi-conducting elements of the Zhao element to improve the electrical function. _ ^ and "Telecom conduction path element two and two purposes" The present invention provides an embedded semiconductor element I 'system includes: a support frame, has Relative to the first and the first; 'face' and having a frame opening through the first and second frame faces; the semiconductor crystal system is disposed in the frame π, and has a relative active surface and a non-active surface, The surface of the first frame of the support frame is electrically charged (4). The active surface has a double layer, and the active surface is filled in the frame, so that the first semiconductor wafer is formed into a substrate body, and the opposite surface is formed. The first and second surfaces are disposed on the first dielectric layer corresponding to the frame and the first circuit layer, and the first and second layers are in the 110725 200950052 m-dielectric layer. :::: Guang system _ base: body: =, electrically connected to the first circuit layer on the east road layer, and has a second conductive blind hole structure The support frame may be obtained based on branched Optional block - A block is flush with the face of the steel structure and the first dielectric layer of said w, the multiplexed-up structure may comprise at least eight ❹

:f;二:成於第二介電層上之第二線路層，且該 包目孔故於弟二介電層中並部份電性 弟一 V 最外面之第二線路層具有電性接料^^路層，而 成防焊層，且形成開孔以顯露該電:接:^增層結構上形 依上述結構’該電性接觸墊上可設有 表面處理層係為鎳/金、鎳/鈀 層，该 如為錫球之焊料球。 銀或金，俾供設置例 散熱Γ另一實施態樣中，該基板本體之第二表面可結合 ❿ S者本發明復提供一種嵌埋半導 ，製法，係包括:提供-承載板;於該承载板上二， 者=合散熱板，·提供—支樓框，係具有 ^ :框：’且具有貫穿該第-及第二框面之框口丄S 口：！：框面以第二黏著層結合於該散熱板上“ 體晶片，該㈣體晶片具有相對之:之結合半導 作用面具有複數電極塾，且，亥半 丨用面’該 亥丰^晶片以該非作用面結 110725 9 200950052 w熱板上’該支樓桓之第一框面並高於該作周面； .框^1〇中填充第—介電層，且該第—介電層與 …' :1之第—框面齊平，俾使該第-介電層、該支撐框 ❹ 體曰::片係構成一基板本體，且該基板本體具有相 •’弟一及第二表面，並對應該支撐框之第一及第二框 於該第—介電層上形成有第-線路層，且該第一介電 :第一導電盲孔，以對應電性連接各該該電極 声"冓，1二二體之第一表面及第一線路層上形成有增 有第二導電盲孔以電性連接至該 整版面封;板。 第一黏著層及承載板，以形成一 前述之製法中， 藉由一離型層及第一 第一黏著層位於同一 黏著層及承载板。 該支+撐框係可為銅，且該承載板係可 黏著層結合至散熱板，而該離型層與 表面上，後續再移除該離型層、第一 别述之製法可包括切割該整版面封裝 :構單元：亦可包括移除該散熱板。 别：之製法中，該第一線路層之製法 5亥苐一介電層中形成第 竹J。括.於 框上、第-介電層上第：顯露電極塾；於該支擇 層；於該導電層上开1 ，孔中、及電極墊上形成導電 /絝電層上形成阻層， 电 導電層；於開口區中m /成開口區，以顯露部份 成第-導帝4 / 線路層，並於第一開孔中形 目孔，俾使第一線路芦 連接電極墊；以及0精由第一導電盲孔電性 乂及移除该阻層及其所覆蓋之導電層。 110725 10 200950052 月'j迷之製法中，該 層、形成於第二介電層上之第二括至少-第二介電 -介電層中且電性連接第一及0 u及形成於第二 孔，而最外面之第_岣 一4路層之第二導電盲 結構上形成防焊電性接觸墊，並於該增層 依上述=層，且形成開孔以顯露電性接觸塾。 層，且今表⑤! Χ可於該電性接觸墊上形成表面處理 且孩表面處理層係 π面處理 以可於表面處理層上形成焊料球…"金、銀或金， 法，係發明嵌埋半導#元件之封裝結構及其f 二半導體=结合具有框…樓框，心 體，再第一介電層，俾形成-基板本 ▽衣IF乐線路層以電性漣桩♦托拙4 術，本發明不需使 电11 ，目較習知技 路層盘電咖 塊及焊料凸塊，即可使第-線 的，且使第—⑽@密度佈線之目 丨 ν θ與半導體晶片之間無間隔’而達到薄 ::裝’又能縮短電流傳導路徑，並降 罾功能；另外，去浐拉π α、 代门电「生 心形成一環繞半導體晶片之圍蔽結構， 可私加封裝構件之防濕性。 【實施方式】 ▲以下係藉由特定的具體實例說明本發明之實施方 式’熟悉此技蟄之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 。月參閱第2Α至2Κ圖，係詳細說明本發明之欲埋半導 組日日片之封裝結構之製法剖面示意圖。 110725 11 200950052 如弟2A圖所示，首先，提供一係為銅箔基板（c〇pper:f; 2: forming a second circuit layer on the second dielectric layer, and the inclusion hole is in the second dielectric layer and partially electrically-electrically-V-the outermost second circuit layer is electrically Receiving the ^^ road layer, forming a solder mask, and forming an opening to reveal the electricity: the connection: the build-up structure is formed according to the above structure. The electrical contact pad may be provided with a surface treatment layer of nickel/gold. a nickel/palladium layer, such as a solder ball of a solder ball. In another embodiment, the second surface of the substrate body can be combined with the ❿ S. The present invention provides an embedded semiconductor, the method comprising: providing a carrier plate; The carrier board has two, the = heat sink board, and the - branch frame, which has a ^ frame: 'and has a frame opening through the first and second frame faces: S:! The frame surface is bonded to the heat dissipation plate by a second adhesive layer, and the (four) body wafer has a plurality of opposite electrodes: the combined semiconductor surface has a plurality of electrodes, and the half of the surface is used. The first frame surface of the branch wall of the non-active surface junction 110725 9 200950052 w is higher than the circumferential surface; the first dielectric layer is filled in the frame, and the first dielectric layer is filled The first dielectric layer and the support frame are the same as the first dielectric layer and the support frame: the substrate is a substrate body, and the substrate body has a phase one and a second Forming, on the first and second frames of the support frame, a first line layer formed on the first dielectric layer, and the first dielectric: the first conductive blind hole, corresponding to the electrical connection The first surface of the electrode and the first circuit layer are formed with a second conductive blind hole electrically connected to the full-face mask; the first adhesive layer and the carrier plate are In the method of forming the foregoing, the release layer and the carrier layer are located by a release layer and the first first adhesive layer. Copper, and the carrier layer is adhesively bonded to the heat dissipation plate, and the release layer and the surface are subsequently removed, and the first alternative method may include cutting the full-page package: a structural unit: The method further comprises: removing the heat dissipation plate. In the method of manufacturing, the first circuit layer is formed by forming a second J in a dielectric layer, including on the frame and the first dielectric layer: Electrode 塾; in the selective layer; opening a hole in the conductive layer, forming a resistive layer on the conductive/germant layer on the electrode pad, forming an electric conductive layer; and forming an open area in the open area to reveal Partially into the first - guide 4 / circuit layer, and in the first opening, the eyelet is shaped, so that the first line is connected to the electrode pad; and 0 is electrically removed from the first conductive blind hole and the resistance is removed a layer and a conductive layer covered thereby. 110725 10 200950052 In the method of manufacturing, the layer is formed in a second dielectric layer of at least a second dielectric-dielectric layer formed on the second dielectric layer and electrically connected The first and the 0 u are formed in the second hole, and the second conductive blind structure of the outermost layer of the fourth layer forms a solder resistive electrical contact And the layer is formed according to the above-mentioned layer, and an opening is formed to expose the electrical contact layer. The layer can be formed on the electrical contact pad and the surface layer of the surface is π-faced. A solder ball can be formed on the surface treatment layer..."gold, silver or gold, the method of inventing the embedded semi-conducting element and its f-semiconductor=combination has a frame...a frame, a heart, and then a first The dielectric layer, the 俾 formation-substrate ▽ IF IF 线路 circuit layer is electrically 涟 ♦ 拙 拙 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , It is possible to make the first line and make the first (10)@ density wiring between the target ν θ and the semiconductor wafer without the gap 'to achieve a thin:: 'can shorten the current conduction path and reduce the function; To pull the π α, the generation of the gate "to form a surrounding structure of the semiconductor wafer, the privacy of the package member can be privately added. [Embodiment] The following embodiments of the present invention are described by way of specific examples. Those skilled in the art can readily appreciate the other advantages and advantages of the present invention from the disclosure herein. . Referring to Figures 2 to 2, a schematic cross-sectional view showing the structure of the package structure of the semiconductor wafer to be buried in the present invention will be described in detail. 110725 11 200950052 As shown in Figure 2A, first, provide a series of copper foil substrates (c〇pper

Clad Laminates, CCL)之承載板 20。 - 如第2B圖所示，於該承載板20上以第一黏著層21a -及離型層22結合一散熱板23 ;再提供一係為銅（Cu)材 之支撐框24，該支撐框24係具有相對之第一及第二框面 24a，24b，且具有貫穿該第一及第二框面24心2仆之框口 • 240，該支撐框240之第二框面24b以第二黏著層2lb結 '合於散熱板23上，並藉框口 240顯露部份散熱板23，又 〇該離型層22與第-黏著層21a位於同—表面上且對應該 框口 240。 請參閱第2B，圖’於另一實施例中，該承載板2〇上 亦可僅以第-黏著層2la結合—散熱板23 ;㉟，於本實 施例中，該承載板20增設離型層22,以便於後續製程 之分離作業。 如弟2C圖所示’於該框口 240中顯露之散熱板23 上接置有半導體晶片25,所述之半導體晶片25具有相對 ®之作用面25a及非作用自现，且該作用面❿具有複數 電極塾25卜而該半導體晶片25以該非作用面现接置 於散熱板23上，·另外，該支撐框24之第一框面2 該半導體晶片25之作用面25a。 、 如第2D圖所示，於該框口 24()中填滿第—介 260，使該第一介電層k 屯增26〇表面與支撐框24之第一框面 ^齊平’且該第一介電層260與半導體晶片25之作用 面祝及側表面25c相結合，俾使該第一介電層26〇、支 110725 12 200950052 …及半導體晶片25構成 .體2具有_之第-表面2a及第二表;;^且縣板本 第-SI 2:圖所示’於該第一介電層26°中形成有複數 .弟開孔260a，以對庫眞苜臂夂# 251。 丁…颂路各该+導體晶片25之電極墊 如弟2 F圖所示，於今古p祐〜 箧一入希段η 於。亥支咎框24之第一框面24a上、 ：卜)丨电e 60上（即基板本體2之第一表面2a上）、 第一開孔260a之孔壁及泰搞執9 97 电極墊251上形成有導電層27, ❹：二 成有阻層28,且於該阻層28中形 成有㈣開口區28〇’以顯露部份之導電層仏 如第2G圖所示，於該開 杰古资^ A x開口區28〇中之導電層27上形 成有苐一線路層261，並於該第— ^ 一導電盲孔262，俾使哕$ % 8形成有第 π 9W 亥弟一線路層261藉由第一導電盲 1性連接至該半導體晶片25之電極塾251。 如第2Η圖所示，移除該阻 27,以顯露該第一線路層261。及-所覆盍之導電層Clad Laminates, CCL) carrier board 20. - as shown in FIG. 2B, a heat dissipation plate 23 is bonded to the carrier 20 with the first adhesive layer 21a and the release layer 22; and a support frame 24 of copper (Cu) material is provided. The 24 series has opposite first and second frame faces 24a, 24b, and has a frame opening 240 extending through the first and second frame faces 24, and the second frame face 24b of the support frame 240 is second. The adhesive layer 2b is bonded to the heat dissipation plate 23, and a part of the heat dissipation plate 23 is exposed by the frame opening 240, and the release layer 22 and the first adhesive layer 21a are located on the same surface and correspond to the frame opening 240. Referring to FIG. 2B, in another embodiment, the carrier plate 2 may be bonded only by the first adhesive layer 2la--the heat dissipation plate 23; 35. In this embodiment, the carrier plate 20 is additionally provided with a release type. Layer 22 facilitates the separation of subsequent processes. As shown in FIG. 2C, the semiconductor wafer 25 is mounted on the heat dissipation plate 23 exposed in the frame 240. The semiconductor wafer 25 has a working surface 25a opposite to the surface, and the active surface ❿ The semiconductor wafer 25 is placed on the heat sink 23 with the non-active surface, and the first frame surface 2 of the support frame 24 is the active surface 25a of the semiconductor wafer 25. As shown in FIG. 2D, the second opening 246 is filled in the frame 24 (), so that the surface of the first dielectric layer k is increased by 26 齐 and the first frame surface of the support frame 24 is flush with each other. The first dielectric layer 260 is combined with the active surface of the semiconductor wafer 25 and the side surface 25c, so that the first dielectric layer 26, the support 110725 12 200950052 ... and the semiconductor wafer 25 are formed. - Surface 2a and the second table;; ^ and the county plate - SI 2: the figure shown in the first dielectric layer 26 ° formed in the plural. Brother opening 260a, to the library 眞苜 arm 夂 # 251. Ding...颂路 Each electrode pad of the +conductor wafer 25 As shown in the figure 2 F, in this ancient pyou ~ 箧一入希段 η 于. On the first frame surface 24a of the cymbal frame 24, on the e e e 60 (i.e., on the first surface 2a of the substrate body 2), the hole wall of the first opening 260a, and the electrode of the 997 electrode A conductive layer 27 is formed on the pad 251, and a resist layer 28 is formed, and (4) an open region 28〇' is formed in the resist layer 28 to expose a portion of the conductive layer, as shown in FIG. 2G. A conductive layer 27 is formed on the conductive layer 27 of the opening area of the open space of the open source, and the first conductive layer 27 is formed in the first conductive hole 262, so that 哕$% 8 is formed with the π 9W A wiring layer 261 is blindly connected to the electrode pads 251 of the semiconductor wafer 25 by a first conductive. As shown in Figure 2, the resistor 27 is removed to reveal the first circuit layer 261. And - the conductive layer covered

© 本發明藉由該第一線路層？ β 1 # I 體晶片25之電極塾25卜心羽直接⑪性連接該半導 道φ 才車父於習知技術’因不需透讲 導電凸塊及焊料凸塊，即可使 口不兩透過 片25連接，俾使封裝結構 、千等體日日 傳導路徑；又，該第一線跋思Λ度南’且縮短電流 並無外接凸塊，得以使整㈣驻/、+導體曰曰片25之間 叹正奴封裝結構體積縮小。 及第如^21圖所示，於該切框24、第一介電層26〇、 及第-線路層261上形成有增層結構3，該增層結構“系 】】0725 13 200950052 巴牯主少一第二介電層300、形成於該第二介電層3〇〇上 .之第二線路層301、以及形成於該第二介電層3〇〇中且電 •-性連接5亥第一線路層3 01之複數第二導電盲孔3 〇 2，其 -中，部份第二導電盲孔302電性連接該第—線路層261， 且於該增層結構3最外面之第二線路層301具有複數電性 接觸墊303，並於該增層結構3上形成防焊層33，並於該 :防焊層33中形成有複數開孔330，以對應顯露各該電性 ^ 接觸墊303。 ❺ 所述之電性接觸墊303之表面上形成表面處理層 34，且該表面處理層34係為鎳/金（Ni/Au)、鎳/鈀/ = (Ni/Pd/Au)、銀（Ag)及金（Au)之其中一者。 如第2J圖所示，藉由移除該第一黏著層21&及離型 層22，使該承載板20由散熱板23上分離，俾完成一整 版面封裝板4 ’之製作。 如第2K圖所示，切割該整版面封裝板4，以形成複數 封裝結構單元4,且該封裝結構單元4底面（即基板本體 © 2之第二表面2b)具有散熱板23，而該散熱板23與支樓 框24形成一環繞半導體晶片25之圍蔽結構，以增加封= 構件之防濕性；另外，該表面處理層34上形成 _ 之焊料球35。 然，於另一實施態樣中， 該散熱板23，以外露該半導體 便於散熱。 如第2Γ圖所示’復可移除 晶片25之非作用面25b而 依所述之製法’本發明復提供一種嵌埋半導體晶片之 Π0725 】4 200950052 蚵衮’，係包括：支撐框24，係具有相對之第一及第 .二框面24a，24b，且具有貫穿該第一及第二框面24a，24b 之框口 240’，·半導體晶片25，係設於框口 24〇中，且且 _有相對之作用面25a及非作用面挪，該作用面2… 撐框24之第一框面24a同側，並具有電極塾251 ;第一 介電層260’係填滿框口 24〇而包覆半導體晶片&，俾使 = 電層260、支撐框24及半導體晶片⑺形成一基 板=胜2,且該基板本體2具有相對之第一表面％及第 ❹一表面2b’以對應第一及第二框面24a，24b;帛一線路層 261，係設於第一介電層26〇 ， 且方、弟—介電層260中 具有複㈣-導電盲孔262以電性連接各電極塾Μη以 及增層結構3 ’係設於該基板本體2之第—表面2心 :電層260及第一線路層261上，且電性連接第一線路層 中’該增層結構3係包括至少-第二介電層300、 =於第二介電層300上之第二線路層3〇ι、以及設於第二 〇 ^電層_中且電性連接第一及第二線路層261，期 -導電盲孔302,且最外面之第二線路層斯具有電性 =墊303’而於該增層結構3上設有防焊層犯，該防焊声 具有開孔330以對應顯露該電性接觸墊3〇3。 再者，該電性接觸墊303上設有表面處理層34，俾 t设置例如為錫球之焊料球35,且於該基板本體2之第 二表面2b設有散熱板23。 綜上所述’本發明嵌埋半導體元件之封裝結構及其製 110725 15 200950052 α…亦相·由具有框口之支撐框埋設半導體晶片，再以第— • ’泉路層$性連接半導體晶片，俾使該第一線路層與半導體 -' 〗並無^電凸塊及焊料凸塊，不僅使該第一線路層 、與半導體晶片之間無間隔而達到薄小封裝，且達高密度佈 、’泉之目的，又能縮短電流傳導路徑及降低阻抗以提高電性 功此，另外，支撐框形成一環繞半導體元件之圍蔽結構， 以增加封裝構件之防濕性。 上述實施例僅例示性說明本發明之原理及其功效，而 〇非用於限制本發明。任何熟習此項技藝之人士均可在 背本發明之精神及範訂，對上述實施例進行修飾盘改© The present invention by the first circuit layer? The electrode 塾 25 of the β 1 # I body wafer 25 is directly connected to the semi-channel φ. The car is in the conventional technology. Because there is no need to talk about the conductive bumps and the solder bumps, the two can pass through the film. 25 connection, so that the package structure, thousands of body day conduction path; in addition, the first line 跋思Λ南' and shorten the current without external bumps, so that the whole (four) station /, + conductor 曰曰 25 The size of the sighed slave package is reduced. And as shown in FIG. 21, a build-up structure 3 is formed on the dicing frame 24, the first dielectric layer 26A, and the first-line layer 261, and the build-up structure is "system"] 0725 13 200950052 a second dielectric layer 300, a second circuit layer 301 formed on the second dielectric layer 3, and a second dielectric layer 3〇〇 and an electrical connection 5 a plurality of second conductive blind vias 3 〇 2 of the first circuit layer 3 01, wherein a portion of the second conductive vias 302 are electrically connected to the first wiring layer 261, and the outermost layer of the buildup structure 3 The second circuit layer 301 has a plurality of electrical contact pads 303, and a solder resist layer 33 is formed on the build-up structure 3, and a plurality of openings 330 are formed in the solder resist layer 33 to correspondingly expose the electrical properties. ^ Contact pad 303. A surface treatment layer 34 is formed on the surface of the electrical contact pad 303, and the surface treatment layer 34 is nickel/gold (Ni/Au), nickel/palladium/= (Ni/Pd/ One of Au), silver (Ag), and gold (Au). As shown in FIG. 2J, by removing the first adhesive layer 21 & and the release layer 22, the carrier 20 is made of a heat sink 23 Separate and finish Manufacture of the layout package board 4'. As shown in Fig. 2K, the full-face package board 4 is cut to form a plurality of package structure units 4, and the bottom surface of the package structure unit 4 (i.e., the second surface 2b of the substrate body © 2) A heat dissipating plate 23 is formed, and the heat dissipating plate 23 and the branch frame 24 form a surrounding structure surrounding the semiconductor wafer 25 to increase the moisture resistance of the sealing member; in addition, the solder ball 35 is formed on the surface treating layer 34. However, in another embodiment, the heat dissipation plate 23 exposes the semiconductor to facilitate heat dissipation. As shown in FIG. 2, the invention can be used to remove the non-active surface 25b of the wafer 25 according to the method described. Providing a buried semiconductor wafer Π0725 】4 200950052 蚵衮', comprising: a support frame 24 having opposite first and second frame faces 24a, 24b, and having through the first and second frames The frame 24' of the 24a, 24b, the semiconductor wafer 25 is disposed in the frame port 24, and has a relative action surface 25a and an inactive surface, the first frame of the action frame 2... The face 24a is on the same side and has an electrode 塾251; the first dielectric layer 260' is filled The frame 24 is covered with a semiconductor wafer & = = electrical layer 260, support frame 24 and semiconductor wafer (7) form a substrate = win 2, and the substrate body 2 has a first surface % and a first surface opposite 2b' corresponds to the first and second frame faces 24a, 24b; the first circuit layer 261 is disposed on the first dielectric layer 26A, and the square-dielectric layer 260 has a complex (four)-conductive blind hole 262. Electrically connecting the electrodes 塾Μη and the build-up structure 3′ are disposed on the first surface 2 of the substrate body 2: the electrical layer 260 and the first circuit layer 261, and electrically connected to the first circuit layer. The build-up structure 3 includes at least a second dielectric layer 300, a second circuit layer 3〇 on the second dielectric layer 300, and a second electrical layer _ and is electrically connected first. And the second circuit layer 261, the period-conducting blind hole 302, and the outermost second circuit layer has electrical property = pad 303', and the build-up structure 3 is provided with a solder resist layer, and the solder resist has The opening 330 is configured to correspondingly expose the electrical contact pad 3〇3. Further, the electrical contact pad 303 is provided with a surface treatment layer 34, for example, a solder ball 35 of a solder ball, and a heat dissipation plate 23 is provided on the second surface 2b of the substrate body 2. In summary, the package structure of the embedded semiconductor device of the present invention and its manufacture 110725 15 200950052 α... also embed a semiconductor wafer by a support frame having a frame, and then connect the semiconductor wafer with a first 'spring' layer The first circuit layer and the semiconductor are not provided with electric bumps and solder bumps, so that the first circuit layer and the semiconductor wafer are not spaced apart to achieve a thin package, and the high density cloth is provided. The purpose of the spring is to shorten the current conduction path and reduce the impedance to improve the electrical function. In addition, the support frame forms a surrounding structure surrounding the semiconductor component to increase the moisture resistance of the package member. The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Anyone skilled in the art can modify the above embodiments to modify the spirit and scope of the present invention.

，。因此’本發明之權利保護範圍，應如後述之中 範圍所列。 J 【圖式簡單說明】 第1A及1G圖係為習知覆晶式封裝基板之製 接合技術之剖視示意圖；以及 復日日 第2A至2K圖係為本發明之嵌埋半導體元件 ©構及其製法之剖視示意圖…，第2β，係為第2上 另一實施態樣剖視示意圖，且第2K，係為第2 之 實施態樣剖視示意圖。 另一 【主要元件符號說明】 1 封裝基板 la, 2a 第一表面 lb, 2b 第二表面 10, 2 基板本體 110725 16 200950052 i u i 102 1 03, 303 104 11, 33 110,330 12, 27 13,28 ^ 130,280 14 \A, 15, 25 15a, 25a 151 16 20 〇 21a 21b 22 23 24 240 251 25b 内層線路 介電層 電性接觸墊 導電盲孔 防焊層 開孔 導電層 阻層 開口區 導電材料 焊料凸塊 半導體晶片 作用面 導電凸塊 底膠 承載板 第一黏著層 第二黏著層 離型層 散熱板 支樓框 框口 電極墊 非作用面 200950052 乙 側表面 260 第一介電層 260 a 第一開孔 261 第一線路層 262 第一導電盲孔 3 增層結構 300 第二介電層 •301 第二線路層 ^ 302 ❹ 第二導電盲孔 34 表面處理層 35 焊料球 4 封裝結構單元 4， 整版面封裝板 ❿ 18 110725,. Therefore, the scope of protection of the present invention should be as listed in the scope of the following description. J [Simplified Schematic Description] Figs. 1A and 1G are schematic cross-sectional views showing a bonding technique of a conventional flip chip package substrate; and Figs. 2A to 2K are the embedded semiconductor elements of the present invention. FIG. 2 is a cross-sectional view showing another embodiment of the second embodiment, and FIG. 2K is a schematic cross-sectional view showing the second embodiment. [Main component symbol description] 1 package substrate la, 2a first surface lb, 2b second surface 10, 2 substrate body 110725 16 200950052 iui 102 1 03, 303 104 11, 33 110,330 12, 27 13,28 ^ 130,280 14 \A, 15, 25 15a, 25a 151 16 20 〇21a 21b 22 23 24 240 251 25b inner layer dielectric layer electrical contact pad conductive blind hole solder mask open hole conductive layer resistive layer open area conductive material solder bump Semiconductor wafer active surface conductive bump primer carrier first adhesive layer second adhesive layer release layer heat dissipation plate support frame frame electrode pad non-active surface 200950052 B side surface 260 first dielectric layer 260 a first opening 261 First circuit layer 262 first conductive blind via 3 build-up structure 300 second dielectric layer • 301 second circuit layer ^ 302 ❹ second conductive blind via 34 surface finish layer 35 solder ball 4 package structure unit 4, full-page package ❿ 18 110725

Claims (1)

200950052 τ 1. ❹ ❹ 2. 3. 肀請專利範圍： 一種嵌埋半導體元件之封裝結構，係包括： 支撐框，係具有相對之第一及第二框面，且具有 貫穿該第一及第二框面之框口； 半導體晶片，係設於該框口中，且具有相對之作 用面及非作用® ’該作用面與該支#框之第-框面同 側，且該作用面具有複數電極墊； 第一介電層，係填充於該框口中，俾使該第 電層、該支撐框及該半導體晶片形成-基板本體，且 =基板：體具有相對之第一及第二表面，以對應該支 撑框之第一及第二框面； 第-線路層’係設於該第一介電層上，且於 一介電層中具有複數第一 ' ^ 電極塾；以及 Η目孔％性連接各該 增層結構，係設於該基板本體之第—表 w電層及该第一線路層上， _ 性連接該第一線路層。 、有弟盲孔以電 如申叫專利範圍第1項之後半 構，其中，該支榜框係為銅(CuH 之封裝結 :申2利範圍第i項之嵌埋半導體元件之封裝社 平該第-介電層係與該支撐框之第一框面； :申=利範圍第1項之谈埋半導體元件之封裝結 -°亥基板本體之第二表面結合散熱板。 Ο 110725 】9 4. 200950052 3.戈口 T請專利範圍第1 TS +山 .項之嵌埋半導體元件之封f处 構，其中，該增層結構復包括至少一第二^衣: -- 形成於該第二介電層上之第-綠々 θ及 、盲孔設於該第二介電#中;路層，且該第二導電 路層，而最外面之第二層份電性連接該第-線 编增層結構上形成有防焊層，且二=有 複數開孔以對應顯露各該電性接觸墊。 成有 如申請專利範圍第5項之 構，其中，該電性 h兀件之封裝結 也性接觸墊上設有表面處理層。 如申請專利範圍第6項 構，並中，兮#&南 瓜埋+绔體凡件之封裝結 :、中遠表面處理層係為鎳/金（Ni/Au)、 金㈤/Pd/Au)、銀（Ag)或金（Au)。 桌/纪/ 如申請專利範圍第6項之嵌 構，1中n Μ +導件之封裝結 八甲5亥表面處理層結合焊料球。 一種，埋半導體元件之封裝結構之製法，係包括： 提供一承载板； 於'•亥承載板上以第一黏著層結合散熱板； 支撐框，係具有相對之第—及第二框面， ^貝穿該第-及第二框面之框口’且該支樓框之 口以第二黏著層結合於該散熱板上，並藉該框 口顯路部份之散熱板； ❹ φ 6. 7. 8. 9. 於該框口中之散熱板上結合半導體晶片，該 體晶片具有相對之作用 了乏作用面及非作用面，該作用面具有 電極塾，且該半導體晶以該非作用面結合於該 Π0725 20 200950052 職板上，該支㈣之第—框面並高 八於該支樓框之框口中填充第-介電層= … 4層與該支抛之第—框㈣+，心4=— 、層、該支樓框及該半導體晶片係構成— 電 該基板本體具有相對之第— 土板本體，且 • 馳之第-及第二框面 並對應該支 方…亥第"电層上形成有第-線路層 )丨電層中形成複數第一導電盲孔， 且该第— ❹該該電極墊； $目孔叫應電性連接各200950052 τ 1. ❹ ❹ 2. 3. Scope of the patent: A package structure for embedded semiconductor components, comprising: a support frame having opposite first and second frame faces and having a first and a second a frame of the second frame; the semiconductor wafer is disposed in the frame and has a relative active surface and an inactive surface of the 'the same surface as the first frame of the frame #, and the active surface has a plurality of An electrode pad; the first dielectric layer is filled in the frame, so that the first electrical layer, the support frame and the semiconductor wafer form a substrate body, and the substrate: the body has opposite first and second surfaces, Corresponding to the first and second frame faces of the support frame; the first circuit layer is disposed on the first dielectric layer, and has a plurality of first '^ electrode electrodes in a dielectric layer; Each of the build-up structures is connected to the first and second circuit layers of the substrate body, and is connected to the first circuit layer. There is a blind hole in the body, such as the application of the patent scope of the first half of the structure, which is the frame of the copper (CuH package: Shen 2 Lee range i item of embedded semiconductor components package The first dielectric layer is the first frame surface of the support frame; and the second surface of the substrate body is bonded to the heat dissipation plate. Ο 110725 】 9 4. 200950052 3. Gekou T please patent the first TS + mountain. The embedded semiconductor component of the semiconductor structure, wherein the buildup structure includes at least one second garment: -- formed in the first a first-green 々 θ and a blind hole on the second dielectric layer are disposed in the second dielectric #; a road layer, and the second conductive circuit layer, and the outermost second layer is electrically connected to the first- A solder resist layer is formed on the wire braided layer structure, and two = a plurality of openings are formed to correspondingly expose the respective electrical contact pads. The invention has the structure of the fifth aspect of the patent application, wherein the package of the electrical component A surface treatment layer is provided on the junction contact pad. For example, the sixth aspect of the patent application scope, and the package of the 兮#& pumpkin burial + 绔 body parts : The COSCO surface treatment layer is nickel/gold (Ni/Au), gold (five)/Pd/Au), silver (Ag) or gold (Au). Table/Ji / As in the scope of application No. 6 of the patent application, 1 package of n Μ + guides The Bajia 5 hai surface treatment layer combines the solder balls. A method for fabricating a package structure for burying a semiconductor component, comprising: providing a carrier board; combining a heat dissipation plate with a first adhesive layer on the 'Heil carrier board; and supporting frames having opposite first and second frame faces, ^Bei wears the frame of the first and second frame' and the mouth of the frame is bonded to the heat dissipation plate with a second adhesive layer, and the heat dissipation plate of the road portion is formed by the frame; ❹ φ 6 7. 8. 9. Bonding a semiconductor wafer to the heat dissipation plate in the frame, the body wafer has a relative active and non-active surface, the active surface has an electrode, and the semiconductor crystal has the non-active surface Combined with the Π0725 20 200950052 professional board, the first (frame) of the branch (4) is filled with the first dielectric layer = ... 4 layers and the first box of the branch (4) + The core 4 = -, the layer, the branch frame and the semiconductor wafer system - the substrate body has a relative first - soil body, and the first and second frames of the Chi and the second side of the frame "The first layer is formed on the electrical layer; the first guide is formed in the tantalum layer A blind hole, and the second - ❹ which the electrode pad; $ mesh holes for each call to be electrically connected to 有增層結構，且該增層結構表:有及第第二;=:成 連接至該第一線路層；以及 “生 裝板移除該第一黏著層及承載板，以形成一整版面封 1〇.ί=Γ第9項之礙埋半導體元件之封裝結構 、/、中，*玄支撐框係為銅（Cu)。 之:、、:專:圍第9項之嵌埋半導體元件之封裝結構 社/、中承載板係藉由-離型層及該第 教熱板，且該離型層與該第-黏著層位 12.:!d圍第11項之嵌埋半導趙元件之封裝結 板。 移除該離型層、第一黏著層及承載 士申β月專利範圍第9項之嵌埋半導體元件之封裳結構 ]10725 21 200950052 &眾法，復包括移除該散熱板。 U.如申請專利範圍第Θ項之嵌埋丰 之萝，作 人埋+導體兀件之封裝結構 ,裝結構單2切割該整版面封裝板’以形成複數封 15.Π:專=圍第9項之嵌埋半導體元件之封裝結構 * 、、中，該第-線路層之製法，係包括： ' 介電層中形成有複數第-開孔，以對應 頒路各該電極塾； 4 l 〇 於該支稽框上、該第—介電層上、該第一開孔 及忒電極墊上形成有導電層； 於該導電層上形成有阻層 開口區，以顯露部份之導電層；、綱中形成有 於m 口區巾形成有第—線路層，並 孔中形成有第-導電盲孔’俾使 f開 © 16 第一導電盲孔電性連接該電極塾；以&日猎由該 移除該阻層及其所覆蓋之導電層。 =請專利範圍第9項之嵌埋半導體元件 之製法，其中’該增層結構係包 裝：構 層、形成於該第二介電層上之第_線路；弟-介電 於該第二介電層中且電性連接該^二層第^形成 之第二導電盲孔，而最外面之第二線 、、友路層 鱗塾，並於該增層結構上形成有防烊層接 形成有複數開孔以對應顯露各該電性接觸塾μ焊層 如申请專利範圍第】6項之嵌埋半導體元件之封裝結 110725 22 17. 200950052 傅 < 製法，復包括於該電性拉 層。 r接觸墊上形成有表面處理 .I8.如申請專利範圍第Π項之嵌埋半導體 構之製法，其中，該表面處理層蛊 封裴結 . 处理層係為鎳/金（Ni/Α,Λ 錄/▲巴 / 金（Ni/Pd/Au)、銀（Ag)或金（Au)。 u)、 19.如申請專利範圍第17項之嵌埋半導體元件士 構之製法，復包括於該表面處理層上形成焊料球，結There is a build-up structure, and the build-up structure table has: and a second; =: is connected to the first circuit layer; and "the raw plate removes the first adhesive layer and the carrier plate to form a full-page Sealed 1〇. ί=Γ Item 9 of the buried semiconductor component package structure, /, medium, * Xuan support frame is copper (Cu).:,:: special: embedded in the ninth embedded semiconductor components The package structure/the middle carrier plate is formed by the release layer and the first teaching hot plate, and the release layer and the first adhesion layer 12::! The encapsulation of the component is removed. The release layer, the first adhesive layer, and the encapsulation structure of the embedded semiconductor component carrying the ninth patent scope of the patent application] 10725 21 200950052 & public law, including removal The heat dissipating plate. U. As claimed in the patent application, the embedding of Fengzhiluo, as a package structure of a human buried + conductor element, the mounting structure 2 cuts the full-face encapsulating plate to form a plurality of seals. Specifically, the package structure of the buried semiconductor device of the ninth item is the method of manufacturing the first-line layer, which includes: 'The dielectric layer is formed with a plurality of layers - an opening for respectively corresponding to the electrode 塾; 4 l 〇 on the rib, on the first dielectric layer, the first opening and the 忒 electrode pad are formed with a conductive layer; on the conductive layer Forming a resistive opening region to expose a portion of the conductive layer; wherein the m-zone region is formed with a first-line layer, and a first-conductive blind hole is formed in the hole to make f open © 16 A conductive blind via is electrically connected to the electrode 塾; and the resist layer and the conductive layer covered by the resistor layer are removed by the & day hunting. = Please refer to the method of embedding the semiconductor component of the ninth patent, wherein The layer structure is a package: a layer formed on the second dielectric layer; the second dielectric layer is electrically connected to the second dielectric layer and electrically connected to the second layer a hole, and the outermost second line, the friend road layer scale, and the anti-mite layer formed on the layered structure is formed with a plurality of openings to correspondingly expose each of the electrical contacts, such as a patent application Scope of the sixth item of embedded semiconductor components package junction 110725 22 17. 200950052 Fu < recipe, complex The method includes the step of forming a buried semiconductor structure according to the scope of the patent application, wherein the surface treatment layer is 蛊 裴 .. The processing layer is nickel/ Gold (Ni/Α,Λ录/▲巴/金(Ni/Pd/Au), silver (Ag) or gold (Au). u), 19. The embedded semiconductor component structure of claim 17 a method of forming a solder ball on the surface treatment layer 110725 23110725 23
TW097120144A 2008-05-30 2008-05-30 Package structure having semiconductor component embedded therein and fabrication method thereof TWI384606B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI560827B (en) * 2014-09-15 2016-12-01 Siliconware Precision Industries Co Ltd Semiconductor package and its carrier structure and method of manufacture
TWI691041B (en) * 2019-01-29 2020-04-11 矽品精密工業股份有限公司 Electronic package and package substrate thereof and method for manufacturing same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI286372B (en) * 2003-08-13 2007-09-01 Phoenix Prec Technology Corp Semiconductor package substrate with protective metal layer on pads formed thereon and method for fabricating the same
TWI245384B (en) * 2004-12-10 2005-12-11 Phoenix Prec Technology Corp Package structure with embedded chip and method for fabricating the same
TWI279897B (en) * 2005-12-23 2007-04-21 Phoenix Prec Technology Corp Embedded semiconductor chip structure and method for fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI560827B (en) * 2014-09-15 2016-12-01 Siliconware Precision Industries Co Ltd Semiconductor package and its carrier structure and method of manufacture
TWI691041B (en) * 2019-01-29 2020-04-11 矽品精密工業股份有限公司 Electronic package and package substrate thereof and method for manufacturing same

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