200945622,— 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種發光二極體封裝（light_emitting diode package)，且特別是有關於一種具有高發光效率的發光 二極體封裝。 【先前技術】 發光一極體屬於半導體元件’其發光晶片之材料主要為 ❹ 族化學元素，如：磷化鎵(GaP)、砷化鎵(GaAs)等化合物 半導體，其發光原理係將電能轉換為光’也就是對化合物半 導體施加電流，透過電子與電洞的結合，將能量以光的形式 釋出，進而達成發光的效果。由於發光二極體的發光現象不 是藉由加熱發光或放電發光，因此發光二極體的壽命長達十 萬小時以上’且無須暖燈時間(idling time)。此外，發光二極 體更具有反應速度快（約為1〇·9秒）、體積小、用電省、污染低、 咼可靠度、適合量產等優點，所以發光二極體所能應用的領 域十分廣泛，如大型看板、交通號誌燈、手機、掃描器、傳 © 真機之㈣以及照明裝置等。由於發光二極體的發光亮度與 發光效率持續地提昇’同時白光的發光二極體也被成功地量 產所以逐漸有發光一極體被應用在顯示器、照明裝置等產 品中。 目1為習知發光二極體封裝之剖面示意圖。請參照圖卜 曰σ的發光-極體封们〇〇包括—導線架m、—發光二極體 120以及一封裝膠體130。其中’導_ 110的表面ll〇a 為鏡面(spec— SUrface)用以反射發光二極體晶片i2〇所發出 5 200945622— 的光線。發光二極體晶片120配置於導線架11〇上，並與導 線架110電性連接。此外，封聚膠體13〇包覆發光二極體晶 片120以及部分導線架uo,以使部分導線架11〇暴露於封曰 膠體130外，以作為外部電極e。 如圖1所示’封裝膠體13〇係由一外殼132以及一第— 透光部134所構成。外殼132具有一凹陷132a，發光二極體 晶片120位於該凹陷132a内，且凹陷132a具有傾斜程度固定 ❹ 的側壁S。透光部134則配置於凹陷132a中並與外殼132連 接’透光部134包覆發光二極體晶片12〇以及未被外殼ι32 包覆之導線架110的部分區域。 由圖1可清楚得知，雖然表面為鏡面的導線架110對於 光線的反射效果十分良好，但被透光部134包覆的部分導線 架110會將發光二極體晶片12〇所發出的光線反射，且被導 線架110反射後的光線極有可能因為全反射現象而被侷限於 封裝膠體130的透光部134内部’進而造成發光二極體封裝 100的整體發光效率不彰。 ❹ 【發明内容】 本發明提供一種發光二極體封裝，其具有良好的發光效 〇 本發明提出一種發光二極體封裝，其包括一導線架、至 少一發光二極體晶片以及一封裝膠體。其中，導線架具有一 粗糙表面，發光二極體晶片配置於導線架上，並與導線架電 性連接，粗糙表面適於使發光二極體晶片所發出的光線散 射。此外，封裝膠體包覆發光二極體晶片以及部分導線架， 200945622 八*vf_doc/p 以使部分導線架暴露於封裝膠體外。 外 在本發明之-實補巾，上狀導餘包衫個 各個引腳具有-内？I腳以及-外引腳’内引腳被封 覆並與發光電性連接，科引腳暴露於封裝^ 在本發明之-實施例中，上述之各個㈣腳具 粗縫表面。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light-emitting diode package, and more particularly to a light-emitting diode package having high luminous efficiency. [Prior Art] A light-emitting body belongs to a semiconductor element. The material of the light-emitting chip is mainly a bismuth chemical element, such as a compound semiconductor such as gallium phosphide (GaP) or gallium arsenide (GaAs), and the light-emitting principle is to convert electrical energy. For light, that is, applying a current to a compound semiconductor, through the combination of electrons and holes, the energy is released in the form of light, thereby achieving the effect of luminescence. Since the illuminating phenomenon of the illuminating diode does not illuminate by heating or discharging, the life of the illuminating diode is as long as 100,000 hours or more and the idling time is not required. In addition, the light-emitting diode has the advantages of fast reaction speed (about 1 〇·9 seconds), small volume, low power consumption, low pollution, reliability, and mass production, so the light-emitting diode can be applied. The field is very wide, such as large billboards, traffic lights, mobile phones, scanners, transmissions (4) and lighting devices. Since the luminance and the luminous efficiency of the light-emitting diode are continuously increased, and the light-emitting diode of the white light is also successfully mass-produced, the light-emitting diode is gradually applied to products such as displays and illumination devices. 1 is a schematic cross-sectional view of a conventional light-emitting diode package. Please refer to the illuminating-polar body package of Fig. 曰σ, including the lead frame m, the light emitting diode 120 and an encapsulant 130. The surface 〇 〇 a of the _ 110 is a spec-surface for reflecting the light emitted by the LED chip i2 5 5 200945622. The LED chip 120 is disposed on the lead frame 11 and electrically connected to the lead frame 110. In addition, the encapsulating colloid 13 encases the LED dipole 120 and a portion of the lead frame uo so that a portion of the lead frame 11 is exposed to the outside of the encapsulant 130 as the external electrode e. As shown in Fig. 1, the encapsulant 13 is composed of a casing 132 and a first light transmitting portion 134. The outer casing 132 has a recess 132a in which the light emitting diode wafer 120 is located, and the recess 132a has a side wall S with a fixed inclination ❹. The light transmitting portion 134 is disposed in the recess 132a and connected to the outer casing 132. The light transmitting portion 134 covers the light emitting diode wafer 12A and a partial region of the lead frame 110 not covered by the outer casing ι32. It can be clearly seen from FIG. 1 that although the mirror frame 110 has a very good reflection effect on light, a part of the lead frame 110 covered by the light transmitting portion 134 will emit light from the LED chip 12 The light reflected and reflected by the lead frame 110 is highly likely to be confined to the inside of the light transmitting portion 134 of the encapsulant 130 due to the phenomenon of total reflection, thereby causing the overall luminous efficiency of the LED package 100 to be inconsistent. SUMMARY OF THE INVENTION The present invention provides a light emitting diode package having good light emitting efficiency. The present invention provides a light emitting diode package including a lead frame, at least one light emitting diode chip, and an encapsulant. The lead frame has a rough surface, and the LED array is disposed on the lead frame and electrically connected to the lead frame. The rough surface is adapted to scatter light emitted by the LED chip. In addition, the encapsulant encapsulates the LED chip and a portion of the lead frame, which is used to expose a portion of the lead frame to the outside of the encapsulant. In addition, the present invention is a solid-filled towel, and the upper-shaped guide blanket has a pin-in-one? The I pin and the - outer pin 'inner pin are encapsulated and electrically connected to the light emitting, and the pin is exposed to the package. In the embodiment of the present invention, each of the above (4) legs has a rough surface.
在本發明之-實施例中，上述之各個内引腳與各 腳具有前述之粗縫表面。 在本發明之-實施例中’上述之各個外引腳從封裝膠 的侧壁延伸至封裝膠體的底部。 / 在本發明之一實施例中，上述之封裝膠體包括一外殼以 及一透光部。其中，外殼具有一凹陷，且發光二極體晶片位 於凹陷内。透光部配置於凹陷中並與外殼連接，且透光部包 覆發光二極體晶片以及未被外殼包覆之内引腳的部分區域。 ❹ 在本發明之一實施例中，上述之被透光部包覆之内引腳 的部分區域具有前述之粗糙表面。 在本發明之一實施例中，上述之被外殼包覆之内引腳的 部分區域具有前述之粗縫表面。 在本發明之一實施例中，上述之粗糙表面的粗糙度介於 0.05微米至500微米之間。 、 由於本發明採用具有散射表面的導線架作為晶片承載器 (chip Carrier)，因此，本發明之發光二極體封裝具有良好的發 光效率。 7 200945622一 為讓本發明之上述和其他目的、特徵和優點能更明顯易 懂’下文特舉較佳實施例，並配合所附圖式，作詳細說明如 下。 【實施方式】 【第一實施例】 圖2與圖3為本發明第一實施例之發光二極體封裝之剖 面示意圖。請參照圖2與圖3，本實施例之發光二極體封裳 ❹ 200包括一導線架210、至少一個發光二極體晶片220以及— 封裝膠體230。其中，導線架2ί〇具有一粗糙表面210a，發光 二極體晶片220配置於導線架210上，並與導線架210電性 連接。在本實施例中，發光二極體晶片220例如是透過焊線 (bonding wire)240與導線架210電性連接，當然，發光二極體 晶片220亦可以透過覆晶技術(f|ip_chip technology)或是其他 晶粒接合製程(die-bonding processes)達成電性連接之目的。封 裝膠體230包覆發光二極體晶片220以及部分導線架21〇,以 使部分導線架210暴露於封裝膠體230外。此外，粗糖表面 © 210a適於使發光二極體晶片22〇所發出的光線散射，而在本 實施例中，粗糙表面的粗糙度例如是介於〇 〇5微米至5〇〇微 米之間。 如圖2與圖3所示，導線架21〇包括多個引腳L，各個引 腳L具有-内引腳IL以及-外引腳〇L，内引腳^被封裝膠 體230包覆並與發光二極體晶片22〇電性連接，而外引腳沉 暴露於封裝膠體230外，且各個外引腳〇L例如是從封裝膠體 23〇的侧壁延伸至封裝膠體23〇的底部。在本實施例中，導線 8 wf.doc/p 200945622 架210例如是銅導線架、鋁導線架等金屬材質之導線架，當 然本實施例亦可根據實際需求在導線架23〇上鍍上一金屬鍍 層(metal coatings)。此外，本發明所採用的導線架21〇不限定 於圖2與圖3中所繪示出的型態，換言之，導線架21〇可根 據實際設計需求而採用上置(Up_set)設計或下沈設計（d own set)，意即，被封裝膠體230所包覆的内引腳正與外引腳〇L 可分別位在不同平面上。 〇 值得注意的是，製造者可在導線架210上的不同部位形 成粗糙表面21〇a，而在導線架21〇的不同部位上形成粗糙表 面210a，將可帶來不同的功效（將詳述於後）。舉例而言， 製造者可以在各個内引腳正上形成粗糙表面21〇a(如圖2所 繪示），當然，製造者亦可在内引腳IL以及外引腳〇L上同 時形成粗链表面210a (如圖3所續'示）。 當製造者在導線架210的外引腳〇l上形成粗糙表面 210a時，此粗糙表面2l〇a將有助於發光二極體封裝2〇〇與其 他承載器（如電路板）之間的連接。當製造者在導線架210 ® 的内引腳11上形成粗糙表面210a時，此粗糙表面21〇a將有 助於導線架210本身與封裝膠體23〇之間的接合強度，使導 線架210與封裝膠體23〇之間不容易有脫層的現象 (de-lamination)發生。 承上述，圖2與圖3雖僅繪示出導線架210的單一表面 為粗糙表面210a的情況，但本發明並不排除導線架21〇的二 相對表面皆為粗糖表面；2i〇a之可能性。 在本發明之一較佳實施例中，封裝膠體23〇包括一外殼 9 200945622 fd , 3twr.doc/p 232以及一透光部234。其中，外殼232具有一凹陷232a，且 發光二極體晶片22〇位於凹陷咖内。透光部234配置於凹 232a中並與外殼232連接，且透光部234包覆發光二極體 晶片220以及未被外殼232包覆之内引腳乩的部分區域。 在内引腳IL的不同部位上形成粗糙表面21〇a同樣會帶 來不同的功效，將詳述如下。當製造者在内引腳IL的A區域 上形成粗糙表面21〇a時，此粗糙表面21〇a將有助於導線架 ❹ 210與發光一極體晶片220之間的接合強度；當製造者在内引 腳IL的B區域上形成粗糙表面21〇&時，此粗糙表面以⑽將 有助於導線架210與透光部234之間的接合強度；當製造者 在内引腳IL的C區域上形成粗糙表面210a時，此粗糙表面 21〇a將有助於導線架21〇與外殼232之間的接合強度。 值得注意的是，製造者可選擇性地在A區域、B區域或 C區域上形成粗糙表面21〇a’當然，製造者亦可在A區域、B 區域與c區域中的至少兩個區域上形成粗糖表面21〇a。 【第二實施例】 ® 圖4為本發明第二實施例之發光二極體封裝之剖面示意 圖。請參照圖4，本實施例之發光二極體封裝2〇〇,包括一導線 架210、至少一個發光二極體晶片220以及一封裝膠體23〇。 其中，發光二極體晶片220配置於導線架21〇上並與導線架 210電性連接。在本實施例中，發光二極體晶片22〇例如是透 過焊線(bonding wire)240與導線架210電性連接，當然，發光 =極體晶片220亦可以透過覆晶技術(flip_chip techn〇1〇gyX)或 疋其他晶粒接合製程(die-bonding processes)達成電性連接之 200945622—p 目的。封裝膠體230包覆發光二極體晶片22()以及部分導線 架230 ’以使部分導線架21〇暴露於封裝膠體23〇外。此外， 封裝膠體230包括一外殼232以及一第一透光部234。外殼具 有一第一凹陷232a’而發光二極體晶片22〇位於第一凹陷232& 内，且第一凹陷232a具有多段傾斜程度不同的侧壁8卜S2。 第一透光部234配置於第一凹陷232a中並與外殼232連接， 而第一透光部234包覆發光二極體晶片22〇以及未被外殼232 Ο 包覆之導線架210的部分區域。 如圖4所示’導線架21〇包括多個引腳L，各個引腳l 具有y内引腳IL以及—外引腳〇L’内引腳IL被封裝膠體23〇 包覆並與發光二極體晶片220電性連接，而外引腳〇L暴露於 封裝膠體230外，且各個外引腳〇L例如是從封裝膠體23〇的 側壁延伸至封裝膠體230的底部。在本實施例中，導線架 例如是銅導線架、鋁導線架等金屬材質之導線架，當然本實 施例亦可根據實際需求在導線架230上鍍上一金屬鍍層(metal coatings)。此外，本發明所採用的導線架21〇不限定於圖4中 © 麟示出的型態，換言之，導線架21〇可根據實際設計需求 而採用上置(up-set)設計或下沈設計(d〇wnset)，意即，被封裝 膠體230所包覆的内引腳冚與外引腳〇L可分別位在不同平 面上。 值得注意的是，製造者可在導線架210選擇性地形成一 粗糙表面210a，此粗糙表面210a適於使發光二極體晶片220 所發出的光線散射，而粗糙表面的粗糖度例如是介於〇 微 米至500微米之間》在本實施例中，製造者可在導線架2w 200945622— 上的不同部位形成粗糙表面21〇a，而在導線架210的不同部 位上形成粗糙表面210a，將可帶來不同的功效（將詳述^ 後）。舉例而言，製造者可以僅在各個内引腳IL上形成粗糙 表面210a，當然，製造者亦可在内引腳IL以及外引腳〇1^上 同時形成粗糙表面210a (如圖4所繪示）。 當製造者在導線架210的外引腳OL上形成粗糙表面 21〇a時，此粗糙表面21〇a將有助於發光二極體封裝2〇〇，與 〇 其他承載器（如電路板）之間的連接。當製造者在導線架以〇 的内引腳IL上形成粗糙表面21〇a時，此粗糙表面21〇a將有 助於導線架210本身與封裝膠體230之間的接合強度，使導 線架210與封裝膠體23〇之間不容易有脫層的現象 (de-lamination)發生。 承上述，圖4雖僅繪示出導線架21〇的單一表面為粗糙 表面21〇a的情況，但本發明並不排除導線架21〇的二相對表 面皆為粗糙表面210a之可能性。 在内引腳1L的不同部位上形成粗糙表面210a同樣會帶 來不同的功效，將詳述如下。當製造者在内引腳IL的A區域 上形成粗糙表面210a時，此粗糙表面2l〇a將有助於導線架 21〇與發光二極體晶片220之間的接合強度；當製造者在内引 腳IL的B區域上形成粗糙表面210a時，此粗糙表面以如將 有助於導線架210與透光部234之間的接合強度；當製造者 在内引腳IL的C區域上形成粗糙表面21〇a時，此粗糙表面 21〇a將有助於導線架210與外殼232之間的接合強度。 值得注意的是，製造者可選擇性地在A區域、B區域或 12 200945622 … HWi.doc/p c區域上形成粗糙表面21〇a，當然，製造者亦可在A區域、B 區域與c區域中的至少兩個區域上形成粗糙表面21〇a。 【第三實施例】 圖5為本發明第三實施例之發光二極體封裝之剖面示意 ，，而圖6A至圖6D為第三實施例中外殼與導線架的立體^ 意圖。請參照圖5，本實施例之發光二極體封裝3〇〇與第二實 施例之發光二極體封裝200’相似，惟二者主要差異之處在於： ❹本實施例之發光二極體封裝300可進一步包括一第二透光部 236，而外殼232更具有一第二凹陷232b以容納一電子元件 250以及第一透光部236 (如圖6A至圖6D所緣示），第二透 光吾P 236配置於第二凹陷232b中並與外殼232連接，而第二 ，光部2326包覆電子元件25〇以及未被外殼232包覆之導線 架210的部分區域。由圖5可清楚得知，第一透光部234與 第二透光部236分別位於導線架21〇的兩對側。此外，第一 凹陷232a的尺寸例如是大於第二凹陷232b的尺寸。值得注意 鲁=是，電子元件250例如是一發光二極體晶片、一靜電防護 曰曰片、一控制晶片或是其他型態的晶片。 綜上所述’本發明至少具有下列優點： 丨.由於本發明採用具有散射表面的導線架作為晶片承載 态，因此，設計者可以在不大幅增加製造成本的前提下製造 出發光效率較高的發光二極體封裝。 2.由於本發明之外殼具有第一凹陷，且第一凹陷具有多段 傾斜程度不同的侧壁，因此，本發明之發光二極體封裝具有 良好的發光效率。 13 200945622 … nwi.doc/p 雖然本發明已啸佳實補揭露如上，然其並非用 定本發明，任何熟習此技藝者，在不脫離本發明之精神和^ 圍内’當可作些許之更動與潤飾，因此本發明之保護範圍= 視後附之申請專利範圍所界定者為準。 田 【圖式簡單說明】 圖1為習知發光二極體封裝之剖面示意圖。 圖2與圖3為本發明第一實施例之發光二極體封裳之剖 ❹ 面示意圖。 圖4為本發明第二實施例之發光二極體封裝之剖面示音 圖。 圖5為本發明第三實施例之發光二極體封裝之剖面示意 圖。 圖6A至圖6D為第三實施例中外殼與導線架的立體示意 圖。 【主要元件符號說明】 100 :發光二極體封裝 ❹ 110:導線架 110a :鏡面表面 120 :發光二極體晶片 130 :封裝膠體 132 :外殼 132a :凹陷 134 :透光部 E:外部電極 200945622— s :側壁 200、200’、300 :發光二極體封裝 210 :導線架 210a :粗糙表面 220 :發光二極體晶片 230 :封裝膠體 232 :外殼 ▲ 232a :第一凹陷 232b :第二凹陷 234 :第一透光部 236 :第二透光部 240 :焊線 250 :電子元件 A、B、C :區域 L :引腳 IL :内引腳 G OL :外引腳 S卜S2 :侧壁 15In the embodiment of the invention, each of the inner pins and the legs has the aforementioned rough surface. In the embodiment of the invention - each of the outer pins described above extends from the sidewall of the encapsulant to the bottom of the encapsulant. / In an embodiment of the invention, the encapsulant comprises an outer casing and a light transmitting portion. Wherein, the outer casing has a recess and the light emitting diode chip is located in the recess. The light transmitting portion is disposed in the recess and connected to the outer casing, and the light transmitting portion covers the light emitting diode chip and a partial region of the inner pin not covered by the outer casing. In one embodiment of the invention, the partial region of the inner lead covered by the light transmitting portion has the aforementioned rough surface. In an embodiment of the invention, the partial region of the inner lead covered by the outer casing has the aforementioned rough surface. In an embodiment of the invention, the roughness of the rough surface is between 0.05 microns and 500 microns. Since the present invention employs a lead frame having a scattering surface as a chip carrier, the light emitting diode package of the present invention has good light emitting efficiency. The above and other objects, features, and advantages of the present invention will become more apparent and understood. [Embodiment] FIG. 2 and FIG. 3 are schematic cross-sectional views showing a light emitting diode package according to a first embodiment of the present invention. Referring to FIG. 2 and FIG. 3, the LED package 200 of the present embodiment includes a lead frame 210, at least one LED chip 220, and an encapsulant 230. The lead frame 2 has a rough surface 210a. The LED chip 220 is disposed on the lead frame 210 and electrically connected to the lead frame 210. In this embodiment, the LED chip 220 is electrically connected to the lead frame 210 through a bonding wire 240. Of course, the LED chip 220 can also pass the flip chip technology (f|ip_chip technology). Or other die-bonding processes for electrical connection. The encapsulant 320 encloses the LED chip 220 and a portion of the lead frame 21A to expose a portion of the lead frame 210 to the outside of the encapsulant 230. Further, the raw sugar surface © 210a is adapted to scatter light emitted from the light-emitting diode wafer 22, and in the present embodiment, the roughness of the rough surface is, for example, between 5 μm and 5 μm. As shown in FIG. 2 and FIG. 3, the lead frame 21A includes a plurality of pins L, and each of the pins L has an inner pin IL and an outer pin 〇L, and the inner pin ^ is covered by the encapsulant colloid 230 and The light emitting diode chip 22 is electrically connected, and the outer lead sink is exposed outside the encapsulant 230, and each of the outer leads 例如L extends from the sidewall of the encapsulant 23〇 to the bottom of the encapsulant 23〇, for example. In the present embodiment, the wire 8 wf.doc/p 200945622 frame 210 is, for example, a lead frame made of a metal material such as a copper lead frame or an aluminum lead frame. Of course, the present embodiment can also be plated on the lead frame 23〇 according to actual needs. Metal coatings. In addition, the lead frame 21 used in the present invention is not limited to the type illustrated in FIG. 2 and FIG. 3, in other words, the lead frame 21 can be designed with an Up_set or sink according to actual design requirements. The d own set means that the inner pin and the outer pin 〇L covered by the encapsulation colloid 230 can be respectively located on different planes. It is worth noting that the manufacturer can form a rough surface 21〇a at different portions of the lead frame 210, and forming a rough surface 210a on different portions of the lead frame 21〇, which will bring different effects (described in detail) After). For example, the manufacturer can form a rough surface 21〇a (shown in FIG. 2) directly on each inner pin. Of course, the manufacturer can also form a thick joint on the inner lead IL and the outer lead 〇L at the same time. Chain surface 210a (shown in Figure 3). When the manufacturer forms a rough surface 210a on the outer lead 〇1 of the lead frame 210, the rough surface 21a will contribute to the light-emitting diode package 2 〇〇 between the other carrier (such as a circuit board) connection. When the manufacturer forms a rough surface 210a on the inner lead 11 of the lead frame 210®, the rough surface 21〇a will contribute to the joint strength between the lead frame 210 itself and the encapsulant 23〇, so that the lead frame 210 and De-lamination does not easily occur between the encapsulants 23 〇. 2 and FIG. 3, although only a single surface of the lead frame 210 is shown as a rough surface 210a, the present invention does not exclude that the opposite surfaces of the lead frame 21 are both rough surfaces; the possibility of 2i〇a Sex. In a preferred embodiment of the present invention, the encapsulant 23 includes a housing 9 200945622 fd , 3twr.doc/p 232 and a light transmitting portion 234. Wherein, the outer casing 232 has a recess 232a, and the light emitting diode chip 22 is located in the recessed coffee. The light transmitting portion 234 is disposed in the recess 232a and connected to the outer casing 232, and the light transmitting portion 234 covers the light emitting diode wafer 220 and a partial region of the inner lead which is not covered by the outer casing 232. The formation of a rough surface 21〇a on different portions of the inner lead IL also has different effects, as will be described in detail below. When the manufacturer forms a rough surface 21〇a on the A region of the inner lead IL, the rough surface 21〇a will contribute to the bonding strength between the lead frame 210 and the light-emitting one-pole wafer 220; when the manufacturer When a rough surface 21〇& is formed on the B region of the inner lead IL, this rough surface will contribute to the bonding strength between the lead frame 210 and the light transmitting portion 234 at the (10); when the manufacturer is in the inner lead IL When the rough surface 210a is formed on the C region, the rough surface 21〇a will contribute to the joint strength between the lead frame 21〇 and the outer casing 232. It is worth noting that the manufacturer can selectively form a rough surface 21〇a' on the A region, the B region or the C region. Of course, the manufacturer can also be on at least two of the A region, the B region and the c region. The surface of the raw sugar 21a is formed. [Second Embodiment] Fig. 4 is a schematic cross-sectional view showing a light emitting diode package according to a second embodiment of the present invention. Referring to FIG. 4, the LED package of the present embodiment includes a lead frame 210, at least one LED chip 220, and an encapsulant 23A. The LED chip 220 is disposed on the lead frame 21A and electrically connected to the lead frame 210. In this embodiment, the LED chip 22 is electrically connected to the lead frame 210 through a bonding wire 240. Of course, the light-emitting body plate 220 can also pass through the flip chip technology (flip_chip techn〇1). 〇 gyX) or other die-bonding processes to achieve the electrical connection of the 200945622-p purpose. The encapsulant 230 encloses the LED wafer 22 () and a portion of the lead frame 230' to expose portions of the leadframe 21A to the encapsulant 23. In addition, the encapsulant 230 includes a housing 232 and a first light transmitting portion 234. The outer casing has a first recess 232a' and the light-emitting diode wafer 22 is located in the first recess 232 & and the first recess 232a has a plurality of side walls 8 S2 having different degrees of inclination. The first light transmitting portion 234 is disposed in the first recess 232a and connected to the outer casing 232, and the first light transmitting portion 234 covers the light emitting diode wafer 22 and a portion of the lead frame 210 not covered by the outer casing 232 . As shown in FIG. 4, the lead frame 21 includes a plurality of pins L, each of which has a y inner pin IL and an outer pin 〇L'. The inner lead IL is covered by the encapsulant 23 并 and emits light. The polar body wafers 220 are electrically connected, and the outer leads 〇L are exposed outside the encapsulant 230, and the respective outer leads 例如L extend from the sidewalls of the encapsulant 23〇 to the bottom of the encapsulant 230, for example. In this embodiment, the lead frame is, for example, a lead frame made of a metal such as a copper lead frame or an aluminum lead frame. Of course, the present embodiment can also be plated with a metal coating on the lead frame 230 according to actual needs. In addition, the lead frame 21 used in the present invention is not limited to the type shown in FIG. 4, in other words, the lead frame 21 can be designed with an up-set design or a sinking design according to actual design requirements. (d〇wnset), that is, the inner pin 冚 and the outer pin 〇L covered by the encapsulation colloid 230 can be respectively located on different planes. It should be noted that the manufacturer can selectively form a rough surface 210a on the lead frame 210, and the rough surface 210a is adapted to scatter light emitted by the LED wafer 220, and the roughness of the rough surface is, for example, Between 微米 and 500 μm ” In this embodiment, the manufacturer may form a rough surface 21〇a at different portions on the lead frame 2w 200945622, and a rough surface 210a may be formed on different portions of the lead frame 210. Bring different effects (will be detailed ^). For example, the manufacturer may form the rough surface 210a only on each inner lead IL. Of course, the manufacturer may simultaneously form the rough surface 210a on the inner lead IL and the outer lead 〇1^ (as shown in FIG. 4). Show). When the manufacturer forms a rough surface 21〇a on the outer lead OL of the lead frame 210, the rough surface 21〇a will contribute to the light-emitting diode package 2〇〇, and other carriers (such as a circuit board) the connection between. When the manufacturer forms a rough surface 21〇a on the inner lead IL of the lead frame, the rough surface 21〇a will contribute to the joint strength between the lead frame 210 itself and the encapsulant 230, so that the lead frame 210 De-lamination does not easily occur with the encapsulant 23〇. In view of the above, although Fig. 4 only shows the case where the single surface of the lead frame 21 is a rough surface 21a, the present invention does not exclude the possibility that the two opposite surfaces of the lead frame 21 are both rough surfaces 210a. Forming the rough surface 210a on different portions of the inner lead 1L also has different effects, as will be described in detail below. When the manufacturer forms the rough surface 210a on the A region of the inner lead IL, the rough surface 21a will contribute to the bonding strength between the lead frame 21 and the light emitting diode wafer 220; When the rough surface 210a is formed on the B region of the pin IL, the rough surface will, for example, contribute to the bonding strength between the lead frame 210 and the light transmitting portion 234; when the manufacturer forms a roughness on the C region of the inner pin IL This rough surface 21〇a will contribute to the joint strength between the lead frame 210 and the outer casing 232 when the surface 21〇a. It is worth noting that the manufacturer can selectively form a rough surface 21〇a in the A region, the B region, or the 12200945622 ... HWi.doc/pc region. Of course, the manufacturer can also be in the A region, the B region, and the c region. A rough surface 21〇a is formed on at least two of the regions. [THIRD EMBODIMENT] Fig. 5 is a cross-sectional view showing a light emitting diode package according to a third embodiment of the present invention, and Figs. 6A to 6D are perspective views of a case and a lead frame in the third embodiment. Referring to FIG. 5, the LED package 3A of the present embodiment is similar to the LED package 200' of the second embodiment, but the main differences are as follows: 发光 The LED of the embodiment The package 300 may further include a second light transmitting portion 236, and the outer casing 232 further has a second recess 232b for accommodating an electronic component 250 and the first light transmitting portion 236 (as shown in FIGS. 6A to 6D). The light transmissive P 236 is disposed in the second recess 232b and connected to the outer casing 232, and secondly, the light portion 2326 covers the electronic component 25A and a partial region of the lead frame 210 not covered by the outer casing 232. As is clear from Fig. 5, the first light transmitting portion 234 and the second light transmitting portion 236 are respectively located on opposite sides of the lead frame 21A. Further, the size of the first recess 232a is, for example, larger than the size of the second recess 232b. It is worth noting that the electronic component 250 is, for example, a light emitting diode chip, an electrostatic protection cymbal, a control wafer or other type of wafer. In summary, the present invention has at least the following advantages: 丨. Since the present invention employs a lead frame having a scattering surface as a wafer bearing state, the designer can manufacture a luminous efficiency without greatly increasing the manufacturing cost. Light-emitting diode package. 2. Since the outer casing of the present invention has a first recess and the first recess has a plurality of side walls having different degrees of inclination, the light emitting diode package of the present invention has good luminous efficiency. 13 200945622 ... nwi.doc/p Although the present invention has been disclosed above, it is not intended to be exhaustive, and any person skilled in the art can make some changes without departing from the spirit and scope of the present invention. And the scope of protection of the present invention is defined by the scope of the appended claims. [Simplified illustration of the drawings] Fig. 1 is a schematic cross-sectional view of a conventional light-emitting diode package. 2 and 3 are schematic cross-sectional views showing the light-emitting diode of the first embodiment of the present invention. Fig. 4 is a cross-sectional view showing a light emitting diode package in accordance with a second embodiment of the present invention. Figure 5 is a cross-sectional view showing a light emitting diode package in accordance with a third embodiment of the present invention. 6A to 6D are perspective views of the outer casing and the lead frame in the third embodiment. [Main component symbol description] 100: Light-emitting diode package ❹ 110: Lead frame 110a: Mirror surface 120: Light-emitting diode wafer 130: Package colloid 132: Housing 132a: recess 134: Light-transmitting portion E: External electrode 200945622 - s: side wall 200, 200', 300: light emitting diode package 210: lead frame 210a: rough surface 220: light emitting diode wafer 230: encapsulant 232: outer casing ▲ 232a: first recess 232b: second recess 234: First light transmitting portion 236: second light transmitting portion 240: bonding wire 250: electronic component A, B, C: region L: pin IL: inner pin G OL: outer pin Sb S2: side wall 15