200930200 •九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體製程技術，更詳而古之 尤指一種電路板及其製法。 【先前技術】 &隨著電子產業的蓬勃發展’電子產品亦逐漸邁入多功 能、高性能的方向研發。為滿足半導體封裝件高積集度 (Integration)以及微型化的封裝需求，提供多數:二 ❾被動元件及線路載接之電路板，亦逐漸由單層板演變成多 層板，俾於有限的空間下，藉由層間連接技術擴大電路板 上可利用的電路面積以因應高電子密度之積體電路之使 用需求。為提高電路板之佈線精密度，業界發展出一種增 層技術（Bui Id-up)，亦即在-核心板表面利用線路增層^ 術交互形成複數介電層及線路層，並於該介電層中形成有 複數導電結構’如導電盲孔（c〇nductivevia)及電鐘導通 through hole，PTH)以供上下層線路之間的 電性連接。 '請參閱帛1A圖至U圖，係為習知核心電路板以電鑛 法（Pattern process)形成線路及電鍍導通孔（ρτΗ)之制 法；如第u圖所*，首先，提供一具有二表面1〇&之= 。板10,且於該核心板10之表面1〇&上形成有第一金屬 層11;如第1B圖所示，對該第一金屬層u進行薄化製 程，以成為薄化金屬層11，；如第lc圖所示，於該核心 板10及其表面10a之薄化金屬層u，形成至少一通孔 110669 5 200930200 ，1 〇 1;如第1D圖所+ .. _ ^ .中之表面上妒= 缚化金屬層1Γ上及通孔叫 -=2上二電層12;如第1E圖所示，接著，於該 等電層12上形成阻層13，且令該阻層 開口 13。以露出部份之導電層12 :成有阻層 阻層開口 130中之導” 19 κ F圖所不’於該 14;如第ig圖所-包曰 书鍍形成有第二金屬層 電芦12 f 不’之後移除該阻層13及其所覆蓋之導 線^ 15錢金屬層U’ ’以形成具有複數線路⑸之 β 圖 於該通孔1〇1中形成電鍍導通孔152.如第 ❹〗Η圖所示，於該電鐘導通孔152 如第 料16，以槪& 4试 泉〒真入有塞孔材 續論㈣程巾產生 ::::::高於該線路層15之上表面，二應若:： 材料16的曰位置線路時，會因介電層相對於塞孔 線路亦隨致使設置於介電層表面之增層 增層線路整’而影響其電性或可靠度；為避免前述 〇 SI::之問題，必須如第”圖所示，進行刷磨 該線路層15之上表面之塞孔㈣16， 使1孔材料16之外露表面與線路層15之上表面齊平。 進行刷磨製程以移除高於該線路層 ::::r時導r路層15之整體結構丄: 導電曰12與以電鍍製程所構成的第二金 細:線敗故線路層15之整體結構厚度較薄，雖可形成較 L間距，惟其厚度較薄，故於刷磨製程中該線路層 <之部份線路151極易被移除（如第u圖所示），導致已 、、泉路151被移除破壞，如此即無法再進行後續製 110669 6 200930200 •程。 因此，如何提出一種電路板 >仿、、此击板及I法，以避免習知技術 路層’而在該電鑛導通孔中埴人Μ Mu兩側之'線 由塞孔材料進行刷磨製程 中=易^致線路被刷磨移除之缺失，實已成爲 亟待克服之課題。 【發明内容】 βπ 之缺點，本發明之主要目的在於提 ❹供一種電路板及其製法，能免除電料通孔中填入之塞孔 材料於進行刷磨製程中導致線路被刷磨移除之缺失。 為達上述及其他目的，本發明提供一種電路板，係包 括：核心板，係具有相對應之二表面，並具有至少一貫穿 該一表面之通孔，第一線路層，係設於該核心板之表面 上，並具有複數線路；電鍍導通孔，係設於該通孔中以電 性連接該核心板二表面上之第一線路層，且於該電錢導通 ❹孔中填入有塞孔材料，該塞孔材料與第一線路層齊平；以 及填充層，係設於該核心板表面上之第一線路層的線路之 間，並與該第一線路層齊平。 依上述結構’該核心板係為絕緣板或内部具有核心線 路層之線路板；該第一線路層係由薄化金屬層、導電層及 第一金屬層組成。 又依上述結構，復包括線路增層結構，係設於該填充 層與第一線路層上，該線路增層結構包括有至少一介電 層、疊置於該介電層上之第二線路層，以及形成於該介電 110669 7 200930200 * 層中並電性連接該第一 τα , 弟及第一線路層之導電盲孔，且於嗲 :結構^具有複數電性連接該第二線路層之Ϊ ，又於錢路增層結構上形成絕緣保護層，心 護層形成有複數個開孔以對應露出該電性連接塾/巴 本發明復提供-種電路板之製法，係包括：提供 ^ :應二表面之核心板，且該核心板並具有至少：貫； 〇接該核心板二表面上之第一線路成層有==電性連 之第-線路層料路之㈣ 面上 孔中填入有塞孔材料；以及進编亥電鍍導通 與第-線路層齊平。及進仃刷磨製程，使該塞孔材料 依上述之製法’該核心板係為絕緣 線路層之線路板之其中一者；該填充声。具有核心 成於該第-線路層的線路之間。、θ糸以網版印刷形 G 該第一線路層之製法，係包括：於該 具有第一金屬層，並薄化該第一 板之二表面 戶·；^兮妨4 Μ 屬層以成為薄化今麗 層，於该核心板及其表面之薄化金屬層 巧身化金屬 該薄化金屬層上及通孔中之表面上形成導^通孔，並於 電層上形成阻層，且該阻層中形成有阻層開％層’於該導 之導電層；於該阻層開口中之導 汗口以露出部份 屬層；以及移除該阻層及其所覆蓋之：：形成第二金 層’以露出該具有複數線路之第 $層及薄化金屬 路層係由該薄化金屬層、導電層；成：：該第 '線 屯成之第二金屬層 130669 8 200930200 .組成，故第-線路層之整體結構厚度較薄 -之線路間距。 杈，·、田 該電路板之製法復包括於該填充層與第―線路層上 形成線路增層結構，該線路增層結構係包括有至少一 層、疊置於該介電層上之第-綠,々a 昆山 急弟一線路層，以及形成於該介電 y並電性連接該第一及第二線路層之導電盲孔，且於該 線路增層結構表面具有複數電性連接該第二線路層之;; =連接墊，又於該料增層結構切錢緣料層 〇、，象保護層形成有複數個開孔以對應露出該電性連接塾。、， 電二二本發明之電路板及其製法’係於核心板表面以 電鍍法形成細間距的第一線路声， 再弟一線路層的線路 2間先明㈣刷形成填充層，並於該電料通孔中填入 m’然後進行刷磨製程，以將凸出於該路 塞孔材料及填充層移除，故可保護該細間距的第一 〇 塞孔材料、該填充層與該第—線中被移除’使該 距的第-線路層。線路層齊平，並保護該細間 【實施方式】 以下係藉由特定的|體者 式，熟悉此技藝之人士可由、本二::所:本㈣^ 瞭解本發明之其他優點與功所^之内容輕易地. 請參閲第以至21(圖，係為本發 其製法的剖視示意圖。 W路之電路板及 如第2A圖所示’提供一具有相對二表面·之核心 110669 9 200930200 *板20，該核心板20係為絕緣板或内部具有核心線路層之 .線路板，於本實施令以核心板2〇係為絕緣板作說明，且 於該核心板20之表面2〇a具有第一金屬層21。 如第2B圖所示，該第一金屬層21進行薄化製程以成 為薄化金屬層21 ’。 如第2C圖所示，接著，該核心板2〇及其表面2〇a 之薄化金屬層21，形成至少一通孔2〇1。 如第2D圖所示，之後，於該薄化金屬層21，上及通 ©孔201中之表面上形成有導電層22,其中該導電層22主 要係作爲後續電鍍金屬材料所需之電流傳導路徑，其可由 金屬、合金或沉積數層金屬層所構成，如選自銅、錫、鎳、 鉻、鈦、銅-鉻合金或錫-鉛合金等所構成之群組之其中一 者所組成，係以濺鍍、蒸鍍、無電電鍍及化學沈積之一者 形成；或可使用例如聚乙炔、聚苯胺或有機硫聚合物等導 電高分子材料，而以旋轉塗佈（spinc〇ating)、噴墨印 ❹刷（ink-jetprinting)或壓印（imprinting)等方式形 成該導電層22。 乂 如第2E圖所示，於該導電層22上形成有阻層23， 該阻層23係為一例如乾膜或液態光阻等光阻層 (Photoresi st)，其係利用印刷、旋塗或貼合等方式分別 形成於該導電層22上’再藉由曝光、顯影等方式加以圖 案化’於該阻層23中形成阻層開口 23〇，以露出部份之 導電層22。 乃 如第2F圖所示，然後於該阻層開口 23〇中之導電層 110669 10 200930200 * 22上電錢形成有第二金屬層24。 如第2G圖所示，接著移除該阻層23及其所覆蓋之導 二層22及薄化金屬層21，’以形成具有複數線路25丨之 第一線路層25,並於該通孔2〇1中形成有電鍍導通孔252 以電性連接該核心板2〇之二表面2〇a上之第一線路層 25，使§亥第一線路層25係由該薄化金屬層2〗，、導電層 22與電鍍形成之第二金屬層24組成，故該第一線路層μ 之整體結構厚度較薄，並能形成較細之線路間距。 〇 如第2H圖所示，於該核心板表面2〇&上之第一線路 層25的線路251之間以網板印刷形成有填充層26，該填 充層26係可為具環狀化合物之高分子樹脂。 如第21圖所示，於該電鍍導通孔252中填入有塞孔 材料27。 、土 如第2J圖所示，之後，進行刷磨製程，藉由該填充 層26’俾可保護該線路251，以避免該線路251於刷磨製 ❹程中被移除，並使該塞孔材料27與第一線路層託齊平： 且使該填充層26並與該第一線路層25齊平。 如第2K圖所示，後續復可於該填充層26與第一線路 層25上形成有線路增層結構28，該線路增層結構28包 括有至少-介電層28卜疊置於該介電層上之第二線路層 282’以及形成於該介電層中並電性連接該第一線路層託 及第二線路層282之導電盲孔283,且於該線路增層結構 28表面具有複數電性連接該第二線路層282之電性連接 墊284,又於該線路増層結構28上形成絕緣保護層 110669 11 200930200 •該絕緣保護層29形成有複數個開孔29〇以對應露出該電 性連接墊284。 本發明復提供一種電路板，係包括：核心板2〇，係 具有相對應之二表面20a，並具有至少一貫穿該二表面 2〇a之通孔201;第一線路層25，係設於該核心板別之 表面20a上，並具有複數線路251 ;電鍍導通孔252，係 設於該通孔201中以電性連接該核心板2〇之二表面2〇& 上之第一線路層25，且於該電鍍導通孔252中填入有塞 〇孔材料27 ’該塞孔材料27與第一線路層25齊平；以及 填充層26，係設於該核心板表面2〇a上之第一線路層25 的線路251之間，並與該第一線路層25齊平。 依上述之結構，該核心板2〇係為絕緣板或内部具有 核心線路層之線路板；該第一線路層25係由薄化金屬層 21’、導電層22及第二金屬層24組成。 又依上述之結構，復包括於該填充層26與第一線路 〇層25上設置線路增層結構28，該線路增層結構28包括 有至少-介電層281、疊置於該介電層上之第二線路層 282，一以及形成於該介電層中並電性連接該第一線路層託 第、線路層282之導電盲孔283,且於該線路增層結構 28表面具有複數電性連接該第二線路層挪之電性連接 兮H X於該線路增層結構28上形成絕緣保護層29， 形成有複數個開孔29。以對應露出該電 主要係於核心板表 因此，本發明之電路板及其製法， 110669 12 200930200 •面以電鍍法（Pattern process)形成第一線路層，以提供 細線路結構，並於該第一線路層的線路之間先以網板印刷 形成填充層，藉以保護該第一線路層，接著於電鍍導通孔 中填入塞孔材料，然後進行刷磨製程，以將凸出於該第一 線路層表面之塞孔材料移除，藉由該填充層與該第一線路 層齊平，俾可保護該線路，以避免該線路於刷磨製程中被 移除，並使該塞孔材料與第一線路層齊平。 上述實施例僅例示性說明本發明之原理及其功效，而 ❹非用於限制本發明。任何熟習此項技藝之人士均可在不違 背本發明之精神及範嘴下，對上述實施例進行修飾盈改 變。因此，本發明之權利保護範圍，應如後述之申請專利 【圖式簡單說明】 電鍍導通孔中形成塞 第1A至II圖係為習知電路板之 孔材料之製法剖視示意圖；以及 〇 第2A至2K圖係本發明電路板及其製法之剖視示竟 圖。 心 【主要元件符號說明】 10 ' 20 核心板 10a 、20a 表面 101 、201 通孔 11 ' 21 第一金屬層 11，， 、21， 薄化金屬層 12、 22 導電層 110669 13 200930200 • 13、23 阻層 130 、 230 阻層開口 • 14 、 24 第二金屬層 15 線路層 151 、 251 線路 152 、 252 電鍍導通孔 16、27 塞孔材料 25 第一線路層 ❹26 填充層 28 線路增層結構 281 介電層 282 第二線路層 283 導電盲孔 284 電性連接墊 29 絕緣保護層 _ 290 開孔200930200 • Nine, invention description: [Technical field to which the invention pertains] The present invention relates to a semiconductor process technology, and more particularly to a circuit board and a method of fabricating the same. [Prior Art] & With the booming of the electronics industry, electronic products are gradually entering the direction of multi-functional and high-performance development. In order to meet the high integration and packaging requirements of semiconductor packages, most of them are provided: two passive components and circuit-loaded circuit boards have gradually evolved from single-layer boards to multi-layer boards, which are limited to a limited space. Next, the circuit area available on the circuit board is expanded by the interlayer connection technology to meet the use requirements of the integrated circuit with high electron density. In order to improve the wiring precision of the circuit board, the industry has developed a layer-up technology (Bui Id-up), that is, on the surface of the core board, a plurality of dielectric layers and circuit layers are alternately formed by using a layer build-up layer, and A plurality of conductive structures, such as conductive vias and through holes (PTH), are formed in the electrical layer for electrical connection between the upper and lower layers. 'Please refer to 帛1A to U, which is a method for forming a circuit and a plating via (ρτΗ) by a conventional chip in a core circuit; as shown in Figure u, first, Two surfaces 1 〇 & =. a first metal layer 11 is formed on the surface of the core plate 10; and as shown in FIG. 1B, the first metal layer u is thinned to form a thinned metal layer 11 As shown in FIG. 1c, the thinned metal layer u on the core plate 10 and its surface 10a forms at least one through hole 110669 5 200930200 , 1 〇 1 ; as shown in FIG. 1D + .. _ ^ . On the surface, 妒 = the metallization layer 1 and the via hole are called -= 2 upper electric layer 12; as shown in FIG. 1E, a resist layer 13 is formed on the isoelectric layer 12, and the resist layer is opened. 13. To expose a portion of the conductive layer 12: the conductive layer 19 is formed in the barrier layer 130, and the second metal layer is formed by plating. 12 f does not 'after removing the resist layer 13 and its covered wire ^ 15 money metal layer U' ' to form a β line with a plurality of lines (5) to form a plated via 152 in the through hole 1 〇 1. ❹ Η Η , , 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 The upper surface of the 15th, the second should be:: When the material 16 is in the 曰 position, the dielectric layer will be affected by the dielectric layer relative to the plug hole line, which will cause the buildup of the build-up layer on the surface of the dielectric layer. Or reliability; in order to avoid the aforementioned problem of 〇SI::, the plug hole (4) 16 of the upper surface of the circuit layer 15 must be brushed as shown in the figure, so that the exposed surface of the 1-hole material 16 and the circuit layer 15 The upper surface is flush. Performing a brushing process to remove the overall structure of the conductive layer 15 above the circuit layer::::r: a conductive germanium 12 and a second gold alloy formed by an electroplating process: a line of faulty circuit layer 15 The thickness of the overall structure is relatively thin. Although the L pitch can be formed, but the thickness is thin, part of the line 151 of the circuit layer is easily removed during the brushing process (as shown in Fig. u), resulting in , , Spring Road 151 was removed and destroyed, so that the follow-up system can not be carried out 110669 6 200930200. Therefore, how to propose a circuit board > imitation, this hitting plate and I method to avoid the conventional technical road layer 'and the 'line on both sides of the electric mine conduction hole is brushed by the plug hole material In the grinding process, it is easy to overcome the problem that the line is brushed and removed. SUMMARY OF THE INVENTION The main purpose of the present invention is to provide a circuit board and a method for manufacturing the same, which can eliminate the plug material filled in the through hole of the electric material and cause the line to be brushed and removed during the brushing process. Missing. To achieve the above and other objects, the present invention provides a circuit board comprising: a core board having two corresponding surfaces and having at least one through hole penetrating the surface, the first circuit layer being disposed on the core On the surface of the board, and having a plurality of lines; a plating via hole is disposed in the through hole to electrically connect the first circuit layer on the two surfaces of the core board, and the plug is filled in the electric money conducting hole a hole material, the plug material is flush with the first circuit layer; and a filling layer is disposed between the lines of the first circuit layer on the surface of the core plate and flush with the first circuit layer. According to the above structure, the core board is an insulating board or a circuit board having a core wiring layer therein; the first circuit layer is composed of a thinned metal layer, a conductive layer and a first metal layer. According to the above structure, the circuit further includes a line build-up structure disposed on the fill layer and the first circuit layer, the line build-up structure comprising at least one dielectric layer and a second line stacked on the dielectric layer a layer, and a conductive via hole formed in the dielectric 110669 7 200930200 * layer and electrically connected to the first τα, the first circuit layer, and the 嗲: structure has a plurality of electrical connections to the second circuit layer Thereafter, an insulating protective layer is formed on the structure of the Qianlu build-up layer, and the core layer is formed with a plurality of openings to correspondingly expose the electrical connection. The method for manufacturing the circuit board is: providing ^ : the core board of the two surfaces, and the core board has at least: the first line on the two surfaces of the core board is layered with the layer of the first line layer of the == electrical connection The plug hole material is filled in; and the electroplating conduction is flush with the first line layer. And the brushing process, the plug material is in accordance with the above method. The core board is one of the circuit boards of the insulating circuit layer; the filling sound. There is a core between the lines of the first-line layer. The method for manufacturing the first circuit layer is as follows: the first metal layer is formed, and the surface of the first surface is thinned; Thinning the current layer, forming a via hole on the thinned metal layer and the surface of the via hole on the thinned metal layer of the core plate and the surface thereof, and forming a resist layer on the electric layer And forming a resist layer in the resist layer on the conductive layer; the sweat opening in the opening of the resist layer to expose a portion of the layer; and removing the resist layer and covering it: Forming a second gold layer 'to expose the first layer having the plurality of lines and the thinned metal road layer from the thinned metal layer and the conductive layer; forming: the second metal layer formed by the 'th line' 130669 8 200930200 The composition, so the overall structure thickness of the first-line layer is thinner - the line spacing. The method of manufacturing the circuit board includes forming a line build-up structure on the fill layer and the first-line layer, the line build-up structure comprising at least one layer stacked on the dielectric layer - Green, 々a Kunshan squad, a circuit layer, and a conductive blind hole formed in the dielectric y and electrically connected to the first and second circuit layers, and having a plurality of electrical connections on the surface of the line build-up structure The second circuit layer;; = connection pad, and the material layer structure cuts the edge layer of the material, and the protective layer is formed with a plurality of openings to correspondingly expose the electrical connection port. The circuit board of the invention and the method for manufacturing the same are formed on the surface of the core board by electroplating to form a first line sound of fine pitch, and the line 2 of the circuit layer is formed by a first (four) brush to form a filling layer. The electric material through hole is filled with m' and then subjected to a brush grinding process to remove the material and the filling layer protruding from the plug hole, thereby protecting the finely spaced first plug hole material, the filling layer and the filling layer The first line is removed to make the first line layer of the distance. The circuit layer is flush and protects the thin room. [Embodiment] The following is a specific style of the person who is familiar with the art. The second::: (4) ^ to understand other advantages and advantages of the present invention. ^ The content is easy. Please refer to the first to 21 (Figure, is a schematic cross-sectional view of the method of the present invention. W circuit board and as shown in Figure 2A 'providing a core with opposite two surfaces 110669 9 200930200 *Board 20, the core board 20 is an insulating board or a circuit board having a core circuit layer therein. In the present embodiment, the core board 2 is an insulating board for description, and the surface of the core board 20 is 2〇 a has a first metal layer 21. As shown in Fig. 2B, the first metal layer 21 is subjected to a thinning process to become a thinned metal layer 21'. As shown in Fig. 2C, the core plate 2 and its core plate The thinned metal layer 21 of the surface 2〇a forms at least one through hole 2〇1. As shown in FIG. 2D, a conductive layer is formed on the surface of the thinned metal layer 21 and the through hole 201. 22, wherein the conductive layer 22 is mainly used as a current conduction path required for subsequent plating of a metal material, which can a metal, an alloy, or a plurality of layers of metal, such as one selected from the group consisting of copper, tin, nickel, chromium, titanium, copper-chromium alloy, or tin-lead alloy. One of plating, vapor deposition, electroless plating, and chemical deposition; or a conductive polymer material such as polyacetylene, polyaniline or organic sulfur polymer, or spin coating, inkjet printing The conductive layer 22 is formed by ink-jet printing or imprinting. As shown in FIG. 2E, a resist layer 23 is formed on the conductive layer 22, and the resist layer 23 is, for example, a dry film. Or a photoresist layer such as a liquid photoresist, which is formed on the conductive layer 22 by printing, spin coating or lamination, and then patterned by exposure, development, etc. A resist opening 23 is formed in 23 to expose a portion of the conductive layer 22. As shown in FIG. 2F, then the conductive layer 110669 10 200930200 * 22 in the resist opening 23 is formed with a second Metal layer 24. As shown in Fig. 2G, the resist layer 23 is subsequently removed and covered The second layer 22 of the cover and the thinned metal layer 21 are formed to form a first circuit layer 25 having a plurality of lines 25 , and a plating via 252 is formed in the through hole 2 〇 1 to electrically connect the core board The first circuit layer 25 on the surface 2〇a of the second surface is such that the first circuit layer 25 of the second layer is composed of the thinned metal layer 2, the conductive layer 22 and the second metal layer 24 formed by electroplating. The overall thickness of the first circuit layer μ is thin, and a fine line pitch can be formed. For example, as shown in FIG. 2H, the line 251 of the first circuit layer 25 on the surface of the core board 2〇& A filling layer 26 is formed by screen printing, and the filling layer 26 may be a polymer resin having a cyclic compound. As shown in Fig. 21, a plug material 27 is filled in the plating via 252. The soil is as shown in FIG. 2J. Thereafter, a brushing process is performed, and the line 251 is protected by the filling layer 26' to prevent the line 251 from being removed during the brushing process, and the plug is removed. The hole material 27 is flush with the first circuit layer support: and the fill layer 26 is flush with the first circuit layer 25. As shown in FIG. 2K, a subsequent build-up layer 28 is formed on the fill layer 26 and the first circuit layer 25, and the line build-up structure 28 includes at least a dielectric layer 28 interposed on the dielectric layer. a second circuit layer 282' on the electrical layer and a conductive via 283 formed in the dielectric layer and electrically connected to the first circuit layer carrier and the second circuit layer 282, and having a surface on the surface of the circuit buildup structure 28 An electrical connection pad 284 electrically connected to the second circuit layer 282 is formed on the circuit layer structure 28 to form an insulating protection layer 110669 11 200930200. The insulating protection layer 29 is formed with a plurality of openings 29 对应 to correspondingly expose The electrical connection pad 284. The present invention further provides a circuit board comprising: a core plate 2 having two corresponding surfaces 20a and having at least one through hole 201 extending through the two surfaces 2a; the first circuit layer 25 is provided on On the surface 20a of the core board, and having a plurality of lines 251, a plating via 252 is disposed in the through hole 201 to electrically connect the first circuit layer on the surface 2 of the core board 2 25, and the plating via 252 is filled with a plug material 27', the plug material 27 is flush with the first circuit layer 25; and the filling layer 26 is disposed on the surface 2a of the core board Between the lines 251 of the first circuit layer 25 and flush with the first circuit layer 25. According to the above structure, the core board 2 is an insulating board or a circuit board having a core wiring layer therein; the first wiring layer 25 is composed of a thinned metal layer 21', a conductive layer 22, and a second metal layer 24. According to the above structure, a line build-up structure 28 is disposed on the fill layer 26 and the first via layer 25, and the line build-up structure 28 includes at least a dielectric layer 281 stacked on the dielectric layer. a second circuit layer 282, a conductive blind via 283 formed in the dielectric layer and electrically connected to the first circuit layer carrier layer 282, and having a plurality of electrodes on the surface of the circuit build-up structure 28 An electrical connection 兮HX is connected to the second circuit layer to form an insulating protective layer 29 on the line build-up structure 28, and a plurality of openings 29 are formed. Therefore, the circuit board of the present invention and the manufacturing method thereof are formed by correspondingly exposing the electricity. 110669 12 200930200 The first circuit layer is formed by a pattern process to provide a fine circuit structure. A filling layer is formed by screen printing between the lines of a circuit layer, thereby protecting the first circuit layer, and then filling the plug hole material in the plating via hole, and then performing a brushing process to protrude from the first The plug hole material on the surface of the circuit layer is removed, and the fill layer is flush with the first circuit layer, so that the line can be protected to prevent the line from being removed in the brushing process, and the plug material is The first line layer is flush. The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as described later in the patent application [Simplified Description of the Drawings] A schematic cross-sectional view of a method for forming a plug material in a plated via hole, which is a hole material of a conventional circuit board; 2A to 2K are cross-sectional views showing the circuit board of the present invention and its manufacturing method. Heart [Main component symbol description] 10 ' 20 core board 10a, 20a surface 101, 201 through hole 11 ' 21 first metal layer 11,, 21, thinned metal layer 12, 22 conductive layer 110669 13 200930200 • 13, 23 Resistor layer 130, 230 resist layer opening • 14, 24 second metal layer 15 circuit layer 151, 251 line 152, 252 electroplated vias 16, 27 plug material 25 first circuit layer ❹ 26 filled layer 28 line build-up structure 281 Electrical layer 282 Second circuit layer 283 Conductive blind hole 284 Electrical connection pad 29 Insulating protective layer _ 290 Opening