200930172 ^f.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種線路板及其製作方法，且特別是 有關於一種内埋式線路板（embedded circuit board)及其製 作方法。 【先前技術】200930172 ^f.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board and a method of fabricating the same, and more particularly to an embedded circuit board and Production Method. [Prior Art]
近年來，隨著電子技術的日新月異，高科技電子產 2繼問世’使得更人性化、功能更佳的電子產品不斷地 =出新’並朝向輕、、薄、短、小的趨勢設計。在這些電 料會配置—線板，此祕基板除了具有導 以外，亦可承載單個例如是電容、電感、電阻或是 日日片之電子元件，以作為電子產 而電子元件或是導電料配置㈣絲上 然 ::加已:™子元件《==::: 板中’已成為當前的關鍵技術。 土 【發明内容】 效地巍-翻埋场路板及其製作方法，1可有 放地鈿減内埋式線路板之尺 了有 輕、薄、短、小的設計趨勢。使内埋式線路板符合 其可提升 本發明提供-_埋魏路㈣ 内埋式線路板之製作效率。 本發明提出-_埋式線路板， 其包括一介電 層 5 200930172 twf.doc/n (dielectric layer)、二線路層（Circuit iayer)以及一電子元 件。這些線路層分別内埋於介電層之兩側邊。此外，電子 元件是内埋於介電層中，且與這些線路層其中之一電性連 接。 在本發明之一實施例中，電子元件與線路層間電性連 接的型癌為覆晶接合（flip chip)。 在本發明之一實施例中，介電層的材質包括玻璃環氧 ❹ 基樹脂（FR-4、FR-5)、雙順丁烯二酸醯亞胺 (Bismaleimide-Triazine，BT)或環氧樹脂（ep〇xy resin)。 在本發明之一實施例中，電子元件為主動元件或是被 動元件。 本發明另提出一種内埋式線路板的製作方法，其包括 " 了列步驟。首先’提供—複合载板，複合載板包括-第- 載板、-第二載板以及-第三載板，第一載板與第二載板 分別位於第三載板之兩侧。接著，分別於第一載板與第二 載板上形成一線路層。然後，移除第三載板，以分^ ❹ 驗以及第二載板。接著，於第-載板上形成—乾線^| 電性連接之電子元件，其中第一載板、與第一載板對應之 線路層以及電子兀件構成-第一線路結構，而第二載板以 及與其對應之線路層構成一第二線路結構。接著，提供一 介電層，並分別於介電層之兩側壓合第一線路結構以及第 二線路賴。之後，歸第—餘以及第二餘以形成 一内埋式線路板，其中介電層之一側内埋有電子元件以及 與第-载板對應之線路層，另一侧内埋有與第二載板對應 6 200930172 —'twf.doc/n 之線路層。 形成第-載板以及第二載板上 m-忐包括下列步驟。首先，於第一載板以及 路Ϊ。上形成—導電層。接著，圖案化導電層以形成線 鲁 ，本發明之_實_巾，圖案化導電層以形成線路層 阳®、、包ί下列步驟。首先，於每—個導電層上形成一光 曰接著’圖案化該光阻層以形成一圖案化光阻層，其 中圖案化光阻層暴露出部分導電層。然後，移除圖案化^ 阻層暴露出之部分導電層’以形成線路層。之後，移除該 圖案化光阻層。 ,，在本發明之一實施例中，圖案化該光阻層之方法包括 微影製程（lithography process)。 % 本發明再提出一種内埋式線路板的製作方法，其包括 下列步驟。首先，提供一複合載板，複合載板包括一第一 載板、一第二載板以及一第三載板，第一載板與第二载板 分別位於第三載板之兩側。接著，分別於第一載板與第二 载板上形成一線路層。然後，於第一載板上形成一與線路 層電性連接之電子元件，其中第一载板、與第一載板對應 之線路層以及電子元件構成一第一線路結構，第二载板以 及與其對應之線路層構成一第二線路結構，而第一線路矣士 構、第二線路結構以及第三载板構成一複合線路結構。接 著’移除第三載板’以分離第一線路結構以及第二線路結 構。接著，提供一介電層，並分別於介電層之兩側壓合第 7 200930172 吃wf.doc/n -線路結構以及第二線路結構。之後，移除第一載板以及 第-載板’以形成-内埋式線路板，其中介電層之一側内 埋有電子元件以及與第—載板對應之線路層，另一側内埋 有與弟二載板對應之線路層。 在本發明之—實施例中於第一載板以及第二載板上 形成線路層之方法包括下列步驟。首先，於第—載板以及 第-載板上形成-導電層。接著，圖案化導電層 路層。 在本發明之-實施例中，圖案化導電層以形成線路層 之方法包括下列步驟。首先，於每—個導電層上形成一光 阻層。接著，圖案化該級m彡成―圖案化光阻層，盆 中圖案化光阻層暴露出部分導電層。然後，移除圖案化^ 阻層暴露出之部分導電層，以形成線路層。之後 圖案化光阻層。 ,，在本發明之一實施例中，圖案化該光阻層之方法包括 微影製程。 參 本發明又提出一種内埋式線路板的製作方法，其包括 下列步驟。首先，提供一複合載板，複合載板包括二^一 載板、一第二載板以及一第三載板，第一載板與第二载板 刀別位於第二載板之兩側。接著，分別於第一载板與第 載板上形成一線路層。然後’於第一載板上形成—與^ 層電性連接之電子元件，其中第-她、與第—载板對 之線路層以及電子元件構成一第一線路結構，而第二 以及與其對應之線路層構成一第二線路結構。接著了 8 200930172 >twf.doc/n 第一载板，以为離第一線路結構以及第二線路結構。提供 另一複合線路結構，並於另一複合線路結構具有電子元件 之一侧壓合一第二介電層與第二線路結構，於另一侧壓合 一第一介電層與第一線路結構，其中第二介電層位於另一 複合線路結構與第二線路結構之間，第一介電層位於另一 複合線路結構與第一線路結構之間。後 第二载板以及第三載板，以形成二_式|路=，=反第 ❹ 一介電層以及第二介電層之一側内埋有電子元件以及與第 —載板對應之線路層，另-侧内埋有與第二載板對應之線 路層。 在本發明之一實施例中，於第一載板以及第二載板上 形成線路層之方法包括下列步驟。首先，於第一載板以及 第-載板上形成-導電層。接著，圖案化導電層以形成線 路層。 在本發明之-實施例中，圖案化導電層以形成線路層 魯 之方法包括下列步驟。首先，於每—個導電層上形成—光 =層。接著，圖案化該級層以形成-圖案化光阻層，其 圖案化光阻層暴露出部分導電層。然後，移除圖案化光 阻層暴露出之部分導電層，以形成線路層 。之後，移除該 圖案化光阻層。 y在本發明之一實施例中，圖案化該光阻層之方法包括 微影製程。 本發明是採用堆疊的方式來將電子元件以及線路層 配置於内埋式線路板中。因此，本發明可縮減内埋式線ς 9 200930172 twfdoc/n 板之尺寸，以符合輕、薄、短、小的設計趨勢。此外，在 同樣面積之内埋式線路板中，本發明可置入更多線路層以 及電子兀件’以提升了内埋式線路板的效能。另—方面， 、她於應用雷射成孔以及機械鑽孔之方式來製作線路層， 本發明之内埋式線路板的製作方法有較佳之線路層製作效 率，進而提升内埋式線路板之整體製作效能。 另外，本發明亦提出同時製作二内埋式電路板的方 ❹ 法，以更有效地提升内埋式電路板的產能以及製作速率。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉較佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】In recent years, with the rapid development of electronic technology, high-tech electronic products have been introduced to make more user-friendly and functional electronic products continue to be new and oriented toward light, thin, short and small trends. In these materials, the wire board can be configured. In addition to the guide, the secret substrate can also carry a single electronic component such as a capacitor, an inductor, a resistor or a day chip to be used as an electronic component or a conductive material. (4) On the silk:: Plus has: TM sub-component "==::: board" has become the current key technology. Soil [Summary] 效 巍 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻The buried circuit board can be improved according to the invention. The invention provides the production efficiency of the embedded circuit board of the buried Wei Road (4). The present invention proposes a buried circuit board comprising a dielectric layer 5 200930172 twf.doc/n (dielectric layer), a circuit iayer and an electronic component. These circuit layers are buried in the sides of the dielectric layer, respectively. In addition, the electronic components are embedded in the dielectric layer and are electrically connected to one of the circuit layers. In an embodiment of the invention, the type of cancer in which the electronic component and the wiring layer are electrically connected is a flip chip. In an embodiment of the invention, the material of the dielectric layer comprises glass epoxy ruthenium resin (FR-4, FR-5), Bismaleimide-Triazine (BT) or epoxy. Resin (ep〇xy resin). In one embodiment of the invention, the electronic component is an active component or a passive component. The invention further provides a method for fabricating a buried circuit board, which comprises the steps of < First, a composite carrier is provided. The composite carrier includes a -first carrier, a second carrier, and a third carrier. The first carrier and the second carrier are respectively located on opposite sides of the third carrier. Next, a wiring layer is formed on the first carrier and the second carrier, respectively. Then, the third carrier is removed to separate the test and the second carrier. Then, an electronic component electrically connected to the first carrier, the first carrier, the circuit layer corresponding to the first carrier, and the electronic component constitute a first circuit structure, and the second carrier The board and its corresponding circuit layer form a second line structure. Next, a dielectric layer is provided, and the first line structure and the second line are respectively pressed on both sides of the dielectric layer. Thereafter, the first and the second are formed to form an embedded circuit board, wherein one side of the dielectric layer is embedded with an electronic component and a circuit layer corresponding to the first carrier, and the other side is buried The second carrier board corresponds to 6 200930172 - the circuit layer of 'twf.doc/n. Forming the first carrier and the second carrier m-忐 includes the following steps. First, on the first carrier board and the road. Formed on - a conductive layer. Next, the conductive layer is patterned to form a line, the present invention is patterned, and the conductive layer is patterned to form a wiring layer, and the following steps are performed. First, a photoresist is formed on each of the conductive layers, and the photoresist layer is patterned to form a patterned photoresist layer, wherein the patterned photoresist layer exposes a portion of the conductive layer. Then, a portion of the conductive layer exposed by the patterned resist layer is removed to form a wiring layer. Thereafter, the patterned photoresist layer is removed. In one embodiment of the invention, the method of patterning the photoresist layer comprises a lithography process. % The present invention further provides a method of fabricating a buried wiring board, which comprises the following steps. First, a composite carrier is provided. The composite carrier includes a first carrier, a second carrier, and a third carrier. The first carrier and the second carrier are respectively located on opposite sides of the third carrier. Next, a wiring layer is formed on the first carrier and the second carrier, respectively. Then, an electronic component electrically connected to the circuit layer is formed on the first carrier, wherein the first carrier, the circuit layer corresponding to the first carrier, and the electronic component form a first circuit structure, the second carrier, and The circuit layer corresponding thereto constitutes a second line structure, and the first line gentleman structure, the second line structure and the third carrier board form a composite line structure. Next, the third carrier is removed to separate the first line structure and the second line structure. Next, a dielectric layer is provided, and the wf.doc/n-line structure and the second line structure are respectively pressed on both sides of the dielectric layer. Thereafter, the first carrier and the first carrier are removed to form a buried circuit board, wherein one side of the dielectric layer is embedded with electronic components and a circuit layer corresponding to the first carrier, and the other side is inside A circuit layer corresponding to the second carrier board is buried. The method of forming a wiring layer on the first carrier and the second carrier in the embodiment of the present invention includes the following steps. First, a conductive layer is formed on the first carrier and the first carrier. Next, the conductive layer layer is patterned. In the embodiment of the invention, the method of patterning the conductive layer to form the wiring layer comprises the following steps. First, a photoresist layer is formed on each of the conductive layers. Next, the stage m is patterned into a "patterned photoresist layer", and the patterned photoresist layer in the basin exposes a portion of the conductive layer. Then, a portion of the conductive layer exposed by the patterned resist layer is removed to form a wiring layer. The photoresist layer is then patterned. In one embodiment of the invention, the method of patterning the photoresist layer comprises a lithography process. The invention further proposes a method of fabricating a buried wiring board, which comprises the following steps. First, a composite carrier is provided. The composite carrier includes two carrier plates, a second carrier plate and a third carrier plate. The first carrier plate and the second carrier plate are located on opposite sides of the second carrier plate. Next, a wiring layer is formed on the first carrier and the carrier, respectively. Then forming an electronic component electrically connected to the layer on the first carrier, wherein the first and the first circuit structure of the first carrier layer and the electronic component form a first line structure, and the second and corresponding The circuit layer constitutes a second line structure. Then 8 200930172 > twf.doc / n first carrier board, thinking that it is away from the first line structure and the second line structure. Providing another composite circuit structure, and pressing a second dielectric layer and a second wiring structure on one side of the electronic circuit component on the other composite circuit structure, and pressing a first dielectric layer and the first circuit on the other side The structure wherein the second dielectric layer is between the other composite line structure and the second line structure, and the first dielectric layer is between the other composite line structure and the first line structure. a second carrier plate and a third carrier plate are formed to form an electronic component and a corresponding one of the second carrier layer and the second dielectric layer In the circuit layer, a circuit layer corresponding to the second carrier is buried in the other side. In one embodiment of the invention, the method of forming a wiring layer on the first carrier and the second carrier includes the following steps. First, a conductive layer is formed on the first carrier and the first carrier. Next, the conductive layer is patterned to form a wiring layer. In the embodiment of the present invention, the method of patterning the conductive layer to form the wiring layer includes the following steps. First, a light layer is formed on each of the conductive layers. Next, the grade layer is patterned to form a patterned photoresist layer, the patterned photoresist layer exposing a portion of the conductive layer. Then, a portion of the conductive layer exposed by the patterned photoresist layer is removed to form a wiring layer. Thereafter, the patterned photoresist layer is removed. In one embodiment of the invention, the method of patterning the photoresist layer comprises a lithography process. The present invention uses a stacked manner to dispose electronic components and circuit layers in a buried circuit board. Therefore, the present invention can reduce the size of the buried coil 9 200930172 twfdoc/n board to meet the trend of light, thin, short and small design. In addition, in a buried circuit board of the same area, the present invention can accommodate more circuit layers and electronic components to enhance the performance of the buried circuit board. On the other hand, she uses the method of laser hole formation and mechanical drilling to make the circuit layer. The method for manufacturing the buried circuit board of the present invention has better circuit layer fabrication efficiency, thereby improving the buried circuit board. Overall production performance. In addition, the present invention also proposes a method of simultaneously fabricating two buried circuit boards to more effectively improve the productivity and production rate of the buried circuit board. The above described features and advantages of the present invention will become more apparent from the following description. [Embodiment]
圖1A至圖1K繪示本發明一實施例之内埋式線路板 之^•作方法的流程剖視圖。本實施例之内埋式線路板的製 作方法包括下列步驟：首先，如圖1A所示，提供一複合 載板110,複合載板110包括一第一載板112、一第二載板 ❹ 114以及一第三載板116，第一載板112與第二載板JR 刀別位於第三載板116的兩侧。接著，如圖至圖1F所 示’分別於第一載板112與第二載板114上形成一線路層 120’。下文中，本實施例將先針對線路層12〇，之形成方式 做詳細說明。 承上所述，在本實施例中，分別於第一载板112與第 二载板114上形成線路層丨20’之方式包括下列步驟：首 先’於第一載板112以及第二載板114上形成一材質例如 twf.doc/n 200930172 是銅之導電層12G(如圖IB所示）。接著，例如是藉由遷人 (lamination)之方式以於每一個導電層12〇上形成一光二 層130(如圖1C所示）。接著’例如是藉由微影製程來圖案 化該光阻層130以形成一圖案化光阻層13〇，（如圖1〇所 示）。其中，圖案化光阻層130,暴露出部分導電層12〇。然 後，例如是藉由蝕刻製程（etching process)來移除圖案化= 阻層130’暴露出之部分導電層12〇,並移除該圖案化光阻 層130’即可完成線路層12〇,之製作（如圖1E至圖汀 一 \ ' 不）。 在完成線路層120,之製作後，接著如圖1G所示，移 除第三載板116’以分離第一載板112以及第二載板114。 接著’如圖1H所示，於第一載板112上形成一與線路層 120’電性連接之電子元件14〇，其中電子元件14〇與線路 層120間電性連接的型態例如為覆晶接合，且電子元件可 以疋主動元件或是被動元件。在本實施例中，第一載板 112、與第一載板112對應之線路層12〇，以及電子元件14〇 構成一第一線路結構S11〇，而第二載板114以及與其對應 之線路層120’構成一第二線路結構sl2〇。接著，如圖u 至圖1J所示’提供一介電層150，並分別於介電層150之 兩側邊壓合第一線路結構Sii〇以及第二線路結構S120。 其中’介電層150的材質例如是玻璃環氧基樹脂、雙順丁 烯二酸酿亞胺或環氧樹脂。之後，如圖1K所示，例如是 利用剝離法（Hft_〇ff)來移除第一載板112以及第二載板 114。如此一來，即可完成本實施例之内埋式線路板100 11 200930172 》tw£d〇c/n 的製作，其中介電層150之一侧内埋 ==一另-侧内埋有= 祐之至圖汉緣示本發明另一實施例之内埋式線路 ΐ程的流程剖視圖。其中’圖2A至圖2F之製作 =圖1A至圖1F之製作流程相同，本文在此即不做任 ^述。在本實施例中，完成圖2F所示之線路層12〇，的 乍汰’本實施例會預先於第一載板112上形成與線路層 120電性連接之電子元件⑽（如圖犯所示）。同樣地，第 m 一載板112、與第一載板112對應之線路層12〇，以及電子 凡件140構成第—線路結構㈣，而第二載板114以及與 其對應之線路層120,構成第二線路結構sl2〇。此外，第一 線路結構siio、第二線路結構S120以及第三載板116構 成一複合線路結構S100。接著，如圖2H所示，移除第三 載板116，以分離第一線路結構sn〇以及第二線路結構 S120。接著’與圖u至圖化所示之製程相同，提供一介 電層150,並分別於介電層15〇之兩侧壓合第一線路結構 siio以及第二線路結構S120(如圖21至圖2J所示）’接著 再移除第一載板112以及第二載板n4(如圖2K所示）。如 此一來，同樣可形成内埋式線路板1〇〇。 圖3A至圖3K繪示本發明再一實施例之内埋式線路 板之製作方法的流程剖視圖。其中，圖3A至圖3H之製作 流程與圖2A至圖2H之製作流程相同，本文在此即不做任 何贅述。在本實施例中，在移除第三載板116，以分離第 12 200930172 ^twf.doc/n1A to 1K are cross-sectional views showing a flow of a method for manufacturing a buried wiring board according to an embodiment of the present invention. The method for fabricating the buried circuit board of the present embodiment includes the following steps. First, as shown in FIG. 1A, a composite carrier 110 is provided. The composite carrier 110 includes a first carrier 112 and a second carrier 114. And a third carrier 116, the first carrier 112 and the second carrier JR are located on both sides of the third carrier 116. Next, a wiring layer 120' is formed on the first carrier 112 and the second carrier 114, respectively, as shown in Fig. 1F. Hereinafter, the embodiment will be described in detail with respect to the formation of the circuit layer 12A. As described above, in the embodiment, the manner of forming the circuit layer 20' on the first carrier 112 and the second carrier 114 respectively includes the following steps: firstly, the first carrier 112 and the second carrier. A material such as twf.doc/n 200930172 is formed on 114 as a conductive layer 12G of copper (as shown in FIG. 1B). Next, a photonic layer 130 is formed on each of the conductive layers 12, for example, by lamination (as shown in Fig. 1C). Then, for example, the photoresist layer 130 is patterned by a lithography process to form a patterned photoresist layer 13 (as shown in FIG. 1A). Wherein, the patterned photoresist layer 130 exposes a portion of the conductive layer 12A. Then, the wiring layer 12 is completed, for example, by an etching process to remove a portion of the conductive layer 12 图案 exposed by the patterned resist layer 130 ′ and removing the patterned photoresist layer 130 ′. Production (Figure 1E to Tingyi \ 'No). After the completion of the fabrication of the circuit layer 120, the third carrier 116' is removed to separate the first carrier 112 and the second carrier 114, as shown in Fig. 1G. Then, as shown in FIG. 1H, an electronic component 14A electrically connected to the circuit layer 120' is formed on the first carrier 112. The type of the electrical connection between the electronic component 14A and the circuit layer 120 is, for example, a cover. The crystal is bonded, and the electronic component can be an active component or a passive component. In this embodiment, the first carrier 112, the circuit layer 12A corresponding to the first carrier 112, and the electronic component 14A constitute a first line structure S11, and the second carrier 114 and its corresponding line Layer 120' constitutes a second line structure sl2. Next, a dielectric layer 150 is provided as shown in FIG. 1 to FIG. 1J, and the first wiring structure Sii and the second wiring structure S120 are respectively pressed on both sides of the dielectric layer 150. The material of the dielectric layer 150 is, for example, a glass epoxy resin, a bis-butenedioic acid, or an epoxy resin. Thereafter, as shown in Fig. 1K, for example, the first carrier 112 and the second carrier 114 are removed by a lift-off method (Hft_〇ff). In this way, the fabrication of the buried circuit board 100 11 200930172 "tw£d〇c/n" of the present embodiment can be completed, wherein one side of the dielectric layer 150 is buried == one other side is buried in the side =至至至图汉缘 shows a cross-sectional view of a buried circuit process of another embodiment of the present invention. The production process of FIG. 2A to FIG. 2F is the same as that of FIG. 1A to FIG. 1F, and is not described herein. In this embodiment, the implementation of the circuit layer 12A shown in FIG. 2F is completed. In this embodiment, an electronic component (10) electrically connected to the circuit layer 120 is formed on the first carrier 112 in advance (as shown in the figure). ). Similarly, the m-th carrier 112, the circuit layer 12A corresponding to the first carrier 112, and the electronic component 140 constitute a first-line structure (4), and the second carrier 114 and the corresponding circuit layer 120 thereof constitute The second line structure sl2〇. Further, the first line structure siio, the second line structure S120, and the third carrier plate 116 constitute a composite line structure S100. Next, as shown in Fig. 2H, the third carrier 116 is removed to separate the first wiring structure sn and the second wiring structure S120. Then, in the same manner as the process shown in FIG. 5 to FIG. 3, a dielectric layer 150 is provided, and the first line structure siio and the second line structure S120 are respectively pressed on both sides of the dielectric layer 15 (see FIG. 21 to Figure 2J) 'The first carrier 112 and the second carrier n4 are then removed (as shown in Figure 2K). As a result, the buried wiring board 1 can also be formed. 3A to 3K are cross-sectional views showing a flow of a method of fabricating a buried wiring board according to still another embodiment of the present invention. The production process of FIG. 3A to FIG. 3H is the same as the production process of FIG. 2A to FIG. 2H, and nothing will be described herein. In this embodiment, the third carrier 116 is removed to separate the 12th 200930172 ^twf.doc/n
一線路結構S110以及第二線路結構sl2〇(如圖3ΙΪ所示） 之後’本實施例會提供另一複合線路結構S100’，並於複 合線路結構S100具有電子元件14〇之一侧壓合一第二介 電層150”與第二線路結構Sl2〇，於另一侧壓合一第一介 電層150’與第一線路結構811〇(如圖31至圖3j所示），其 中第二介電層150”位於複合線路結構si〇〇,與第二線路結 構S120之間’第一介電層15〇，位於複合線路結構sioo, 與第一線路結構S110之間。之後，同樣可利用剝離法來 移除第一載板112、第二载板114以及第三載板116，即可 形成内埋式線路板1〇〇’以及1〇〇，，（如圖3K所示）。其中， 内埋式線路板1〇〇’以及1〇〇，，之組成相同於内埋式線路板 100(如圖1Κ所示）之組成。 綜上所述’本發明是利用堆疊的方式來將具有電子元 件與線路層之第一載板以及具有線路層之第二載板分別壓 合於介電層之兩側，以使介電層之兩側分別内埋有一線路 層以及一線路層與一電子元件之組合。相較於將線路層以 及電子το件配置在同一平面之線路板設計方式，本發明能 有效地縮軸埋5^線路板之尺寸，以使内埋^線路板符合 輕、薄、短、小的設計趨勢。此外，在同樣面積之内埋式 線路板中’本發明可置人更多線路層以及電子元件，以提 内埋式線路板的魏H相較於翻雷射成孔以 孔之方式來製作線路層，由於本發明是利用微影 線路層之㈣位置，因此本發明有較佳之線路 θ ’。，進而提升了内埋式線路板之整體製作效能。 13 200930172 'twf.doc/n 另一方面 、 ，丰發明亦提出同時製作二内埋式電路起沾 方法，以更有效地提相时電路板的產能以及製作、。 —雖然本發明已峨佳實施例揭露如上然其並非用以 限定本發明’任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範圍内，當可作些許之更動與潤飾， 因此本發明之保護範圍當視後附之申請專利範圍所界定 為準。 【圖式簡單說明】 圖1A至圖1K繪示本發明一實施例之内埋式線路板 之製作方法的流程剖視圖。 圖2A至圖2K繪示本發明另一實施例之内埋式線路 板之製作方法的流程剖視圖。 圖3A至圖3K繪示本發明再一實施例之内埋式線路 板之製作方法的流程剖視圖。 β 【主要元件符號說明】 100 :内埋式線路板 110 :複合載板 112 :第一載板 114 ··第二載板 116 :第三載板 120 :導電層 120’ ：線路層 twf.doc/n 200930172 130 :光阻層 130’：圖案化光阻層 140 :電子元件 150 :介電層 150’ ：第一介電層 150” ：第二介電層 S100、S100’ ：複合線路結構 S110 :第一線路結構 S120 :第二線路結構A line structure S110 and a second line structure sl2〇 (shown in FIG. 3A) are followed by 'this embodiment provides another composite line structure S100', and the composite line structure S100 has one side of the electronic component 14〇. The second dielectric layer 150" and the second wiring structure S12, and the first dielectric layer 150' and the first wiring structure 811 (shown in FIGS. 31 to 3j) are pressed on the other side, wherein the second dielectric layer The electrical layer 150" is located between the composite circuit structure si and the second dielectric structure S120, and is located between the composite circuit structure sioo and the first circuit structure S110. Thereafter, the first carrier 112, the second carrier 114, and the third carrier 116 can also be removed by a lift-off method to form the buried circuit board 1' and 1', (FIG. 3K) Shown). Among them, the built-in circuit boards 1〇〇' and 1〇〇 have the same composition as the buried circuit board 100 (shown in FIG. 1A). In summary, the present invention utilizes a stacking method to press a first carrier having an electronic component and a wiring layer and a second carrier having a wiring layer on both sides of the dielectric layer to form a dielectric layer. A circuit layer and a combination of a circuit layer and an electronic component are embedded in each of the two sides. Compared with the circuit board design method in which the circuit layer and the electronic component are disposed on the same plane, the invention can effectively reduce the size of the buried circuit board, so that the embedded circuit board conforms to light, thin, short and small. Design trends. In addition, in the buried circuit board of the same area, the present invention can place more circuit layers and electronic components, so that the Wei H phase of the buried circuit board can be made by holes. The circuit layer, since the present invention utilizes the (four) position of the lithographic circuit layer, the present invention has a preferred line θ '. , thereby improving the overall production efficiency of the embedded circuit board. 13 200930172 'twf.doc/n On the other hand, Feng invention also proposed to simultaneously produce two buried circuit dipping methods to more effectively improve the production capacity and production of the circuit board. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1K are cross-sectional views showing a process of fabricating a buried wiring board according to an embodiment of the present invention. 2A to 2K are cross-sectional views showing a flow of a method of fabricating a buried wiring board according to another embodiment of the present invention. 3A to 3K are cross-sectional views showing a flow of a method of fabricating a buried wiring board according to still another embodiment of the present invention. β [Main component symbol description] 100: Buried circuit board 110: Composite carrier 112: First carrier 114 · Second carrier 116: Third carrier 120: Conductive layer 120': Circuit layer twf.doc /n 200930172 130: photoresist layer 130': patterned photoresist layer 140: electronic component 150: dielectric layer 150': first dielectric layer 150": second dielectric layer S100, S100': composite circuit structure S110 : First line structure S120: second line structure
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