CN108550531B

CN108550531B - Method for manufacturing package substrate

Info

Publication number: CN108550531B
Application number: CN201810463541.6A
Authority: CN
Inventors: 欧宪勋; 程晓玲; 韩建华
Original assignee: ASE Shanghai Inc
Current assignee: ASE Shanghai Inc
Priority date: 2018-05-15
Filing date: 2018-05-15
Publication date: 2020-05-08
Anticipated expiration: 2038-05-15
Also published as: CN108550531A

Abstract

The present invention relates to a method for manufacturing a package substrate. The manufacturing method of the package substrate according to the embodiment of the invention comprises the steps of providing a first laminated structure, wherein the first laminated structure comprises a first metal layer, a second metal layer and a capacitor dielectric layer positioned between the first metal layer and the second metal layer; patterning the first metal layer of the first laminated structure to form a first circuit layer; providing a carrier plate, wherein the carrier plate is provided with a first surface and a second surface which are opposite; pressing a first dielectric layer and a patterned first laminated structure on the first surface and the second surface of the carrier; and patterning the second metal layer of the first laminated structure to form a second circuit layer. The manufacturing method of the packaging substrate provided by the invention not only realizes the fine layout of the internal elements of the packaging substrate, but also improves the output efficiency of the packaging substrate.

Description

Method for manufacturing package substrate

Technical Field

The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a packaging substrate.

Background

In the current semiconductor packaging technology, a capacitor element is arranged inside a packaging substrate, which is a solution for realizing the miniaturization of an electronic system, and the solution is generally applied to electronic products such as microphones, wearable devices and the like, and can play roles in filtering, timing, decoupling and storing electric energy. In this way, not only can the stability and reliability of the product be improved, but also the physical size of the product is reduced.

The capacitor element is generally composed of two copper foils having a thickness of 35 μm or 70 μm and a dielectric material layer having a thickness of 20 μm or less between the two copper foils. Since the dielectric material layer is very thin, it is difficult to provide sufficient support in the manufacturing process, the conventional technology usually manufactures the circuits on the upper and lower sides of the dielectric material layer in two steps, but only one substrate can be produced at a time in the process, and the production efficiency is low. Moreover, since the thickness of the package substrate to be manufactured is too thin, the conventional technology also has a high requirement on the thin plate capability of the machine.

Therefore, there is a need for an improved method for manufacturing a package substrate to solve the above-mentioned problems of the prior art.

Disclosure of Invention

An objective of the present invention is to provide a method for manufacturing a package substrate, in which an embedded capacitor is combined with a micro circuit, and a carrier is used to provide support in the manufacturing method, so as to improve the yield efficiency of the package substrate.

An embodiment of the present invention provides a method for manufacturing a package substrate, including: providing a first laminated structure, wherein the first laminated structure comprises a first metal layer, a first circuit layer and a capacitor dielectric layer positioned between the first metal layer and the first circuit layer; providing a carrier plate, wherein the carrier plate is provided with a first surface and a second surface which are opposite; and pressing the first superposed structure onto the first surface and the second surface of the carrier plate, and patterning the first metal layer of the first superposed structure to form a second circuit layer of the first superposed structure.

According to an embodiment of the present invention, the carrier includes a sacrificial layer, a second metal layer disposed on two opposite surfaces of the sacrificial layer, and a third metal layer disposed on a surface of the second metal layer.

According to an embodiment of the present invention, the method for manufacturing the package substrate further includes providing a third stacked structure, and pressing the third stacked structure onto the second circuit layer of the first stacked structure. The third stacked structure includes a second dielectric layer and a fourth metal layer, the second dielectric layer is located between the second circuit layer and the fourth metal layer.

According to an embodiment of the present invention, the third stacked structure further includes a resistive material layer between the second dielectric layer and the fourth metal layer.

According to an embodiment of the present invention, the method for manufacturing the package substrate further includes removing the sacrificial layer and the second metal layer, and forming a plurality of conductive bumps in the second dielectric layer. The second circuit layer and the fourth metal layer are electrically connected through the conductive block. And patterning the fourth metal layer to form a third circuit layer. And patterning the fourth metal layer and the resistance layer material to form a third circuit layer and a resistance layer thereof, and forming a solder mask layer on the surface of the packaging substrate.

The packaging substrate provided by the embodiment of the invention is different from the traditional design, has the layout characteristics of the embedded capacitor and the fine circuit, and utilizes the carrier plate to provide support in the manufacturing method, thereby not only realizing the fine layout of the elements in the packaging substrate, but also improving the output efficiency of the packaging substrate.

Drawings

FIGS. 1-11 are cross-sectional views of a package substrate at various stages of its manufacture according to an embodiment of the present invention

Detailed Description

In order that the spirit of the invention may be better understood, some preferred embodiments of the invention are described below.

Fig. 1-11 are cross-sectional views of a package substrate at various stages of its manufacture according to an embodiment of the present invention. However, it is fully understood by those skilled in the art that the package substrate 100 shown in fig. 11 can be obtained according to other embodiments of the present invention without being limited to the steps illustrated in fig. 1-10. In other words, as will be apparent to those skilled in the art based on the following disclosure, the manufacturing process of the package substrate is adjusted according to the structure or production requirement of the package substrate, and the embodiment is merely an example of the manufacturing process of the package substrate and is not intended to limit the specific manufacturing method thereof.

First, referring to fig. 1, a first laminated structure 10 is provided. The first stacked structure 10 includes a first metal layer 11, a second metal layer 12, and a capacitor dielectric layer 13, wherein the capacitor dielectric layer 13 is located between the first metal layer 11 and the second metal layer 12, and has a thickness greater than 0 micron and less than or equal to 20 microns.

Next, referring to fig. 2, the first metal layer 11 of the first stacked structure 10 is patterned to form a first circuit layer 14, where the first circuit layer 14 has a third surface 141 and a fourth surface 142 opposite to each other, and the third surface 141 is in direct contact with the capacitor dielectric layer 13.

Referring to fig. 3, a carrier plate 20 is provided, the carrier plate 20 has a first surface 201 and a second surface 202 opposite to each other, and includes a sacrificial layer 21, a third metal layer 22 respectively disposed on the two opposite surfaces of the sacrificial layer 21, and a fourth metal layer 23 disposed on the third metal layer 22, wherein the third metal layer 22 is located between the sacrificial layer 21 and the fourth metal layer 23.

Next, referring to fig. 4, the first dielectric layer 15 and the patterned first stacked structure 10 are laminated on the first surface 201 and the second surface 202 of the carrier 20. The first dielectric layer 15 is adjacent to the first circuit layer 14 and directly contacts the fourth surface 142 of the first circuit layer 14. In the present embodiment, the first dielectric layer 15 is laminated on the patterned first stacked structure 10, such that the first circuit layer 14 is embedded in the first dielectric layer 15, i.e. the top surface of the first dielectric layer 15 is flush with the first surface 141 of the first circuit layer 14. Meanwhile, the first dielectric layer 15 and the patterned first stacked structure 10, which are pressed together, are stacked on the fourth metal layer 23, such that the first dielectric layer 15 is in direct contact with the first surface 201 and the second surface 202 of the carrier 20.

Next, referring to fig. 5, the second metal layer 12 of the first stacked structure 10 is patterned to form a second circuit layer 16.

Referring to fig. 6, a second dielectric layer 17 and a third stacked structure 30 are laminated on the second circuit layer 16, and the second dielectric layer 17 can be laminated on the second circuit layer 16, so that the second circuit layer 16 is embedded in the second dielectric layer 17, i.e. the bottom surface of the second dielectric layer 17 is flush with the bottom surface of the second circuit layer 16. In the present embodiment, the third stacked structure 30 may further include a fifth metal layer 31, and the second dielectric layer 17 is located between the second circuit layer 16 and the fifth metal layer 31. The third stacked structure 30 may further include a resistance material layer 32, the resistance material layer 32 is located between the second dielectric layer 17 and the fifth metal layer 31 and is in direct contact with the second dielectric layer 17 and the fifth metal layer 31, and the resistance material layer 32 in this embodiment may be a copper foil one surface of which is coated with a nickel-phosphorus alloy, and has a thickness greater than 0 micron and equal to or less than 0.5 micron.

The sacrificial layer 21 and the third metal layer 22 are removed to obtain two identical substrate structures, wherein one substrate structure is shown in fig. 7.

Next, referring to fig. 8, via holes are formed in the fifth metal layer 31, the resistive material layer 32, the second dielectric layer 17, the second circuit layer 16, the capacitor dielectric layer 13, the first circuit layer 14 and the first dielectric layer 15 by using a drilling method commonly used in the art, such as laser drilling, and the via hole 18 is further filled with metal to form the via hole 18, wherein the via hole 18 can conduct at least two of the fifth metal layer 31, the first circuit layer 14, the second circuit layer 16 and the fourth metal layer 23.

Next, referring to fig. 9, a first patterning process is performed on a partial region of the fifth metal layer 31 and the resistance material layer 32 until the second dielectric layer 17 is exposed, and simultaneously, a partial region of the fourth metal layer 23 is patterned until the first dielectric layer 15 is exposed to form the third circuit layer 19.

Next, as shown in fig. 10, the fifth metal layer 31 is subjected to a second patterning process. The sub-patterned region does not overlap with the first-patterned region shown in fig. 10, and the sub-patterning exposes only the resistive material layer 32, thereby forming the fourth wiring layer 40 and the resistive layer 50.

Finally, a solder mask 60 is formed on a partial area of the exposed surfaces of the fourth wiring layer 40 and the third wiring layer 19, and a package substrate 100 as shown in fig. 11 is finally formed.

Compared with the traditional manufacturing method of the packaging substrate with the embedded capacitor, the manufacturing method of the packaging substrate provided by the embodiment of the invention has the following advantages: on one hand, the carrier plate introduced in the embodiment of the invention can provide good support, so that the risk of wrinkling of the carrier plate and the plate is avoided, and the operability of the packaging substrate in the whole circuit manufacturing process is improved; on the other hand, in the manufacturing method provided by the embodiment of the invention, two packaging substrates can be obtained by one-time operation, so that the output efficiency of the packaging substrates is doubled, and the production cost is reduced.

As will be appreciated by those skilled in the art, the above embodiments only demonstrate a method for manufacturing a package substrate, which is fully applicable to the manufacturing process of other package substrates including embedded capacitors, for example, it can further stack more circuit layers.

While the foregoing has been with reference to the disclosure of the present invention, it will be appreciated by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the protection scope of the present invention should not be limited to the disclosure of the embodiments, but should include various alternatives and modifications without departing from the invention, which are covered by the claims of the present patent application.

Claims

1. A method of manufacturing a package substrate, comprising:

providing a first laminated structure, wherein the first laminated structure comprises a first metal layer, a second metal layer and a capacitor dielectric layer positioned between the first metal layer and the second metal layer;

patterning the first metal layer of the first laminated structure to form a first circuit layer;

providing a carrier plate, wherein the carrier plate is provided with a first surface and a second surface which are opposite;

the carrier plate includes:

the sacrificial layer, the third metal layer arranged on two opposite surfaces of the sacrificial layer and the fourth metal layer arranged on the surface of the third metal layer;

pressing a first dielectric layer and a patterned first laminated structure on the first surface and the second surface of the carrier;

patterning the second metal layer of the first laminated structure to form a second circuit layer; and

and patterning the fourth metal layer to form a third circuit layer.

2. The method of manufacturing a package substrate of claim 1, further comprising:

and providing a third laminated structure, and laminating a second dielectric layer and the third laminated structure on the second circuit layer, wherein the third laminated structure comprises a fifth metal layer, and the second dielectric layer is positioned between the second circuit layer and the fifth metal layer.

3. The method of manufacturing a package substrate according to claim 2, wherein the third stacked structure further comprises:

a resistive material layer between the second dielectric layer and the fifth metal layer.

4. The method of manufacturing a package substrate of claim 1, further comprising:

removing the sacrificial layer and the third metal layer.

5. The method of manufacturing a package substrate according to claim 2, further comprising:

and forming a plurality of conduction columns in the first dielectric layer, the second dielectric layer and the capacitor dielectric layer, wherein the conduction columns conduct at least two of the first circuit layer, the second circuit layer, the fourth metal layer and the fifth metal layer.

6. The method of manufacturing a package substrate according to claim 3, further comprising:

and patterning the fifth metal layer and the resistance layer material to form a fourth circuit layer and a resistance layer thereof.

7. The method of manufacturing a package substrate of claim 1, further comprising:

and forming a solder mask layer on the surface of the packaging substrate.