200924248 κ 六、發明說明： "[優先權之主張] β本申請案主張於20〇7年9月28日向韓國智慧財產局 所提出之韓國專利申請案第號和於2刪年$ 月1日提出之％國專利中請案第細8_編63號之優先權， 該等案揭示之内容併人本案作為參考。 【發明所屬之技術領域】 、轉明係關於細微圖案形成方法，詳言之，係關於製 „微圖案以改善光效率之半導體發光裝置之方法。 【先前技術】 •—⑨正製造各種的半導體裝置，譬如基於半導體之發光 •二極體、雷射二核體、光二極體和電晶體。 ，於特定的錢，半導體裝置要求具有細微圖案譬如 ;、疋區域之週期的/非週期的圖案。此種細微圖案可藉由 已知的_製程_半導體表面而形成。 、 、，、/氮化物半導體發光二極體之情況，由於外部與氮化 物半導體之間折射率之差異，光選取效率受到限制。為了 克服此限制，可以在氮化物半導體發光二極體之表面形成 細微圖案結構。 -s处正積極地研究具有細微週期的格柵圖案之光子之結 、晶結構（Ph〇t〇nk crystal structure )，以便改善半導體發光 裝置之照度（luminance)。而且，類似的細微格柵圖案藉 由使用表面電襞共振原理而被採用為改善照度之方法。 …丨而，用於此圖案化製程之钱刻製程在形成細微圖案 4 94476 200924248 於半導體方面具有限制。該等限制依照使用之钱刻方法而 改變。 例如，反應性離子#刻（reactive ion etching，RIE) 和誘發耦合電漿反應性離子蝕刻（inductively c〇upled plasma reactive ion etching，ICP_RIE)之乾蝕刻能夠確保 精確和可重現的圖案，因為其允許功率控制和具有非等向 性。然而，乾射j具有半導體表面之性質於乾_期間由 於離子或中性原子之物理的轟擊而容易劣化之限制。即使 其為非p型GaN之薄膜的材料被沉積在卩型GaN層上， 然後該薄膜使用乾蝕刻來圖案化，亦很難防止損宝設置在 被去除薄膜部分之p型GaN層。 第1圖之實線表示在電極形成於P型GaN表面之前 藉由使用鹵素氣體之ICP而故意損害之氮化物半導體 發光裝置之電流-電壓（I_V)特性。由‘χ，指示之虛線表示 扣害發生之前氮化物半導體發光裝置之Ι-ν特性，其^由 ‘♦，指示之未損害氮化物LED不同。於由料 = 化物半導體發域置中，電流開始從低電愿流動。'二而， 此電流不是由正以子再結合產生的電流， : 生光之漏電流。疋戍十不產 曰尋，種方法從乾_則起之損害恢復結 曰曰之原來狀心〜而，因為氮空缺，？型G咖 蝕刻製程期間其導電率類型經歷改變成n型。^ ； 因，使用一般之後製程（p〇st_pr〇cessi ) ; 損害的結晶。導電率類―面二 94476 5 200924248 命的缺陷。 不像乾蝕刻，濕蝕刻對譬如p型GaN之半導體表面 不造成損害。然而，濕蝕刻亦具有限制，其在於氮化物單 一結晶之特定平面（例如，c平面）幾乎完全不被I虫刻， 而很難達成正確地圖案化。而且，若蝕刻深度過度，則薄 膜之頂端被完全去除，而因此使用為遮罩之光阻層被分離。 【發明内容】 本發明之態樣提供一種形成細微圖案之方法，其能夠 於乾蝕刻後，由使用{ 0001 } c平面六角形半導體結晶之 水平蝕刻特性之乾蝕刻造成的損害面積減至最小。 本發明之態樣亦提供一種製造具有細微圖案之半導 體發光裝置之方法，該發光裝置藉由使用形成細微圖案之 方法而改善光輸出。 依照本發明之態樣，提供一種形成細微圖案之方法， 包含：提供c平面六角形半導體結晶；形成具有預定圖案 之遮罩於該半導體結晶上；使用該遮罩而乾蝕刻半導體結 晶以在該半導體結晶上形成第一細微圖案；以及濕蝕刻包 含該第一細微圖案之該半導體結晶以在水平方向擴展該第 一細微圖案而形成第二細微圖案。以該濕蝕刻該半導體結 晶而獲得的該第二細微圖案具有底表面和侧壁，該底表面 和側壁分別具有唯一的結晶平面。 可由會被乾蝕刻損害之P型氮化物半導體形成半導體 結晶基板。 因為底表面為c平面在濕蝕刻中幾乎完全不會被蝕 6 94476 200924248 刻’、，此於形成第-細微圖案獲得的底表面也許具有與於 形成第二細微圖案獲得的底表面有相同的c平面。 遮罩之圖案可以包含形成於半導體結晶之〈u_2〇〉 方向並沿著〈1-100〉方向配置之複數個 細微圖案之侧壁可以具有m平面。 莱而該第- 遮罩之圖案可以包含形成於半導體結晶之〈1_100〉 方向並沿著〈11-20〉方向配置之複數個線圖案。於現行實 施方式中，當祕刻進—步進行時，線圖案於他們的表面 Z以變成不規則的，錢可以部分變薄而因此提供為點圖 射。再者，若需要的話，甚至虛線圖案可藉由執行額外的 别王㈣和去除。結果，此_方法可使用為控 制半¥體層厚度之方法。 Μ之圖案可包含複數個細孔，而第二細微圖案可包 3稷數個六角形細孔。孔.之内壁可以具有結晶平面，該平 :經過濕蝕刻（其為第二蝕刻製程)之時間而改變。形成 微圖案可包含執行濕侧，譬如第二細微圖案之側 二：::面組件和S平面組件。而且，藉由連續繼 二π:壁可以包含，組件，其更穩定和能夠 第二細微圖案可以具有柱狀結構。 根據需要’可以在去除遮罩之前或之後形成第二細微 +赞明之另 — 怨俅，提- 置之方法，該半導體發光裝置能 製造半導體發光裝 面電漿共振原理而 94476 7 200924248 有利地應用於需要具有細微圖案或結構之光子之結晶結 ，構。 °曰曰、σ 該製造半導體發光裝置之方法，包含：提供包含第一 導電率類型半導體層、第二導電率類型半導體層、和爽於 該第導電率類型半導體層和該第二導電率類型半導體層 之間之主動層之多層之半導體結構；在該多層之半導體社 構之第二導電率類型半導體層上形成具有預定圖案之^ 罩，藉由使用遮罩乾I虫刻該第二導電率類型半導體層以在 該第二，電率類型半導體層上形成第一細微圖案；濕钱刻 包含該第-細微圖案之該第二導電率類型半導體層以擴展 .於水平方向之該第-細微圖案，以形成第二細微圖案；以 、及f該遮罩被去除狀態形成第一電極和第二電極’該第一 和第-電極分別與該第—和第二導電率類型半 接。該第二導電率類型半導體層可以是c平面六角料^ 體結晶’而獲自該渴钱刻兮裳_ 第-细微= 導電率類型半導體層之該 ^面相案可以具有分別具有唯一結晶平面之底表面和 形成於該第二導電率類型半導體層之該第二 案可以❹為光子之㈣結構之# 由Ρ類型氮化物半導體層之表 =主動層之先經 之結晶結構藉由衰減由卵外側時’該光子 折射率㈣起之總反射效果而H被封別（咖細）之低 對於較佳之光子之善f取效率。 含該第二細微圓案之該層可爾在包 钕电率類型半導體層上。舉例 94476 8 200924248 而言，可以形成光傳輸金屬層或譬如IT〇之光傳輸氧化物 層。 。奴使用表面電漿共振原理形成結構，該形成第二電極 可以包含形成高度反射的金屬層（譬如銀）於包含該第二 、’、田微圖案之該第二導電率類型半導體層上。該高度反射的 金屬層可以具有多層結構。 該第一導電率類型半導體層可以具有厚度允許由再 結合電洞·電子對所產生的能量注人至絲層以激發表面 電漿於該第二導電率類型半導體層和該高度反射的金屬層 之間之介面。 • 該第二導電率類型半導體層可以具有大約50nm或少 .於該第一細彳政圖案和該主動層之間之厚度。 、依,¾本發明之製造方法，可以有利地應用於包含氮化 物半‘體之多層半導體之發光裝置。於此情況，該第二導 電率類型半導體層可以是p型氮化物半導體層。 【實施方式】 見將二照所附圖式詳細說明本發明之範例實施例。 第2A至2D圖為剖面圖，說明依照本發明之範例實 施例使用水平濕姓刻之細微圖案形成方法。 — 如第2A圖中所不，依照現行實施例之細微圖案形成 -方法開始以提供£平面六角形半導體結晶U。 /半導體結晶11可以是譬如GaN或另-種已知於六角 形系，之半導體之氮化物半導體。尤其是，半導體基底n 可、疋P里氮化物層，其易受到乾钱刻之損害。依照現行 9 94476 200924248 實施例，使用具有上表面提供為C平面{ 0001 }之六角形 半導體結晶。 其後，如第2B圖中所示，具有預定圖案之遮罩18形 成於半導體結晶11上。 遮罩18可以是光阻圖案。於此製程中，具有所希望 圖案之遮罩18可以藉由施加光阻於半導體結晶11之上表 面，然後於其上執行一般之微影術製程或全像攝影微影術 製程而形成。 若需要的話圖案可以是週期性的圖案，但是用於本發 明之遮罩18之圖案可以改變。舉例而言，圖案譬如可以是 一維之線圖案和二維之三角形或矩形格柵圖案、具有低短 範圍週期性和高長範圍週期性之半週期性圖案之週期性圖 案，或者非週期性圖案。 即使保持週期性或半週期性，圖案之尺寸和形狀可以 改變。此是因為於使用遮罩之乾蝕刻後，執行非等向性濕 蝕刻製程（於本發明中水平方向）。現在將參照第2C和 2D圖作更詳細說明。 結合了主要的乾蝕刻和次要的濕蝕刻之混合蝕刻製 程，使用於現行細微圖案形成製程。 參照第2C圖，半導體結晶11藉由使用遮罩18而乾 蝕刻，由此形成第一細微圖案P1。於現行製程中藉由乾蝕 刻該半導體結晶11達對應於遮罩18之開口之寬度W1之 寬度，以及達半導體結晶11之預定的深度dl而獲得該第 一細微圖案P1。得自該乾蝕刻之該第一細微圖案P1之深 10 94476 200924248 度幾乎等於第2D圖之最終細微圖案P2之深度。然而，該 第一細微圖案P1之寬度W1 (或該圖案之尺寸）小於最終 細微圖案P2之寬度。現將參照第2D圖而作更詳細的說明。 如上所述，於現行製程中，用於此乾蝕刻之離子和中 性原子在半導體結晶11之該第一細微圖案P1之整個表面 之上造成損害面積D。也就是說，由乾蝕刻而直接暴露結 晶之面積D而因此受損係不僅出現於底表面，而且亦於該 第一細微圖案P1之側壁處。然而，此可藉由第2D圖之蝕 刻製程而降至最小。 於第2D圖之製程中，包含第一細微圖案P1之半導體 結晶11被濕蝕刻。於此實施例中，於去除遮罩18後執行 濕蝕刻。然而，本發明不限於此種情況，而於濕蝕刻製程 後可去除遮罩18。 濕蝕刻進行於第一細微圖案P1之水平方向，因為其 幾乎完全不影響穩定的c平面。水平濕蝕刻繼續著直到側 壁變成特定的結晶平面為止。因為蝕刻率於特定的晶格平 面明顯降低，因此濕蝕刻可實施具有高的可重現性。 第一細微圖案P1被擴展於其水平方向，而因此可以 變成具有唯一結晶平面之侧壁之第二細微圖案P2。如此一 來，該第二細微圖案P2可以具有等於該第一細微圖案P1 之深度dl之深度d2，和寬於該第一細微圖案P1之寬度 wl之寬度w2。 於此製程中，如第2D圖中所示，可以不產生或去除 由第一細微圖案P1之水平擴展所獲得的新暴露之側璧和 11 94476 200924248 底表面之知害面積。於是，損害面積d，僅維持對應於第— 細微圖案pi之底表面之面積。 於疋，第二細微圖案P2可以提供最小化損害面積D, 與整個暴露面積之比。藉由使用此原理，可以控制遮罩圖 * °又飯刻製程以便進—步降低損害面積之比。 特別地’藉由減少遮罩18之寬度W1和增加第一细 Z㈣之深度以’可以增加由第二細微圖案P2獲得的 表面：ΐ積同時減少對應於第一細微圖案P1之損害底部 案整少損害面積D，相關於該第二細微圖 由乾_所造並因此能夠實質上防止譬如 Μ士，成 積所引起之電性能劣化之影響。 面Τ Λ、?υ’由乾㈣所獲得的第—細微®f之底表 面可以是c平面 m口系《展表 千面與丰¥體結晶之上表面相同。 口為面為非常穩定之此 圖案之側壁正被濕餘列日士，甘^因此甚至虽第-細微 因此，能夠看到g X T表㈣乎完全不被蝕刻。 心= Ρ2之深度由第-細微圖案 而精確控制。、㈤、、'、、田微圖案之深度能夠透過乾钱刻 而且’依照本發明之招）_…^ 側壁變成特定結晶平面時水’當由濕，刻暴露之 率。例如，於氮化物社曰“〆1具有非常低的钱刻 ⑽U、m平面u_i(；曰曰之情況，側壁可以是S平面 如此-來，因為濕辦=面Λ102}。 J衣私為自行終止製程，其自己 94476 12 200924248 k 停止，因此在確保製程均勻性或高可重現性方面具有很大 ' 的優點。 濕蝕刻之結晶方向以及遮罩圖案在獲得本發明中最 終圖案之形狀和尺寸方面扮演了重要的角色。可以藉由形 成在待蝕刻之半導體結晶上之遮罩圖案而選擇結晶方向。 也就是說，因為濕蝕刻率依照結晶平面而改變，因此 可根據哪個結晶平面被暴露於由遮罩圖案所暴露之結晶圖 案之側壁，而獲得各種圖案（參看實施例ΙΑ、1B)。 '尤其是，本發明人發現可以藉由乾蝕刻然後濕蝕刻其 於水平方向形成粗圓孔，而獲得六角形孔之細微圖案。細 微圖案具有次微米之尺寸，以及可以具有相關於鄰接側形 成120°銳角之各側之六角形的形狀（參看實施例1C)。 ’ 此可考慮為本發明之獨有特性，沒有其他的相關技術半導 體蝕刻方法已經能達成。 再者，如上述提及的，依照濕蝕刻於六角形形狀暴露 之各結晶平面可以不同。尤其是，因為側壁之結晶平面依 . 照濕蝕刻狀況可以傾斜，因此可以提供具有覆蓋輔助沉積 電極材料之側壁。 現將更詳細說明本發明之各種實施例之操作和效果。200924248 κ VI. Invention Description: "Priority Claims] β This application claims to be filed with the Korea Intellectual Property Office on September 28, 2007, and the Korean Patent Application No. 1 and the second year of the month. The priority of the proposed patent in the National Patent No. 8_63, the content of which is disclosed in this case is for reference. [Technical Field to Be Described] The invention relates to a method for forming a fine pattern, and more particularly to a method for fabricating a semiconductor light-emitting device for improving light efficiency by a micro pattern. [Prior Art] • 9 is manufacturing various semiconductors Devices, such as semiconductor-based luminescence • diodes, laser dinuclear bodies, photodiodes, and transistors. For specific money, semiconductor devices are required to have fine patterns such as; periodic/non-periodic patterns of 疋 regions Such a fine pattern can be formed by a known _process_semiconductor surface. In the case of , , , , / nitride semiconductor light-emitting diodes, light selection efficiency due to the difference in refractive index between the external and nitride semiconductors In order to overcome this limitation, a fine pattern structure can be formed on the surface of the nitride semiconductor light-emitting diode. The junction of the photon of the grating pattern having a fine period is actively studied at -s (Ph〇t〇 Nk crystal structure ) in order to improve the luminance of the semiconductor light-emitting device. Moreover, a similar fine grid pattern is used. The principle of surface electric resonance is adopted as a method for improving illuminance. ... However, the engraving process for this patterning process has limitations in forming a fine pattern 4 94476 200924248 in terms of semiconductors. For example, reactive ion etching (RIE) and dry etching of inductively c〇upled plasma reactive ion etching (ICP_RIE) ensure accurate and reproducible patterns. Because it allows power control and is anisotropic. However, the dry shot j has the property that the properties of the semiconductor surface are easily degraded during the dry _ due to the physical bombardment of ions or neutral atoms. Even if it is non-p-type GaN The material of the film is deposited on the 卩-type GaN layer, and then the film is patterned by dry etching, and it is also difficult to prevent the damage layer from being disposed on the p-type GaN layer of the removed film portion. The solid line of FIG. 1 indicates the electrode. The current-voltage (I_V) characteristic of the nitride semiconductor light-emitting device intentionally damaged by the ICP using a halogen gas before being formed on the surface of the P-type GaN. 'χ, the indicated dashed line indicates the Ι-ν characteristic of the nitride semiconductor light-emitting device before the occurrence of the deduction, which is indicated by '♦, indicating that the nitride LED is not damaged. In the case of the material semiconductor, the current starts. From low electricity, it is willing to flow. 'Secondly, this current is not the current generated by the recombination of the child, the leakage current of the raw light. The tenth is not produced, the method is to recover the damage from the dry_ The original shape of the crucible is ~, because of the nitrogen vacancy, the conductivity type of the type G coffee etching process is changed to n type. ^; Because, the general post-process (p〇st_pr〇cessi) is used; the crystal of damage. Conductivity class - face two 94476 5 200924248 Defects of life. Unlike dry etching, wet etching does not cause damage to the surface of a semiconductor such as p-type GaN. However, wet etching also has a limitation in that a specific plane (e.g., c-plane) of a single crystal of nitride is hardly etched by I, and it is difficult to achieve proper patterning. Moreover, if the etching depth is excessive, the tip of the film is completely removed, and thus the photoresist layer used as a mask is separated. SUMMARY OF THE INVENTION A aspect of the present invention provides a method of forming a fine pattern capable of minimizing damage area caused by dry etching using a horizontal etching characteristic of { 0001 } c-plane hexagonal semiconductor crystal after dry etching. Aspects of the invention also provide a method of fabricating a semiconductor light-emitting device having a fine pattern that improves light output by using a method of forming a fine pattern. According to an aspect of the present invention, a method of forming a fine pattern is provided, comprising: providing a c-plane hexagonal semiconductor crystal; forming a mask having a predetermined pattern on the semiconductor crystal; and dry etching the semiconductor crystal using the mask Forming a first fine pattern on the semiconductor crystal; and wet etching the semiconductor crystal including the first fine pattern to expand the first fine pattern in a horizontal direction to form a second fine pattern. The second fine pattern obtained by the wet etching of the semiconductor crystal has a bottom surface and side walls each having a unique crystal plane. The semiconductor crystal substrate can be formed of a P-type nitride semiconductor which is damaged by dry etching. Since the bottom surface is a c-plane which is hardly etched at all in the wet etching, the bottom surface obtained by forming the first fine pattern may have the same surface as that obtained by forming the second fine pattern. c plane. The pattern of the mask may include a plurality of side walls of the plurality of fine patterns formed in the <u_2〇> direction of the semiconductor crystal and arranged along the <1-100> direction, and may have an m-plane. The pattern of the first-mask may include a plurality of line patterns formed in the <1_100> direction of the semiconductor crystal and arranged along the <11-20> direction. In the current implementation, when the secret is advanced, the line patterns are irregular on their surface Z, and the money can be partially thinned and thus provided as a dot pattern. Furthermore, even a dotted pattern can be performed by performing additional kings (4) and removing if necessary. As a result, this method can be used to control the thickness of the body layer. The pattern of the enamel may comprise a plurality of pores, and the second fine pattern may comprise a plurality of hexagonal pores. The inner wall of the hole may have a crystal plane which changes by the time of wet etching which is the second etching process. Forming the micropattern can include performing a wet side, such as a side of the second fine pattern: a::: face component and an S-plane component. Moreover, by successively following two π: walls may comprise, components which are more stable and capable of having a second fine pattern which may have a columnar structure. According to the need, the second subtle + praising can be formed before or after the mask is removed, and the semiconductor light-emitting device can manufacture the semiconductor light-emitting surface plasma resonance principle. 94476 7 200924248 is advantageously applied. A crystal junction of photons having a fine pattern or structure is required. The method of manufacturing a semiconductor light-emitting device, comprising: providing a semiconductor layer including a first conductivity type, a semiconductor layer of a second conductivity type, and a semiconductor layer of the first conductivity type and the second conductivity type a semiconductor structure having a plurality of layers of active layers between the semiconductor layers; forming a mask having a predetermined pattern on the second conductivity type semiconductor layer of the multilayer semiconductor structure, and etching the second conductive layer by using a mask Rate-type semiconductor layer to form a first fine pattern on the second, electric-rate type semiconductor layer; wet-etching the second conductivity type semiconductor layer including the first-fine pattern to expand the first in the horizontal direction - Finely patterning to form a second fine pattern; forming a first electrode and a second electrode with the mask removed. The first and first electrodes are respectively half-connected to the first and second conductivity types. The second conductivity type semiconductor layer may be a c-plane hexene crystal, and the surface layer obtained from the thirst-small-conductivity-type conductivity semiconductor layer may have a unique crystal plane. The bottom surface and the second case formed on the second conductivity type semiconductor layer may be referred to as a photonic (four) structure. The surface of the nitride semiconductor layer is represented by the surface of the active layer, and the crystal structure of the active layer is attenuated by the egg. On the outside, the total reflection effect of the photon refractive index (4) and the lowering of H (the fineness of the coffee) are effective for the better photon. The layer containing the second fine round is on the cladding type semiconductor layer. For example, 94476 8 200924248, a light transmitting metal layer or a light transmitting oxide layer such as IT can be formed. . The slave forms a structure using a surface plasma resonance principle, and the forming of the second electrode may include forming a highly reflective metal layer (e.g., silver) on the second conductivity type semiconductor layer including the second, ' The highly reflective metal layer can have a multilayer structure. The first conductivity type semiconductor layer may have a thickness that allows energy generated by the recombination hole/electron pair to be injected into the wire layer to excite the surface plasma to the second conductivity type semiconductor layer and the highly reflective metal layer The interface between them. • The second conductivity type semiconductor layer may have a thickness of about 50 nm or less between the first fine plaque pattern and the active layer. According to the manufacturing method of the present invention, it can be advantageously applied to a light-emitting device comprising a multilayer semiconductor of a nitride half body. In this case, the second conductivity type semiconductor layer may be a p-type nitride semiconductor layer. [Embodiment] An exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. 2A through 2D are cross-sectional views illustrating a method of forming a fine pattern using a horizontal wetness in accordance with an exemplary embodiment of the present invention. - As in Figure 2A, the fine pattern formation process according to the current embodiment begins with the provision of a planar hexagonal semiconductor crystal U. The / semiconductor crystal 11 may be, for example, GaN or another nitride semiconductor of a semiconductor known in the hexagonal system. In particular, the semiconductor substrate n can be a nitride layer in the 疋P, which is susceptible to damage. According to the current embodiment of 9 94476 200924248, a hexagonal semiconductor crystal having an upper surface provided as a C-plane { 0001 } is used. Thereafter, as shown in Fig. 2B, a mask 18 having a predetermined pattern is formed on the semiconductor crystal 11. The mask 18 can be a photoresist pattern. In this process, a mask 18 having a desired pattern can be formed by applying a photoresist to the surface above the semiconductor crystal 11 and then performing a general lithography process or a holographic lithography process thereon. The pattern may be a periodic pattern if desired, but the pattern used for the mask 18 of the present invention may vary. For example, the pattern may be, for example, a one-dimensional line pattern and a two-dimensional triangular or rectangular grid pattern, a periodic pattern of a semi-periodic pattern having a low short-range periodicity and a high-long-range periodicity, or a non-periodic pattern. The size and shape of the pattern can be changed even if it is maintained periodically or semi-periodically. This is because an anisotropic wet etching process (horizontal direction in the present invention) is performed after dry etching using a mask. A more detailed description will now be made with reference to Figures 2C and 2D. A hybrid etching process that combines a primary dry etch and a secondary wet etch is used in the current fine patterning process. Referring to Fig. 2C, the semiconductor crystal 11 is dry etched by using the mask 18, thereby forming the first fine pattern P1. The first fine pattern P1 is obtained by dry etching the semiconductor crystal 11 to a width corresponding to the width W1 of the opening of the mask 18 and a predetermined depth dl of the semiconductor crystal 11 in the current process. The depth of the first fine pattern P1 from the dry etching is 10 94476 200924248 degrees which is almost equal to the depth of the final fine pattern P2 of the 2D image. However, the width W1 (or the size of the pattern) of the first fine pattern P1 is smaller than the width of the final fine pattern P2. A more detailed description will now be made with reference to FIG. 2D. As described above, in the current process, ions and neutral atoms used for the dry etching cause damage area D over the entire surface of the first fine pattern P1 of the semiconductor crystal 11. That is, the area D of the crystallized crystal is directly exposed by dry etching so that the damaged portion is not only present on the bottom surface but also at the side wall of the first fine pattern P1. However, this can be minimized by the etching process of Figure 2D. In the process of Fig. 2D, the semiconductor crystal 11 containing the first fine pattern P1 is wet etched. In this embodiment, wet etching is performed after the mask 18 is removed. However, the present invention is not limited to this case, and the mask 18 can be removed after the wet etching process. The wet etching proceeds in the horizontal direction of the first fine pattern P1 because it hardly affects the stable c-plane at all. The horizontal wet etching continues until the side walls become a specific crystal plane. Since the etching rate is remarkably lowered on a specific lattice plane, wet etching can be performed with high reproducibility. The first fine pattern P1 is expanded in its horizontal direction, and thus can become the second fine pattern P2 having the side wall of the unique crystal plane. In this way, the second fine pattern P2 may have a depth d2 equal to the depth d1 of the first fine pattern P1 and a width w2 wider than the width w1 of the first fine pattern P1. In this process, as shown in Fig. 2D, the newly exposed side 由 obtained by the horizontal expansion of the first fine pattern P1 and the immersed area of the bottom surface of 11 94476 200924248 may not be generated or removed. Thus, the area d is damaged, and only the area corresponding to the bottom surface of the first fine pattern pi is maintained. Thereafter, the second fine pattern P2 can provide a ratio of the minimum damage area D to the entire exposed area. By using this principle, it is possible to control the mask map * ° and the meal engraving process in order to further reduce the ratio of damaged areas. In particular, 'by reducing the width W1 of the mask 18 and increasing the depth of the first thin Z (four) to 'can increase the surface obtained by the second fine pattern P2: hoarding while reducing the damage to the bottom of the first fine pattern P1 The area D is less damaged, and the second micro-picture is made of dry and thus can substantially prevent the deterioration of electrical performance caused by the accumulation of, for example, a gentleman.底 Λ, υ 由 由 由 由 由 由 由 由 由 由 由 由 由 由 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四The mouth is very stable. The side wall of the pattern is being wetted by the Japanese, so even though it is so fine, it can be seen that the g X T table (four) is completely etched. The depth of the heart = Ρ 2 is precisely controlled by the first-fine pattern. , (5),, ',,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, For example, in the nitride society, "〆1 has a very low money engraving (10) U, m plane u_i (; in the case of 曰曰, the side wall can be the S plane so - come, because wet? = face Λ 102}. The process is terminated, and its own 94476 12 200924248 k stops, so it has great advantages in ensuring process uniformity or high reproducibility. The crystal orientation of the wet etching and the mask pattern are obtained in the shape of the final pattern in the present invention. The size plays an important role. The crystal orientation can be selected by the mask pattern formed on the semiconductor crystal to be etched. That is, since the wet etching rate changes according to the crystal plane, it can be exposed according to which crystal plane Various patterns are obtained on the side walls of the crystal pattern exposed by the mask pattern (see Example 1, 1B). 'In particular, the inventors have found that a thick circular hole can be formed in the horizontal direction by dry etching and then wet etching. , obtaining a fine pattern of hexagonal holes. The fine pattern has a submicron size, and may have six sides on each side that form an acute angle of 120° with respect to the abutting side. Shape of the shape (see Example 1C). 'This can be considered as a unique feature of the present invention, and no other related art semiconductor etching method can be achieved. Further, as mentioned above, according to wet etching in a hexagonal shape The respective crystal planes of the exposure may be different. In particular, since the crystal plane of the sidewalls may be tilted according to the wet etching condition, a sidewall having a material covering the auxiliary deposition electrode may be provided. The operation of various embodiments of the present invention will now be described in more detail. And effects.
. 實施例1A 依照現行實施例，具有形成於<11-20>方向並配置 於<1-100>方向線圖案之遮罩形成於c平面GaN半導體 結晶中。線圖案之週期設定大約0.6 //m。其後，執行乾 蝕刻達大約0.1//m之深度，然後去除遮罩（參看第3A圖）。 13 94476 200924248 其後，使用4MKOH水溶液之濕蝕刻執行於大約100 °C經過約10分鐘，然後使用掃描電子顯微鏡（SEM)觀察， 然後進一步執行濕蝕刻大約20分鐘（總共30分鐘）。 執行大約10分鐘濕钱刻後之結果，稩微傾斜之初始 侧壁變成垂直侧壁如第3B圖中所示。因為側壁變成 { 1-100丨平面，其為GaN之相對穩定結晶平面（亦即，m 平面），該側壁於大約20分鐘之額外的濕蝕刻期間不再被 蝕刻。當然，其為穩定c平面之底表·面幾乎未被蝕刻。[Embodiment 1A] According to the current embodiment, a mask having a pattern formed in the <11-20> direction and arranged in the <1-100> direction line is formed in a c-plane GaN semiconductor crystal. The period of the line pattern is set to be approximately 0.6 //m. Thereafter, dry etching is performed to a depth of about 0.1 / / m, and then the mask is removed (see Fig. 3A). 13 94476 200924248 Thereafter, wet etching using a 4 M KOH aqueous solution was performed at about 100 ° C for about 10 minutes, and then observed using a scanning electron microscope (SEM), and then wet etching was further performed for about 20 minutes (total 30 minutes). As a result of performing the wet etching for about 10 minutes, the initial sidewall of the micro-tilt becomes a vertical sidewall as shown in Fig. 3B. Since the sidewall becomes a {1-100丨 plane which is a relatively stable crystalline plane of GaN (i.e., the m-plane), the sidewall is no longer etched during an additional wet etch of about 20 minutes. Of course, the bottom surface of the stable c-plane is hardly etched.
依照現行實施例，能夠看出由乾蝕刻所造成之損害面 積從側壁和底表面部分去除，能夠獲得清潔的結晶平面。 該結晶平面可以確保於半導體裝置中優越的電性接觸。 實施例1B 依照本實施例，相似於實施例1A，具有複數個線圖 案（例如：大約0.6 // m)之遮罩形成於c平面GaN半導 體結晶上。在形成方向和配置方向上有差異。也就是說’ 依照現行實施例，複數個線圖案形成於< 1-100>方向和配 置於< 11-20〉方向。其後，執行乾蝕刻達大約0.1 //m深 度，然後去除遮罩（參看第4A圖）。 其後，使用4MKOH水溶液之濕蝕刻執行於大約100 °C經過約10分鐘，然後使用SEM觀察所得到的結構（參 看第4B圖）。其後，在其上執行濕蝕刻大約20分鐘（總 共30分鐘），使用SEM觀察所得到的結構（參看第4C 圖）。其後，額外地執行濕蝕刻大約20分鐘（總共50分 鐘），並使用SEM觀察所得到的結構（參看第4D圖）。 14 94476 200924248 祕. 圖案相似的形式（參看第3Α阁、 然而，如第4B圖令所示，者卜见、、/有弟3入圖）。 圖案之寬度增加（亦g|7 田7、’濕蝕刻繼續進行時， 曰刀OF即’圖案結構 蝕刻製程進行大約3〇分 又，斩漸減力。當 線性配置如第化圖中所 米 木又成點圖木， 完全的平括車品P 刻進一步進行時，保持 圖宰二第4〇圖）。此是因為經過時間後 刻於<u-2°>方向執行相較於 八他穩疋、.、。日日平面有相對高的蝕刻率。 述’依照現行實施例，相提供改變長度和寬 又，、有相對小損害之一維格柵和點圖案。 、、當從現行實施例看到（具有<Μ〇〇>方向格栅之水 :/’’’、，刻）’可能去除c平面（其通常未被濕钱刻）至預 疋的厚度。也就是說’依照本發明，乾姓刻執行於小面積 以形成溝槽，而濕關被用為後續製程。亦可能藉由控制 初始乾钱刻之餘刻深度而減少原來蟲晶層之厚度至所希望 之範圍。 尤其是，P型GaN層之表面因為損害而不能被乾蝕 亥】亦因為其為c平面而不能被濕钱刻。然而，藉由使用 依照現行實施例之製程，當P型GaN層之損害部分被最小 化時其厚度能夠減少。 實施例1 q 不像前面的實施例1A和1B，現行實施例使用三維圖 案。各具有尺寸大約〇·3 //m之複數個圓形遮罩形成在c 94476 15 200924248 ‘平面GaN半導體結晶上。複數個圓形遮罩圖案垂直和水平 • 配置於大約0.6/z m週期。 其後，執行乾蝕刻達大約0.1 A m深度，然後去除遮 罩。其後，使用4MKOH水溶液之濕蝕刻執行於大約100 °C經過約10分鐘，然後使用SEM觀察所得結構。如第5 圖中所示，能夠看到形成譬如柱狀結構（直徑：大約130 // m)之三維圖案。According to the current embodiment, it can be seen that the damage area caused by the dry etching is partially removed from the side wall and the bottom surface, and a clean crystal plane can be obtained. This crystal plane can ensure superior electrical contact in a semiconductor device. Embodiment 1B In accordance with this embodiment, similar to Embodiment 1A, a mask having a plurality of line patterns (e.g., about 0.6 // m) is formed on the c-plane GaN semiconductor crystal. There are differences in the direction of formation and the direction of configuration. That is, according to the current embodiment, a plurality of line patterns are formed in the <1-100> direction and in the <11-20> direction. Thereafter, dry etching is performed to a depth of about 0.1 //m, and then the mask is removed (see Fig. 4A). Thereafter, wet etching using a 4 M KOH aqueous solution was carried out at about 100 ° C for about 10 minutes, and then the obtained structure was observed using SEM (see Fig. 4B). Thereafter, wet etching was performed thereon for about 20 minutes (total for 30 minutes), and the obtained structure was observed using SEM (see Fig. 4C). Thereafter, wet etching was additionally performed for about 20 minutes (total 50 minutes), and the obtained structure was observed using SEM (see Fig. 4D). 14 94476 200924248 Secret. Patterns of similar form (see section 3, however, as shown in Figure 4B, see, and / have a brother 3 into the map). The width of the pattern is increased (also g|7 Tian 7, 'When the wet etching continues, the OF OF 即 即 ' pattern structure etching process is about 3 又 and then gradually reduced. When the linear configuration is as shown in the figure It is also a point figure wood, and when the complete flat car P is further engraved, keep the figure of the second figure. This is because the execution of the time in the <u-2°> direction is better than that of the eight. The day-to-day plane has a relatively high etch rate. According to the current embodiment, the phase provides a change in length and width, and a relatively small damage one-dimensional grid and dot pattern. As seen from the current embodiment (water with a <Μ〇〇> direction grid: /''', engraved) 'may remove the c-plane (which is usually not wet-wet) to pre-emptive thickness. That is to say, according to the present invention, the dry name is performed on a small area to form a groove, and the wetness is used as a subsequent process. It is also possible to reduce the thickness of the original insect layer to the desired range by controlling the depth of the initial dry money. In particular, the surface of the P-type GaN layer cannot be dry-etched due to damage, and because it is a c-plane, it cannot be wet-etched. However, by using the process according to the current embodiment, the thickness can be reduced when the damaged portion of the P-type GaN layer is minimized. Embodiment 1 q Unlike the foregoing Embodiments 1A and 1B, the current embodiment uses a three-dimensional pattern. A plurality of circular masks each having a size of approximately 〇·3 //m are formed on c 94476 15 200924248 'planar GaN semiconductor crystals. Multiple circular mask patterns are vertical and horizontal • Configured at approximately 0.6/z m cycles. Thereafter, dry etching is performed to a depth of about 0.1 A m, and then the mask is removed. Thereafter, wet etching using a 4 M KOH aqueous solution was performed at about 100 ° C for about 10 minutes, and then the obtained structure was observed using SEM. As shown in Fig. 5, a three-dimensional pattern such as a columnar structure (diameter: about 130 // m) can be seen.
實施例1D 依照現行實施例，三維圖案使用於前面實施例1C 中，但是各具有大約100 nm尺寸之複數個圓孔之遮罩形 成於c平面GaN半導體結晶上。該複數個圓孔以大約0.5 /zm週期以垂直和水平方式配置於其間。Example 1D According to the current embodiment, a three-dimensional pattern was used in the foregoing Example 1C, but a mask each having a plurality of circular holes having a size of about 100 nm was formed on the c-plane GaN semiconductor crystal. The plurality of circular holes are disposed between them in a vertical and horizontal manner with a period of about 0.5 /zm.
藉由使用遮罩乾蝕刻（大約0.1 #m)執行於c平面 GaN表面，由此形成粗糙圓孔圖案，然後去除遮罩（參看 第6A圖）。於形成圓孔圖案後，使用4MKOH水溶液之 濕蝕刻執行於大約108 °C經過約30分鐘。如第6圖中所 示，各具有六角形孔，該六角形孔之各侧平行於{ 1-1〇〇丨 m平面之細微圖案形成後，該等細微圖案不再被蝕刻。 實施例1E . 現行實施例相似於前面的實施例1D，除了各最終孔 的直徑製得較大以便輔助觀察於結晶平面中於最終孔之側 壁的改變。於現行實施例中，該等孔的週期相同於前面的 實施例1D，但是孔的直徑製得較大。 得自於水平濕蝕刻（100 °C，4MKOH水溶液）之六 16 94476 200924248 角形孔段被攝取為SEM影像a圖 約1〇分鐘之紝果，&锫％ 團員不濕蝕刻經過大 果。 果而第7B圖顯示_經過40分鐘之結 所得結果是，當濕_繼續進行時，由 的面積（該s平面相對較少 十面所佔據 n %疋）於孔之側壁減少，；a τ所佔據的面積增加。詳言之，從第7A二;:由 刻繼續進行時該5平面漸漸 卞曲但疋當蝕 :面。 十曲新漸地改變成1*平面，然後成。平 、孔之段經過—段時間祕刻後觀察的結果 •疋此夠看出當濕蝕刻繼續進行時，由初妒y鈕Μα θ 綠改k直到穩疋的結日日日平面漸漸暴露為止 孔之内部側壁之結晶平面可以由其為底表面ς 0〇n C平面和{ Hoi } s平面、丨 _ 、， { 1-1Π0 I 0丨扭平面、 • r平面等組合構成。因為濕_不進行平面 y則孔之深度不改變。然而，可以假設若底表面且有 、、，田微不平坦和傾斜，制為水平侧操作能將他們去除。 如上所述，至於依照本發明獲得的細微圖案，由水 ㈣所暴露之結晶平面為由去除由乾钱刻所損害之部分所 ，得的清潔的平面。於是，當電接觸層形成於結晶平面時， 能確保優越的歐姆接觸。而且，當沉積電極材料時，能藉 由根據結晶平面調整祕晶平面之斜度而改善接觸特性。9 細微圖案形成製程可以廣泛應用於形成各種半導體 裝置之功成圖案。尤其是，其可以有利地應用於形成圖案 94476 17 200924248 用來改善半導體發光裝置之光效率 — 關於氮化物半導體發光裝置8G第8A圖之貫施例拍 參照第8A圖，氮化物半導結晶之應^例子。 基板81，而n型氮化物半導體層& 監寶石 化物半_ 85依序地形成於”石和Ρ型氮 而且，氮化物半導體發光裝 和ρ側電極_側電極 接至η型氮化物半導體肩 極89b 7刀別電性連 週期的細微圖案P3形成:以化物半導體層85。 上。細微圖案”可以透過參考第P2A型氣化物半導體層85 獲得(實施例1D)。也就是說: 明之製程 型孔可以週期性方式配置。 弟8B圖中所示，六角 依照現行實施例，如第8八和 :87進一步形成於包含週期性細孔圖荦=光傳輸 半導體層8S上。光声 圖案朽之㈣氮化物 歐姆接觸之任何材料形Γ。例如，^光傳輸朗時確保 光傳=屬層或譬如IT0之光傳輪氧=譬如―之 更少。若二3=導體層，之厚度可以是5。-或 從主㈣β ’物半導體層85之厚度過度地小，亦即， 1〇咖或更多 Ρ型氮化物半導體層85之厚度可以是 用Α :成於Ρ型氮化物半導體層85之細微圖案Ρ3可以使 ”、、子結晶結構，當產生於該主動層84之光經由卩類型 94476 18 200924248 氮化物半導體層85之表面被選取至外侧時，其藉由衰減由 ^ 周圍空氣或密封劑之低折射率所引起之總反射效果而改善 光選取效率。 依照本發明之細微圖案形成方法可執行具有高的精 確度和優越的可重現性，因為甚至當使用濕蝕刻時，根據 結晶平面而改變蝕刻率。如此一來，細微圖案形成製程可 有利地施用於例示於第8A圖中之具有光子結晶結構之氮 化物半導體發光裝置。 雖然於現行實施例中說明為氮化物半導體發光裝 置，但是本發明不限於此，本發明可以應用於使用各種已 知半導體材料之發光裝置。 而且，第8A圖之實施例使用光子結晶結構於特定半 導體層上，譬如P型氮化物半導體層。然而，第8A圖之 實施例甚至當用於光選取之非週期不均勻圖案由不同的材 料形成時，可有利地應用於使用表面電漿之形成週期性細 微圖案之方法，或用來形成同時保護結晶表面之所希望細 微圖案之方法。 實施例2關聯於具有光子結晶之發光裝置之實驗，和 其結果。 實施例2 依照現行實施例，製造具有主動層之氮化物半導體發 光裝置，該主動層包含具有綠色波長之InGaN多量子井。 至於依照現行實施例製造之發光裝置，具有厚度大約 150 nm之p型GaN層藉由使用具有圓孔之遮罩於相似於 19 94476 200924248 實施例ID之狀況下被乾蝕刻至大約54 nm之厚度，然後 於其上執行濕蝕刻大約經過10分鐘，以形成六角形孔圖 案。其後，相似於第8A圖中所例示構造，譬如ITO之光 傳輸電極氧化物沉積於p型GaN層上作為發光電極層以形 成P側接觸。在其上執行檯面钱刻（mesa-etching )以部分 暴露η型GaN層，並於該暴露之η型GaN層上形成η侧 接觸。 為了確定改善藉由依照本發明方法製造之半導體發 光裝置之電特性和照度，測量依照實施例2之氮化物半導 體發光裝置之電特性和照度。測量所得的結果與參考例 Ref比較顯示於第9和10圖中。參考例Ref為發光裝置之 結果，其中僅銀接觸備設置於P型氮化物半導體層上並且 在其上未形成圖案。 第9圖為顯示依照現行範例實施例半導體發光裝置之 I-V曲線圖。第10圖為顯示相關於依照現行範例實施例氮 化物半導體發光裝置之電流之光輸出。 如第9圖中所示，不像第1圖之氮化物發光裝置，依 照本發明之實施例2所製造之半導體發光裝置具有I-V特 性，其中幾乎沒有由乾蝕刻所造成之損害結晶所引起之漏 電流。相較於參考例Ref，氮化物半導體發光裝置於相同 電流具有較高的電壓，但是此差異不明顯。獲自濕蝕刻之 結晶平面之面積比可以進一步增加，而使得相較於現行實 施例能夠改善接觸電阻，並且能夠達成較佳之電特性。 第10圖為顯示相關於依照本發明之現行實施例製造 20 94476 200924248 之氮化物半導體發光裝置之電流的光輸出。 如第10圖中所示，能夠看出相較於參考例Ref，依照 現行實施例之氮化物半導體發光裝置因為光子結晶之擴散 影響達成於350 mA照度增加大約24%。也就是說，透過 依照本發明之蝕刻製程所製造之光子結晶圖案形成具有精 確的輪廓，而使得於LED晶片中由總反射所局限之光的部 分被繞射行進於允許發射至晶片之外側之角度。此亦能夠 明顯地改善LED之照度。 第11圖為藉由本發明之製造方法獲得之氮化物半導 體發光裝置之側剖面圖，其為表面電漿共振原理之應用例 子。 使用於此應用之表面電漿為發生於金屬薄膜表面之 電子之集體電荷密度振盪。由集體電荷密度振盪所產生之 表面電漿波為沿著金屬和介電質之間邊界表面傳播之表面 電磁波。當表面電漿和主動層之間之耦合發生時，發生於 主動層之自然發射由表面電漿所增加，而由自然發射所產 生光之大部分被激發以產生表面電漿。採用此原理以改善 其效率之半導體發光裝置可以稱之為表面電漿半.導體發光 裝置。 參照第11圖，表面電漿氮化物半導體發光裝置110 藉由焊接安裝在次安裝基板120上。表面電漿氮化物半導 體發光裝置110包含氮化物半導體藍寶石基板1Π、η型氮 化物半導體層112、主動層114和ρ型氮化物半導體層115 依序配置在氮化物半導體藍寶石基板111上。 21 94476 200924248 而且，氮化物半導體發光裝置110包含η侧電極117 ' 和ρ側電極117分別電性連接至η型氮化物半導體層112 和Ρ型氮化物半導體層115。 具有週期性之細微圖案Ρ4形成於ρ型氮化物半導體 層115上。這些細微圖案Ρ4可以是以週期方式配置之六 角型孔圖案，其由參照第2Α至2D圖說明之製程獲得（實 施例1D)。 依照現行實施例，如第11圖中所示，高度反射金屬 層形成為ρ側電極118於包含週期性細孔圖案Ρ4之ρ型 氮化物半導體層115上。此高度反射金屬層可以由具有預 定反射率同時確保歐姆接觸之材料製成。例如，高度反射 金屬層可以由譬如銘、銀、金、絡、錄、錯和銘之單層或 多層形成。 而且，主動層114和高度反射金屬層之間之距離於引 起表面電漿共振非常重要。如此一來，ρ型氮化物半導體 層115被要求具有充分的厚度以允許發射自主動層114之 光激發表面電漿於該ρ型氮化物半導體層115和該高度反 射的金屬層之間之介面。 ρ型氮化物半導體層115之厚度可以少於約50 nm。 . 若ρ型氮化物半導體層115之厚度不足，亦即，從主動層 114至格柵結構之距離過度地短，則漏電流激烈地增加。 基於此原因，ρ型氮化物半導體層115可以具有10 nm或 更大的厚度。 依照現行實施例，表面電漿共振之原理可以使用於發 22 94476 200924248 光裝置以改善發光效率。 於此、且構甲，具有週期性格栅結構之細微圖案p4必 /貝於PiillUb物半導體層115和高度反射的金屬層之二 面處以便再轉換激發的表面電漿減。尤其是，根據^ 自主動層114之波長而決定細微圖案p4之正確間距和尺 關於此點’乾钱刻更適合。然而，如前面說明的，對 於引起表面電§_共振’譬如人射光之波長和材料接觸金屬 之折射率，主動層114和高度反射的金屬層之間之距離在 各種條件中非常重要的。因為距離通常為 50 nm或更少（其 相當短），則由乾蝕刻所引起之對p型氮化物半導體層II5 之損害也許引致嚴重的限制。然而，依照本發明之細微圖 案形成製程能夠將在最終階段保留在細微圖案P4中之損 害部分降至最小。而且，即使使用濕#刻，依照本發明之 細微圖案形成製程能夠達成高度的準確和優良的重現性’ 因為蝕刻率根據結晶平面改變。如此一來，依照本發明之 11 闇中·^ 細微圖案形成製程可以有利地應用於例示於第1 表面電漿氮化物半導體發光裝置。 有含有綠 癯發光装 i^i_3 依照現行實施例，相似於實施例2，製造異 色波長之InGaN多量子井之主動層之氮化物半導 置。 /乾蝕刻所形 依照現行實施例製造之led包含由執打 ip之相 94476 成之六角形孔圖案至深度大約33 nm，係與實施例 23 200924248 似條件下於具有厚度大約66 nm之p型GaN層上使用具有 圓孔之遮罩，然後執行濕蝕刻大約10分鐘。其後，相似於 例示於第11圖中之結構，藉由沉積包含高度反射材料層 (其為於p型GaN層上之銀層）之多層金屬電極而形成p 侧接觸，和藉由執行檯面餘刻以部分地暴露η型GaN層而 形成η侧接觸。 為了檢核依照本發明之方法製造之氮化物半導體發 光裝置之電特性和照度之改善，測量依照實施例3之氮化 物半導體發光裝置之電特性和照度之改善。測量所得的結 果與參考例Ref比較顯示於第12和13圖中。此處，參考 例為包含與實施例3相同之多層金屬電極發光裝置結構而 沒有包含於P型氮化物半導體層上之圖案之結果。 第12圖為顯示依照現行實施例之氮化物半導體發光 裝置之I-V曲線之圖示。第13圖為顯示依照現行實施例有 關氮化物半導體發光裝置之電流之光輸出之圖示。 從第12圖能夠看出，如同從第1圖能夠看出，依照 本發明之實施例3所製造之半導體發光裝置具有I-V特 性，其中幾乎沒有於乾蝕刻時間所產生之漏電流。然而， 在現行實施例之I-V曲線上觀察到稍微不規則的曲線，相 較於一般之氮化物半導體發光裝置現行實施例具有非常薄 的P型氮化物半導體層。 相較於參考例Ref，依照現行實施例之氮化物半導體 發光裝置於相同電流具有幾乎固定的電壓。可藉由增加獲 自濕蝕刻之結晶平面之面積比，而期望相較於現行實施例 24 94476 200924248 有較佳之電特性，並因此改善接觸電阻。 ' 第13圖為顯示依照本發明之實施例3有關氮化物半 導體發光裝置之電流之光輸出之圖示。 從第13圖中能夠看出，相較於參考例Ref，依照現行 實施例之氮化物半導體發光裝置因為表面電漿共振效應而 於350 mA下照度改善大約64%。也就是說，使用依照本 發明之蝕刻製程所製造之細微格栅結構形成具有精確的輪 廓，使得注入至LED晶片内之多量子井之電子-電洞對能 量透過表面電漿之媒介轉換成光，並且該光發射至LED晶 片之外側。 而且，由自行發射而不使用表面電漿作為媒介並且由 總反射所局限所產生之光之部分被繞射以轉變光之傳播方 向至允許發射至晶片之外側之角度。於是，亦能夠明顯改 善發光裝置之照度。 依照本發明，僅最小部分之所希望圖案面積被蝕刻， 然後於水平方向執行濕蝕刻形成表面，而使得由乾蝕刻所 I i 引起之損害降至最小。而且，適當控制結晶方向（圖案形 成方向）和濕蝕刻條件（譬如時間條件），以便能夠確保 細微圖案之高度重現性同時自由地控制細微圖案之高度和 . 尺寸。可以藉由應用此等圖案至光子結晶結構或使用表面 電漿原理之結構而提供具有優越光效率之半導體發光裝 置。 而且，依照本發明之細微圖案之特定幾何形狀係於後 續的濕蝕刻製程期間依照六角形結晶系統而自然形成的。 25 94476 200924248 於疋，細微圖案具有唯一的結晶平面，譬如C平面、m平 面、、S平面、和心平面，於此等平面上幾乎無損害發生、: 因為結晶平面可以直接接觸於半導體發光裝置中之全屬或 導電氧化物之電極層’因此於形成？型歐姆接觸更呈優點。 雖然本發明已關於某些範例實施例作了顯示和說 明’但是熟悉此項技術者將了解其中可作各種修釋和改變 产而不會偏離由所㈣請專利範圍㈣義之本發明之精神和 範圍。 【圖式簡單說明】 由以上之詳細說明，配合所附圖式，點將更清楚了解 本發明之上述和其他態樣、特徵和其他優，其中： 第1圖為顯示包含由乾钱刻損害之？型GaN層氮化 物半導體發光農置之電流-電堡αν)曲線之圖示； 弟2Α至2D圖為依照本發明之範例實施例用來解釋 使用水平濕蝕刻之細微圖案形成製程之剖面圖；. 第3Α至3C圖為於顯示依照本發明之範例實施例（實 施例1A )於細微圖案形成製程巾經過水平濕㈣時間圖案 改變之掃描電子顯微鏡（SEM)影像； 第4A至4D圖為顯示於依照本發明之另一範例實施 例（實施例1B )於細微圖案形成製程中經過水平濕侧時 間圖案改變之SEM影像； 第5圖為依照本發明之又另—範例實施例（實施例 ic)獲得之三維圖案（柱狀結構）之SEM影像； 第6A和6B圖為依照本發明之又另一範例實施例（實 94476 26 200924248 施例ID)於細微圖案形成製程中分別於乾蝕刻後和水平濕 餘刻後細微圖案之SEM影像； 第7A和7B圖為顯示於依照本發明之又一範例實施 例（貫施例1E )於細微圖案形成製程中經過水平濕钱刻時 間圖案改變之SEM影像； 第8A圖為藉由依照本發明之範例實施例之製造方法 獲得之氮化物半導體發光裝置（應用光子之結晶結構之例 子）之剖面圖； f . 第8B圖為沿著第8A圖之氮化物半導體發光裝置之 A-A’線之細微圖案之平面圖； • 第9圖為顯示藉由依照本發明之範例實施例（實施例 2)之製造半導體發光裝置之方法製造之氮化物半導體發光 裝置之I-V曲線圖； ' 第10圖為顯示藉由依照本發明之範例實施例（實施 例2)之製造半導體發光裝置之方法製造之氮化物半導體 ί發光裝置之相關電流之光輸出； 第Π圖為藉由依照本發明之另一範例實施例之製造 方法獲得之氮化物半導體發光裝置（表面電漿共振結構之 應用例子）之剖面圖； .^第12圖為顯示藉由依照本發明之另一範例實施例（實 知例3)之製造半導體發光裝置之方法製造之氮化物半導 體發光裝置之I-V曲線之圖示； 第13圖為顯示有關藉由依照本發明之另一範例實施 例（貫施例3)之製造半導體發光裝置之方法製造之氮化 27 94476 200924248 不。 物半導體發光裝置之電流之光輸出之圖 ' 【主要元件符號說明】 11 半導體結晶 18 遮罩 80 氮化物半導體發光裝置 81 監實石基板 82 η型氮化物半導體層 84 主動層 85 Ρ型氮化物半導體層 87 光傳輸層 89a η侧電極 89b ρ側電極 110 氮化物半導體發光裝置 111 氣化物半導體監寶石基板 112 η型氮化物半導體層 114 主動層 115 Ρ型氮化物半導體層 117 η側電極 118 ρ側電極 120 基板 D、D， 損害面積 dl、d2 深度 PI 第一細微圖案 P2 最終細微圖案 P3、P4 週期的細微圖案 W1 ' W2 寬度 28 94476Dry etching (about 0.1 #m) is performed on the c-plane GaN surface by using a mask, thereby forming a rough circular hole pattern, and then removing the mask (see Fig. 6A). After the formation of the circular hole pattern, wet etching using a 4 M KOH aqueous solution was carried out at about 108 ° C for about 30 minutes. As shown in Fig. 6, each has a hexagonal hole, and the sides of the hexagonal hole are formed in parallel with the fine pattern of the {1-1 〇〇丨 m plane, and the fine patterns are no longer etched. Example 1E. The current embodiment is similar to the previous embodiment 1D except that the diameter of each final hole is made larger to assist in observing the change in the side wall of the final hole in the crystal plane. In the current embodiment, the periods of the holes are the same as in the previous embodiment 1D, but the diameter of the holes is made larger. Sixth from the horizontal wet etching (100 °C, 4M KOH aqueous solution) 16 94476 200924248 The angular hole section is taken as an SEM image a picture about 1 minute of the result, & 锫% members are not wet etched through the fruit. 7B shows that the result of the 40-minute junction is that when the wet_continues, the area (the s-plane is relatively less than ten sides occupies n%疋) decreases on the sidewall of the hole; a τ The area occupied has increased. In detail, from the 7th A2;: the 5th plane gradually distorts as the continuation proceeds, but the eclipse: face. The ten songs are gradually changed into 1* planes, and then become. The results of the observation of the section of the flat and the hole after the secret period of the hole. 疋 This shows that when the wet etching continues, the hole is changed from the initial y button Μ α θ green to the hole until the steady day surface is gradually exposed. The crystal plane of the inner side wall may be composed of a combination of a bottom surface ς 0〇n C plane and a { Hoi } s plane, 丨_ , , { 1-1Π0 I 0 twisted plane, • r plane, and the like. Since the wet _ does not perform the plane y, the depth of the hole does not change. However, it can be assumed that if the bottom surface and there are , , and the fields are not flat and inclined, the horizontal side operation can remove them. As described above, as for the fine pattern obtained in accordance with the present invention, the crystal plane exposed by the water (4) is a clean plane obtained by removing the portion damaged by the dry money. Thus, when the electrical contact layer is formed on the crystal plane, superior ohmic contact can be ensured. Moreover, when the electrode material is deposited, the contact characteristics can be improved by adjusting the slope of the crystal plane according to the crystal plane. 9 The fine pattern forming process can be widely applied to form a work pattern of various semiconductor devices. In particular, it can be advantageously applied to form a pattern 94476 17 200924248 for improving the light efficiency of the semiconductor light-emitting device - with respect to the nitride semiconductor light-emitting device 8G, the eighth embodiment of FIG. 8A, nitride semi-conductive crystal Should be ^ example. The substrate 81, and the n-type nitride semiconductor layer & gemstone half-85 are sequentially formed on the "stone and bismuth-type nitrogen and the nitride semiconductor light-emitting device and the p-side electrode_side electrode are connected to the n-type nitride semiconductor shoulder The fine pattern P3 of the electrode 89b is electrically formed by the compound semiconductor layer 85. The fine pattern can be obtained by referring to the P2A type vaporized semiconductor layer 85 (Example 1D). In other words: The process-type holes of the Ming can be configured in a periodic manner. As shown in the figure 8B, the hexagon is further formed on the surface including the periodic fine hole pattern 光 = optical transmission semiconductor layer 8S in accordance with the current embodiment. Photoacoustic pattern (4) Nitride Any material shape of ohmic contact. For example, ^ light transmission time to ensure that the light transmission = genus layer or such as the light transmission oxygen of IT0 = such as "less". If two 3 = conductor layer, the thickness can be 5. Or, the thickness of the main (four) β ' semiconductor layer 85 is excessively small, that is, the thickness of the 〇 或 or more 氮化 type nitride semiconductor layer 85 may be Α : the nuance of the Ρ type nitride semiconductor layer 85 The pattern Ρ3 may have a "," sub-crystalline structure, when the light generated in the active layer 84 is selected to the outside via the surface of the 944 type 94476 18 200924248 nitride semiconductor layer 85, by attenuating the surrounding air or sealant The total reflection effect caused by the low refractive index improves the light selection efficiency. The fine pattern formation method according to the present invention can perform high precision and superior reproducibility because even when wet etching is used, according to the crystal plane The etch rate is changed. Thus, the fine pattern forming process can be advantageously applied to the nitride semiconductor light-emitting device having the photonic crystal structure illustrated in FIG. 8A. Although described as a nitride semiconductor light-emitting device in the prior embodiment, However, the present invention is not limited thereto, and the present invention can be applied to a light-emitting device using various known semiconductor materials. Moreover, the embodiment of Fig. 8A The photonic crystal structure is used on a specific semiconductor layer, such as a P-type nitride semiconductor layer. However, the embodiment of FIG. 8A can be advantageously applied even when the aperiodic uneven pattern for light selection is formed of a different material. A method of forming a periodic fine pattern of surface plasma or a method for simultaneously forming a desired fine pattern of a crystal surface is formed. Embodiment 2 is related to an experiment of a light-emitting device having photonic crystal, and the result thereof. According to the current embodiment, a nitride semiconductor light-emitting device having an active layer comprising an InGaN multiple quantum well having a green wavelength is fabricated. As for the light-emitting device manufactured according to the current embodiment, a p-type GaN layer having a thickness of about 150 nm is used. It was dry etched to a thickness of about 54 nm by using a mask having a circular hole similar to the case of 19 94476 200924248, and then wet etching was performed thereon for about 10 minutes to form a hexagonal hole pattern. Thereafter, similar to the configuration illustrated in FIG. 8A, an optical transfer electrode oxide such as ITO is deposited on the p-type GaN layer. The light emitting electrode layer is formed to form a P side contact. Mesa-etching is performed thereon to partially expose the n-type GaN layer, and an n-side contact is formed on the exposed n-type GaN layer. The electrical characteristics and illuminance of the semiconductor light-emitting device manufactured by the method of the present invention were measured for electrical characteristics and illuminance of the nitride semiconductor light-emitting device according to Example 2. The results of the measurement are shown in Figures 9 and 10 in comparison with Reference Example Ref. The example Ref is the result of the light-emitting device, in which only the silver contact is disposed on the P-type nitride semiconductor layer and no pattern is formed thereon. Fig. 9 is a graph showing the IV of the semiconductor light-emitting device according to the current exemplary embodiment. The figure shows the light output associated with the current of the nitride semiconductor light-emitting device according to the current exemplary embodiment. As shown in Fig. 9, unlike the nitride light-emitting device of Fig. 1, the semiconductor light-emitting device manufactured in accordance with Embodiment 2 of the present invention has an IV characteristic in which there is almost no damage caused by dry etching. Leakage current. The nitride semiconductor light-emitting device has a higher voltage at the same current than the reference example Ref, but the difference is not significant. The area ratio of the crystal plane obtained from the wet etching can be further increased, so that the contact resistance can be improved as compared with the prior embodiment, and better electrical characteristics can be achieved. Fig. 10 is a view showing the light output of a current relating to the manufacture of a nitride semiconductor light-emitting device of 20 94476 200924248 in accordance with the current embodiment of the present invention. As shown in Fig. 10, it can be seen that the nitride semiconductor light-emitting device according to the current embodiment achieves an increase in illumination of about 24% at 350 mA due to the diffusion of photonic crystals as compared with the reference example Ref. That is, the photonic crystal pattern produced by the etching process according to the present invention is formed to have a precise profile such that a portion of the LED wafer that is limited by the total reflection is diffracted to allow emission to the outside of the wafer. angle. This also significantly improves the illumination of the LED. Fig. 11 is a side sectional view showing a nitride semiconductor light-emitting device obtained by the production method of the present invention, which is an application example of the principle of surface plasma resonance. The surface plasma used in this application oscillates as a collective charge density of electrons occurring on the surface of the metal film. The surface plasma waves generated by the collective charge density oscillation are surface electromagnetic waves propagating along the boundary surface between the metal and the dielectric. When the coupling between the surface plasma and the active layer occurs, the natural emission occurring in the active layer is increased by the surface plasma, and most of the light generated by the natural emission is excited to generate the surface plasma. A semiconductor light-emitting device employing this principle to improve its efficiency may be referred to as a surface plasma half-conductor light-emitting device. Referring to Fig. 11, the surface plasmon nitride semiconductor light-emitting device 110 is mounted on the sub-mount substrate 120 by soldering. The surface plasma nitride semiconductor light-emitting device 110 includes a nitride semiconductor sapphire substrate 1A, an n-type nitride semiconductor layer 112, an active layer 114, and a p-type nitride semiconductor layer 115, which are sequentially disposed on the nitride semiconductor sapphire substrate 111. 21 94476 200924248 Further, the nitride semiconductor light-emitting device 110 includes an n-side electrode 117 ′ and a p-side electrode 117 electrically connected to the n-type nitride semiconductor layer 112 and the germanium-type nitride semiconductor layer 115, respectively. A fine pattern Ρ4 having a periodicity is formed on the p-type nitride semiconductor layer 115. These fine patterns Ρ4 may be hexagonal pattern of holes arranged in a periodic manner, which is obtained by the process described with reference to Figs. 2 to 2D (Embodiment 1D). According to the current embodiment, as shown in Fig. 11, the highly reflective metal layer is formed as the p-side electrode 118 on the p-type nitride semiconductor layer 115 including the periodic fine hole pattern Ρ4. This highly reflective metal layer can be made of a material having a predetermined reflectivity while ensuring ohmic contact. For example, a highly reflective metal layer may be formed of a single layer or multiple layers such as Ming, Silver, Gold, Li, Record, Wrong and Ming. Moreover, the distance between the active layer 114 and the highly reflective metal layer is very important to cause surface plasma resonance. As such, the p-type nitride semiconductor layer 115 is required to have a sufficient thickness to allow the light emitted from the active layer 114 to excite the surface plasma between the p-type nitride semiconductor layer 115 and the highly reflective metal layer. . The p-type nitride semiconductor layer 115 may have a thickness of less than about 50 nm. If the thickness of the p-type nitride semiconductor layer 115 is insufficient, that is, the distance from the active layer 114 to the grid structure is excessively short, the leakage current is drastically increased. For this reason, the p-type nitride semiconductor layer 115 may have a thickness of 10 nm or more. According to the current embodiment, the principle of surface plasma resonance can be used in an optical device to improve luminous efficiency. Here, and the armor, the fine pattern p4 having the periodic grid structure must be on both sides of the PiillUb semiconductor layer 115 and the highly reflective metal layer to re-convert the excited surface plasma. In particular, the correct pitch and rule of the fine pattern p4 is determined according to the wavelength of the active layer 114. However, as previously explained, the distance between the active layer 114 and the highly reflective metal layer is very important in various conditions for causing the surface electrical §_resonance, such as the wavelength of the human light, and the refractive index of the material contacting the metal. Since the distance is usually 50 nm or less (which is relatively short), damage to the p-type nitride semiconductor layer II5 caused by dry etching may cause severe limitations. However, the fine pattern forming process according to the present invention can minimize the damage remaining in the fine pattern P4 at the final stage. Moreover, even if wet etching is used, the fine pattern forming process according to the present invention can achieve high accuracy and excellent reproducibility' because the etching rate changes depending on the crystal plane. As such, the 11 dark pattern forming process in accordance with the present invention can be advantageously applied to the first surface plasma nitride semiconductor light-emitting device. There is a green light-emitting device i^i_3. According to the prior embodiment, a nitride semi-conducting of an active layer of an InGaN multi-quantum well of a heterochromatic wavelength is produced similarly to the second embodiment. / Dry etched The LED fabricated according to the current embodiment comprises a hexagonal hole pattern formed by the ip phase 94476 to a depth of about 33 nm, and is p-shaped with a thickness of about 66 nm as in the case of Example 23 200924248. A mask having a circular hole was used on the GaN layer, and then wet etching was performed for about 10 minutes. Thereafter, similar to the structure illustrated in FIG. 11, a p-side contact is formed by depositing a plurality of metal electrodes including a highly reflective material layer which is a silver layer on the p-type GaN layer, and by performing a mesa The remainder is formed by partially exposing the n-type GaN layer to form an n-side contact. In order to examine the improvement in electrical characteristics and illuminance of the nitride semiconductor light-emitting device manufactured by the method of the present invention, the improvement in electrical characteristics and illuminance of the nitride semiconductor light-emitting device according to Example 3 was measured. The results of the measurement are shown in Figures 12 and 13 in comparison with Reference Example Ref. Here, the reference example is a result of including the same multilayer metal electrode light-emitting device structure as in Embodiment 3 and not including the pattern on the P-type nitride semiconductor layer. Fig. 12 is a view showing an I-V curve of a nitride semiconductor light-emitting device according to the current embodiment. Fig. 13 is a view showing the light output of the current of the nitride semiconductor light-emitting device according to the current embodiment. As can be seen from Fig. 12, as can be seen from Fig. 1, the semiconductor light-emitting device manufactured in accordance with Embodiment 3 of the present invention has an I-V characteristic in which there is almost no leakage current generated at the dry etching time. However, a slightly irregular curve was observed on the I-V curve of the current embodiment, which has a very thin P-type nitride semiconductor layer as compared with the conventional embodiment of the conventional nitride semiconductor light-emitting device. The nitride semiconductor light-emitting device according to the current embodiment has an almost constant voltage at the same current as compared with the reference example Ref. By increasing the area ratio of the crystal plane obtained from the wet etching, it is desirable to have better electrical characteristics than the current embodiment 24 94476 200924248, and thus improve the contact resistance. Fig. 13 is a view showing the light output of the current of the nitride semiconductor light-emitting device according to Embodiment 3 of the present invention. As can be seen from Fig. 13, the nitride semiconductor light-emitting device according to the current embodiment has an improvement in illumination of about 64% at 350 mA due to the surface plasma resonance effect as compared with the reference example Ref. That is, the fine grid structure fabricated using the etching process in accordance with the present invention forms an accurate profile such that the electron-holes of the multi-quantum wells implanted into the LED wafer convert light into light through the medium of the surface plasma. And the light is emitted to the outside of the LED chip. Moreover, portions of the light generated by self-emission without the use of surface plasma as a medium and limited by total reflection are diffracted to shift the direction of propagation of the light to an angle that allows emission to the outside of the wafer. Thus, the illuminance of the illuminating device can also be significantly improved. According to the present invention, only a minimum portion of the desired pattern area is etched, and then wet etching is performed in the horizontal direction to form the surface, so that the damage caused by the dry etching I i is minimized. Moreover, the crystallographic direction (pattern forming direction) and wet etching conditions (e.g., time conditions) are appropriately controlled so that the high reproducibility of the fine pattern can be ensured while the height and the size of the fine pattern are freely controlled. A semiconductor light-emitting device having superior light efficiency can be provided by applying such patterns to a photonic crystal structure or a structure using a surface plasma principle. Moreover, the particular geometry of the fine pattern in accordance with the present invention is naturally formed in accordance with the hexagonal crystallization system during the subsequent wet etch process. 25 94476 200924248 In the 疋, the fine pattern has a unique crystal plane, such as the C plane, the m plane, the S plane, and the heart plane, in which almost no damage occurs, because: the crystal plane can be directly in contact with the semiconductor light-emitting device Is the electrode layer of all or conductive oxides 'so formed? Type ohmic contact is more advantageous. Although the present invention has been shown and described with respect to certain exemplary embodiments, it will be understood that those skilled in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the invention. range. BRIEF DESCRIPTION OF THE DRAWINGS The above and other aspects, features and other advantages of the present invention will be more clearly understood from the aspects of the appended claims. ? Illustrative embodiment of a GaN layer nitride semiconductor illuminating current-electrical voltaic voltaic luminescence; a 2D to 2D diagram is a cross-sectional view illustrating a fine pattern forming process using horizontal wet etching in accordance with an exemplary embodiment of the present invention; Figures 3 to 3C are diagrams showing scanning electron microscope (SEM) images of a fine pattern forming process towel in a horizontal wet (four) time pattern in accordance with an exemplary embodiment (Example 1A) of the present invention; FIGS. 4A to 4D are views According to another exemplary embodiment of the present invention (Example 1B), an SEM image is changed by a horizontal wet side time pattern in a fine pattern forming process; FIG. 5 is a further exemplary embodiment according to the present invention (Example ic) SEM image of the obtained three-dimensional pattern (columnar structure); FIGS. 6A and 6B are diagrams showing another exemplary embodiment (solid 94476 26 200924248, example ID) in the fine pattern forming process after dry etching in accordance with the present invention And an SEM image of the fine pattern after the horizontal wet residue; FIGS. 7A and 7B are diagrams showing the horizontal wetness in the fine pattern forming process according to still another exemplary embodiment (Scheme 1E) according to the present invention. An SEM image in which a time pattern is changed; FIG. 8A is a cross-sectional view of a nitride semiconductor light-emitting device (an example of a crystal structure to which a photon is applied) obtained by a manufacturing method according to an exemplary embodiment of the present invention; f. FIG. 8B is a view A plan view of a fine pattern of the AA' line along the nitride semiconductor light-emitting device of FIG. 8A; and FIG. 9 is a view showing a method of fabricating a semiconductor light-emitting device by an exemplary embodiment (Example 2) according to the present invention IV graph of a nitride semiconductor light-emitting device manufactured; '10 is a current showing a nitride semiconductor light-emitting device manufactured by a method of fabricating a semiconductor light-emitting device according to an exemplary embodiment (Example 2) of the present invention The light output is a cross-sectional view of a nitride semiconductor light-emitting device (application example of a surface plasma resonance structure) obtained by a manufacturing method according to another exemplary embodiment of the present invention; A nitride semiconductor light-emitting device manufactured by a method of manufacturing a semiconductor light-emitting device according to another exemplary embodiment (Summary Example 3) of the present invention It illustrates the I-V curve; graph display section 13 about the nitride semiconductor light emitting device manufactured by the method of manufacture in accordance with another exemplary embodiment of the present invention (Example 3 penetration) of the 2,794,476,200,924,248 not. Diagram of the light output of the current of the semiconductor light-emitting device' [Description of main components] 11 Semiconductor crystal 18 Mask 80 Nitride semiconductor light-emitting device 81 Supervised stone substrate 82 η-type nitride semiconductor layer 84 Active layer 85 Ρ-type nitride Semiconductor layer 87 Light transmission layer 89a η side electrode 89b ρ side electrode 110 nitride semiconductor light-emitting device 111 vaporized semiconductor gilt substrate 112 n-type nitride semiconductor layer 114 active layer 115 Ρ-type nitride semiconductor layer 117 η-side electrode 118 ρ Side electrode 120 substrate D, D, damage area dl, d2 depth PI first fine pattern P2 final fine pattern P3, P4 period fine pattern W1 'W2 width 28 94476