TW200924107A - An electronic circuit element with profiled photopatternable dielectric layer - Google Patents

An electronic circuit element with profiled photopatternable dielectric layer Download PDF

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Publication number
TW200924107A
TW200924107A TW097137652A TW97137652A TW200924107A TW 200924107 A TW200924107 A TW 200924107A TW 097137652 A TW097137652 A TW 097137652A TW 97137652 A TW97137652 A TW 97137652A TW 200924107 A TW200924107 A TW 200924107A
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TW
Taiwan
Prior art keywords
layer
electrically insulating
electronic device
insulating material
electronic
Prior art date
Application number
TW097137652A
Other languages
Chinese (zh)
Inventor
Aerle Nicolaas Aldegonda Jan Maria Van
Joris Pieter Valentijn Maas
Original Assignee
Polymer Vision Ltd
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Publication date
Application filed by Polymer Vision Ltd filed Critical Polymer Vision Ltd
Publication of TW200924107A publication Critical patent/TW200924107A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT

Abstract

An electronic circuit element is disclosed comprising: a first electronic component and a second electronic component, said first electronic component and said second electronic component being arranged to share a first electrically conducting layer, a second electrically conducing layer; and, an electrically insulating layer spatially arranged between the first electrically conducting layer and a second electrically conducing layer, wherein the electrically insulating layer comprises a photopatternable material having a first thickness in a region covered by the first electronic component and a second thickness in a region covered by the second electronic component. The resulting structure 40 may comprise a plurality of areas 42 of a first thickness an area 41 of a second thickness and optionally a plurality of areas 43 with zero thickness.

Description

200924107 九、發明說明： 【發明所屬之技術領域】 本發明係II於一種電子電路器件卩及一帛包括此電子 電路器件的裝置。更明確地說，本發明係關於—種包括一 薄膜電晶體（TFT)的結構。本發明還進一步關於—種製造電 子電路元件的方法。 【先前技術】 。。舉例來說，薄膜電晶體（TFT)裝置通常會使用在一顯示 :的主動㈣之中’於該顯示器巾，—共用介電層可作為 TFT閘極的-合宜介電層、—儲存電容器、或是用來跨 接導電線路。-顯示裝置的主動矩陣通常包括複數掘顯示 π素’它們通常被稱為像素（pixel)或像點（细）。於一黑白顯 示器的情況中，一像素可能和一像點相同。於一彩色顯示 器的情況中，-像素則可能包括—組像點，舉例來說，一 色、4色以及藍色像點。底部閘# tft以及頂端閘 才-T均可以使用。於底部閉極TFT的情況中，該丁π結 構的建構方式通常係從m導體層的基板開始。 此導體層接著會被圖牵化田，v w . 曰牧百B攸闺茶化用以界定：一閘極線路（通常也稱 為列線路”該薄膜電晶體(TFT)開關的閑極電極；以及視情 況界定另-電子器件(例如一電容器或是一儲存電容器)的 電極。該導電層至少部分會被—非導體層覆蓋，該非導體 層係充當一絕緣層以及-介電層。接著，-第二導電層會 被提供並且被圖案化用以界定下㈣何—者：—資料線路 200924107 (亦稱為行料或是源極線路）；該TFT的—源極電極·，一通 道；該TFT的一汲極電極；一像素雷 1豕東電極；以及視情況界定 另-電子器件的電極(例如-電容器的第二電極)。為創造一 功能性的TFT，在塗敷該第二導電層之前或之㈣會提供― 半導體層。該半導體層可能進一步會祐 一鈍化層覆蓋，用 以保護該半導體層。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is directed to an electronic circuit device and a device including the electronic circuit device. More specifically, the present invention relates to a structure including a thin film transistor (TFT). The invention still further relates to a method of fabricating an electronic circuit component. [Prior Art]. . For example, thin film transistor (TFT) devices are typically used in a display (active) (in the display), a shared dielectric layer can be used as a TFT gate - a suitable dielectric layer, a storage capacitor, Or used to bridge conductive lines. - The active matrix of the display device typically includes a plurality of pixels showing π primes which are commonly referred to as pixels or pixels (thin). In the case of a black and white display, one pixel may be the same as an image point. In the case of a color display, the -pixel may include a set of image points, for example, one color, four colors, and blue image points. The bottom gate #tft and the top gate -T can be used. In the case of a bottom closed TFT, the structure of the π-π structure is usually started from the substrate of the m-conductor layer. The conductor layer will then be pulled into the field, vw. 曰 百 百 攸闺 攸闺 用以 用以 用以 用以 用以 用以 用以 用以 用以 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一And optionally, an electrode of an electronic device (for example a capacitor or a storage capacitor). The conductive layer is at least partially covered by a non-conductor layer serving as an insulating layer and a dielectric layer. a second conductive layer will be provided and patterned to define the following (four): - data line 200924107 (also known as a row or source line); the source electrode of the TFT, a channel; a drain electrode of the TFT; a pixel Lei 1 east electrode; and optionally an electrode of the electronic device (eg, a second electrode of the capacitor). To create a functional TFT, apply the second A semiconductor layer is provided before or (4) of the conductive layer. The semiconductor layer may further cover a passivation layer to protect the semiconductor layer.

不同導體層之間的電性短路可能會發生在已知的Μ 結構中。㈣短路會導致—顯示器内的像素缺陷，甚至導 致線路缺陷。在該TFT結構中的源極與閘極之間的重疊區 域中的電性短路以及在料跨接行線路與閘極線路中的短 路均可能會導致線路缺陷。在該TFT㈣極區域中間極與 汲極電極之間的電性短路以及在該儲存電容器區中的短路 則可能會導致像素缺陷或像點缺陷。 1 【發明内容】 本發明的一目的係提供一種電子電路元件，其中，該 介電層的厚度實質上至少會針對構成該電子電路的某些電 子器件而被最佳化，並且可以簡單的方法來製造此電子電 路元件。 為達此目的，根據本發明的電子電路元件包括： _ 一第—電子器件以及一第二電子器件，該第一電子器 件以及該第二電子器件會被排列成用以共用： 一第一導電層； -一第二導電層；以及 7 200924107 一介電層，其在空間上係被排列在該第一導電層 與該第二導電層之間， 。。該介電層包括一可光圖案化材料，其在被該第一電子 器件覆蓋的區域中具有第一厚度，而在被該第二電子器件 覆蓋的區域中具有第二厚度。 r 本發明的技術性手段係以下面的觀察為基礎。應該瞭 解的係’為達一 TFT的良好效能，間極介電質較佳的係保 持非常的薄’以便提高TFT的電容，因為tft的導通電流 係與，極電谷成正比，而該電容則與該介電層的厚度成反 比。高導通電流可能會因TFT的較小通道寬度而被抵銷。 縮減該通道寬度會縮小閘極與源極電極之間的重疊面積以 及閘極與沒極電極之間的重疊面積，從而在每個單位面積 給定怪定數量的短路下，降低因短路所造成的線路缺陷以 及像素缺陷的風險。對儲存電容器來說，同樣係以薄介電 層為佳，因為這會達到縮減電容器面積的目的。對跨接線 路之間的絕緣層來說，該絕緣層則係以儘可能越厚為佳， 以便降低會在顯示器中造成線路缺陷的短路的風險。 偶若係高解析度顯示器，行線路與間極線路之間的相 對跨接面積會提高。這會導致行線路與間極線路之間會有 很高的短路風險。這亦可能會導致增加該閘極線路的 間。為正確地驅動一顧；3& » en » t 、 4不益，該閘極線路的RgateCgate較佳 於選擇時間（其亦稱為線路㈣）的1()% 該等跨接之間的絕緣層的厚度，該等跨接的電容便= 低，從而會降低尺叫/叫。〇 200924107 域φΙ八電性效能之間的平衡而言，在每-個特殊區 '的介電層的厚度會有一最佳值。就平行板電容 說，藉由縮減介電層厚度且縮小電容器面積，或是增加介 電層厚度且提高電容器面積，均可保持相同的電容。降低 ):電質厚度會因頂端電極與底部電極之間的小粒子而提言 短路的風險；相反地，顧及每單位面積怪定的粒子密度Γ 提高電容器面積同樣會因粒子而提高短路的風險。a #據本發明的技術性手段，相同的可光圖案化電絕緣 層可使用於複數個電子器件，舉例來說，其可使用在：間 =電：中儲存電容器介電質，導電線路跨接於之間的絕 '' 其中，該可光圖案化電絕緣層的厚度實質上會依昭 構成根據本發明的電子電路元件的某些電子器件(較佳的、 係，最重要的電子器件）的操作需求而被最佳化。 藉由合宜地套用-特殊的曝光技術（例如已知的半色調 技術或是繞射技術）便可達到該電絕緣（介電質）層之厚声調 制的目的。半色調曝光的其中一範例會參考圖】來討：。 或者’亦可使用已知的雙重曝光方法。雙重曝光技術會在 套用-第-遮罩之後套用—第二遮罩。第一次曝光盘第二 次曝光之間的曝光光強度或波長分佈可能並不相同。 依此方式’該可光圖案化介電層可在單一製程步驟中 被曝光用以產生不同的厚度。較佳的係，為達此目的，會 使用uv曝光。所生成的厚度可依照它們的功能與產量被最 佳化’舉例來說，在該電子電路元件中的其中一區域中有 一厚的絕緣(也就是，介電質)層而另-區域中則有薄的絕緣 200924107 (也就是，介電請。現在將參相2來更詳細討論根據本 發明之電子電路元件的一實施例。 於根據本發明的電子電路元件的一實施财，該可光 圖案化電絕緣層包括一有機材料。 有機的可光圖案化電絕緣（介電f)層特別適合製造一 顯示器（舉例來說，-撓性顯示器）的主動矩陣。應該明白的 係，T宜的有機材料可能包括某些數額的無機成分，例如： ·‘·等°於使用—有機介電材料作為絕緣層 7情況令，其會有利於提供實質上沒有帶電載子的另一電 絕緣層。此另—層會改善該介電層的電性特徵，舉例來說， 會改善電性崩潰強度。舉例來說，聚婦煙或類似物可以用 =-層。於此情況中’會針對該堆疊中的頂端層來選 =^圖案化的材料。可以使用該可光圖案化作為一遮罩 ==刻該絕緣層堆疊中的其它層。可以濕式或乾式 。 ―、匕層了經過選擇，用以最佳化該電子 ::功能，例如經改善的電性崩潰、該些其它層可能包 括無機或有機材料。戍者， 戈者該堆疊中的該等其它介電層可 、濩一頂端閘極TFT裝置的半導體。 儲力2光圖案化介電層可用於-閘極介電質以及用於-器二谷：介電質。有機層可能會被用來製造可撓性顯示 非當寐^匕們的可挽性優於無機等效物並且可藉由簡單且 製造j的方法從一液體溶液中來塗敷。後者比較有利於 f費性電子的可撓性及可捲縮的顯示器，以便實質最 小化在使用中因其變形而在該顯示層中所導致的裂痕。亦 200924107 可以使用無機層。不過，為 t ^ I牡咢折該可接性顚+ 3S η 士 發生和裂痕有關的問題 ” 、時 的俜，機層應該小於5〇〇，且較佳 扪保，谷度大小等級介於丨 议住 声洛丄 至2〇〇nm之間，而更佳的孫 厗度大小等級介於2 尺住的係， 至100nm之間。該可光圖宰 亦可作為該儲存雷夂哭认八# 疋圆茶化7丨電層 導電列線路與導雷杆嬙，w 〃、圖 中所不的 步撼太4 謂的線路跨接）之間的絕緣層。 Φ ^ ^ ^ I抛匕括一第一電子器件與一第二 電子器件的雷早常政-从， ^— 電路7L件的方法包括下面的步驟： 基板上"L·積一第一導電層，用以形成一由第 電子器件與第二電子器件所組成的第一導體 層； ”積可光圖案化電絕緣材料層，該層會被設計 成在空間上被排列在該第一導電層與一第二導電 層之間； •光圖案化該可光圖案化電絕緣材料層，用以在被 該第一電子器件覆蓋的區域中提供該層的第一厚 度以及在被該第二電子器件覆蓋的區域中提供該 層的第二厚度； ' 沉積由該導體材料所組成的第二層。 根據本發明的方法的進一步有利實施例會在申請專利 範圍第11至17項之中提出。根據本發明的方法將會參考 圖4作進—步詳細的討論。 現在將參考圖式來進一步討論本文所揭示之本發明的 實施例的前述與其它觀點。 11 200924107 【實施方式】 圖1所#的係一半色調曝光方法之實施例的概略示意 圖。於-習知的曝光方法⑷之中，可能會使用一遮罩^ 其包括UV透明！I 1以及UV不透明區2。g此，一被排列 在基板8之上的合宜可光圖案化材料6將會被圖案化 括具有實質相等高度的-連串合宜的島狀體^。於此範例 中’層6所指的係-正向型光阻。於半色調曝光方法^之 ( 中則係使用具有至少三個不同區域的遮罩Ua，如圖1(b) 中的概略顯示。該光遮罩山中的區域4會讓uv光透過（和 光遮罩U中的區域！雷同）；區域2會阻隔該…光；而區 j 3則對UV光半透明一合宜光遮罩的範例可能包括石 英，其具有經圖案化的鉻作為區域2以及氧化絡作為區域 3。舉例來說，氧化鉻的製作方式可讓11乂透射率下降至其 原始數值（對應於區域i或4的透射率）的1〇%或2〇%。所 「以，輕射強度在通過該半透明區3之後便會如元件符號5 L， 所示般地下降。 、可光㈣化材料會受到UV光能量的大小程度影響。跨 接連、、.。的私度則會受到該材料被曝光的—光能量的數額 影的情況中’uv曝光將會導致在驗性或 是含驗顯影劑中有高溶解性。於負向光阻的情況中，經過 U +光的區域則會變成無法溶解。當給予高UV曝光劑量 時’整個層厚度甲的被曝光光阻便會完全反應。於施加較 低劑量的情況中，該被曝光光阻則僅有一部分會反應，接 12 200924107 著’顯影便僅會洗掉或移除該層的-部分，從㈣下較薄 的光阻層。元件符锛！ 1 ^ 所不的便係顯影之後所生成的結構。 虽層8頂端的正向 门光敏有機層6曝光至UV光且接著進 行顯影之後，便會漆& - μ μ 凡件符號6a、6b所示的結構。請注 意’在圖1的略圖fb、φ 固中，圖中所示的係使用一正向光阻型 的半色調遮罩；而太岡( Α 圖1的略圖（c)中，圖中所示的則係使 用一負向光阻型的丰、疮 千色調遮罩7。如圖中概略顯示，使用該 光遮罩中的半透明ρ·合+ & £曰在顯影之後產生一中等光阻厚度 6b ° 要進-步注意的係，&了使用半色調遮罩之外，使用 已知的繞射遮罩亦可取得可光圖案化絕緣層6《7的雷同 輪廓化效果。亦可以使用用以產生該可光圖案化電絕緣層 之不同厚度的纟匕技術（較佳的係，在單一處理步驟中）來達 到相同的結果。舉例來說，可以使用已知的雙重曝光方法。 雙重曝光技術會在套用一第一遮罩之後套用一第二遮罩。 第一··人曝光與第二次曝光之間的曝光光強度或波長分佈可 能並不相同。 圖2所不的係一已知的電子電路元件之實施例的概略 示思圖。一主動矩陣式顯示器裝置通常包括複數個顯示元 素，匕們會被稱為像素或像點。圖2所示的便係一以所謂 的底部閘極TFT為基礎的顯示器的單一像素元素的概略代 表圖。此結構的建構方式通常係從一具備一第一導體層的 基板開始。此導體層接著會被圖案化用以界定一閘極線路 22 ’ 一 TFT開關的閘極電極23 ’以及館存電容器27的一電 13 200924107 極32。此層可被一非導體層33直接覆蓋，該非導體層係充 當一絕緣層以及一介電層。於該顯示器的外侧邊界中，此 非導體層具備多個孔洞或通孔，用以促成該等閘極線路的 電性接觸。視情況，為降低因該顯示區内部的開路閘極線 路所導致的可能的產量損失，可能會藉由一穿過該非導電 層33中之接觸孔洞30的第二導電層31來局部並聯該等間 極線路。用以在兩個導體層之間產生並聯的相同方式亦可 用於行線路（此處並未顯示）。於後面的情況中，該並聯結構 係藉由該第一導體層來產生並且經由雷同的通孔來接=該 等行線路。接著，一第二導電層會被提供並且會被圖案化 用以界定資料線路或行線路21，TFT的源極電極乃，通道 區24, TFT的汲極電極26,像素電極28，以及儲存電容= 的第二電極，並且會辑情況界定閘極線路22的並聯層 31。為創造一功能性的TFT’在塗敷該第二 之前或之後可能還會提供-半導體層。此半㈣^可^進) 一步會被一鈍化層覆蓋，用以保護該半導體層。亦可以採 用其它設計’例如頂端閘極TFTe此外，圖中還顯 :二剖面’參見A-A，、—c，。於該顯示器的所有； _區域中’介電層33的厚度均相同，這非常不利。 立圖3戶斤示的係根據本發明的方法的一實施例的概略示 思、圖。根據本發明的技術性手段，會為該絕緣層選擇一可 2圖案化的絕緣層，其係使用半色調曝光來圖案化，用以 產生具有不同厚度的絕緣材料區域。 在以有機為基礎的主動矩陣中，非導電層33(其係充當 14 200924107 ::二電:)二能:由—有機層所製成(舉例來說，請參見圖 為它=1機層可能有利於製造可撓性顯示器，因 法二：：：優於無機材料並且可透過簡單且廉價的方 ✓ί•攸一溶液十來珍獻 亍考φ 可以使用在可撓性及可捲縮的顯 Ζ令而不會在該層中造成裂痕4 —較佳的實施例中， 可光圖案化材料(舉例來說，一可光圖案化有機層) :為非導體層因為不需要額外的蚀刻與剝離製程步驟 更可以完成該建構作業。以，會取得—包括具有不同厚 j Al、A2、B1、B2、C1、C2、c3之絕緣體的結構。要進 夕月白的係，該等不同厚度A1、A2、B1、B2、〇、c2、 C3貫質上互不相同，舉例來說，相差至少百分之10至20, :佳的係’相差百分之20 150,而最佳的係，相差超過百 刀之50。應該明白的係，雖然形成該介電層使其包括兩個 不同的厚度便可能足夠；不過，本實施例亦涵蓋包括由具 有個別特定厚度之介電材料所組成的更多個區域。於具有 —特殊厚度的每一個區域内，該厚度的變化可能小於其數 值的百分之1〇。 舉例來說’本發明發現’相較於先前技術中選定的某 —層’以從由該絕緣材料所組成的一較厚層處開始為較 佳’參見圖3。層33a的导度變化係利用一半色調遮罩來達 成°於此範例中，該絕緣層在導體29a與32a之間的剖面區 域比較厚’如剖面A-A，中所示。該儲存電容器的介電質的 厚度會被選為在儲存電容器區域B-B，中比較薄。於TFT區 域中’在所提出之範例的設計中，該通道區會呈現一較薄 15 200924107 中，短路的 （ci與c2)介電層。於此情況 、風險會下降’ μ會影響導通電流，因為該tft 的通道區24令的介雷曾度η 質旱度3仍然很小。應該明白的係， '、" ，、匕设計，其並不會脫離本發明的範疇。 圖4所不的係根據本發明的方法所製成的一電子電路 =件的實施例的概略示意圖。根據本發明的方法包括下面 fElectrical shorts between different conductor layers may occur in known Μ structures. (4) Short circuits can cause pixel defects in the display and even lead to line defects. Electrical shorts in the overlap region between the source and the gate in the TFT structure and short circuits in the jumper and gate lines may cause line defects. An electrical short between the intermediate pole and the drain electrode of the TFT (four) pole region and a short circuit in the storage capacitor region may cause pixel defects or pixel defects. SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic circuit component in which the thickness of the dielectric layer is substantially optimized for at least some electronic devices constituting the electronic circuit, and a simple method To manufacture this electronic circuit component. To this end, an electronic circuit component according to the present invention comprises: a first electronic device and a second electronic device, the first electronic device and the second electronic device being arranged to share: a first conductive a layer; a second conductive layer; and 7 200924107 a dielectric layer spatially arranged between the first conductive layer and the second conductive layer. . The dielectric layer includes a photo-patternable material having a first thickness in a region covered by the first electronic device and a second thickness in a region covered by the second electronic device. r The technical means of the present invention is based on the following observations. It should be understood that 'the good performance of a TFT, the preferred dielectric is kept very thin' in order to increase the capacitance of the TFT, because the conduction current of tft is proportional to the polar valley, and the capacitance It is inversely proportional to the thickness of the dielectric layer. The high on current may be offset by the smaller channel width of the TFT. Reducing the width of the channel reduces the area of overlap between the gate and the source electrode and the area of overlap between the gate and the electrode of the electrode, thereby reducing the short circuit caused by a given number of short circuits per unit area. Line defects and the risk of pixel defects. For storage capacitors, a thin dielectric layer is also preferred because it reduces the capacitor area. For the insulating layer between the jumper lines, the insulating layer is preferably as thick as possible in order to reduce the risk of short circuits that can cause line defects in the display. Even if it is a high-resolution display, the relative cross-over area between the line and the interpole line will increase. This can result in a high risk of short circuit between the line and the interpole line. This may also result in an increase in the gate line. In order to drive correctly; 3& » en » t, 4 is not beneficial, the gate of the RgateCgate is better than the selection time (which is also called line (four)) 1 ()% of the insulation between the bridges The thickness of the jumper will be low, which will reduce the scale/call. 〇 200924107 In terms of the balance between the electrical properties of the field φ Ι eight, the thickness of the dielectric layer in each of the special regions will have an optimum value. As far as the parallel plate capacitance is concerned, the same capacitance can be maintained by reducing the thickness of the dielectric layer and reducing the area of the capacitor, or increasing the thickness of the dielectric layer and increasing the area of the capacitor. Lower): The thickness of the dielectric is a risk of short-circuiting due to small particles between the top electrode and the bottom electrode; conversely, taking into account the strange particle density per unit area Γ increasing the capacitor area also increases the risk of short-circuiting due to particles. According to the technical means of the present invention, the same photo-patternable electrically insulating layer can be used for a plurality of electronic devices, for example, it can be used in: between = electrical: storage capacitor dielectric, conductive line cross The thickness of the photo-patternable electrically insulating layer substantially constituting certain electronic devices (better, the most important electronic device) of the electronic circuit component according to the present invention. ) is optimized for operational needs. The thick acoustic modulation of the electrically insulating (dielectric) layer can be achieved by expedient application of a special exposure technique such as known halftone techniques or diffraction techniques. One example of halftone exposure will be discussed with reference to the picture: Alternatively, a known double exposure method can also be used. The double exposure technique will be applied after the application - the first mask - the second mask. The exposure light intensity or wavelength distribution between the second exposure of the first exposure disk may not be the same. In this manner, the photopatternable dielectric layer can be exposed to produce different thicknesses in a single process step. Preferably, uv exposure is used for this purpose. The resulting thicknesses can be optimized according to their function and throughput. For example, there is a thick insulating (i.e., dielectric) layer in one of the regions of the electronic circuit component and another region in the region. Thin insulation 200924107 (i.e., dielectric please. Reference will now be made to phase 2 to discuss in more detail an embodiment of an electronic circuit component in accordance with the present invention. In the implementation of an electronic circuit component in accordance with the present invention, the illuminable The patterned electrically insulating layer comprises an organic material. The organic photopatternable electrically insulating (dielectric f) layer is particularly suitable for fabricating an active matrix of a display (for example, a flexible display). The organic material may include certain amounts of inorganic components, such as: '··etc. using - an organic dielectric material as the insulating layer 7 case, which would facilitate the provision of another electrically insulating layer substantially free of charged carriers This additional layer will improve the electrical characteristics of the dielectric layer, for example, to improve the electrical collapse strength. For example, a polybutanide or the like can be used with a =- layer. In this case, The The top layer in the stack is selected to be a patterned material. The photo-patternable can be used as a mask == other layers in the stack of insulating layers. It can be wet or dry. To optimize the electron:: function, such as an improved electrical collapse, the other layers may include inorganic or organic materials. The latter, the other dielectric layers in the stack may be The semiconductor of the top gate TFT device. The memory 2 photopatterned dielectric layer can be used for the gate dielectric as well as for the device: the dielectric layer. The organic layer may be used to make the flexible display. When the drawability of the ruthenium is superior to the inorganic equivalent and can be applied from a liquid solution by a simple method of manufacturing j, the latter is more advantageous for the flexibility and the crimpability of the electrons. The display, in order to substantially minimize the cracks caused in the display layer due to its deformation during use. Also, the inorganic layer can be used for 200924107. However, for the t ^ I oysters, the achievable 顚 + 3S η occurs The problem related to the crack", the time, the machine layer should be small 5〇〇, and better, the size of the valley is between 声 丄 丄 丄 丄 丄 丄 丄 丄 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 。 The rayable map can also be used as the storage thunder, crying and recognizing the eight #疋圆茶化7丨 electric layer conductive column line and the guide rod 嫱, w 〃, the figure is not the step 撼 too 4 said line jumper The insulating layer between the Φ ^ ^ ^ I throws a first electronic device and a second electronic device of the Ray Chang-zheng-^, the method of the 7-piece circuit includes the following steps: on the substrate "L Forming a first conductive layer for forming a first conductor layer composed of the first electronic device and the second electronic device; and a layer of photo-patternable electrically insulating material, the layer being designed to be spatially Arranging between the first conductive layer and a second conductive layer; • photo patterning the photo-patternable electrically insulating material layer to provide a first thickness of the layer in a region covered by the first electronic device And providing a second thickness of the layer in a region covered by the second electronic device; 'deposition from the guide The second layer is composed of a material. Further advantageous embodiments of the method according to the invention are set forth in clauses 11 to 17 of the patent application. The method according to the present invention will be discussed in detail with reference to Figure 4. The foregoing and other aspects of the embodiments of the invention disclosed herein will be further discussed with reference to the drawings. [Embodiment] Fig. 1 is a schematic diagram showing an embodiment of a halftone exposure method. Among the conventional exposure methods (4), a mask may be used, which includes UV transparency! I 1 and UV opaque zone 2. Thus, a suitable photo-patternable material 6 arranged on the substrate 8 will be patterned into a series of suitable island-like bodies having substantially equal heights. In this example, the layer-forward type resist referred to by layer 6. In the halftone exposure method, a mask Ua having at least three different regions is used, as shown in the outline of Fig. 1(b). The region 4 in the light mask mountain allows the uv light to pass through (and the light is blocked). The area in the cover U! is the same; the area 2 blocks the light; and the area j 3 is translucent to the UV light. An example of a suitable light mask may include quartz with patterned chromium as the area 2 and oxidation. The network serves as the region 3. For example, chromium oxide is produced in such a way that the transmittance of 11 Å is reduced to 1% or 2% of its original value (corresponding to the transmittance of the region i or 4). The intensity of the radiation will fall as shown by the symbol 5 L after passing through the translucent region 3. The light (four) material will be affected by the magnitude of the energy of the UV light. In the case where the material is exposed to the amount of light energy, the 'uv exposure will result in high solubility in the test or test developer. In the case of negative photoresist, U + light The area will become insoluble. When giving a high UV exposure dose, the entire layer thickness The exposed photoresist of the degree A will be completely responsive. In the case of applying a lower dose, only a part of the exposed photoresist will react, and the 12 will be washed or removed. - Part, from (4) Thinner photoresist layer. Component symbol! 1 ^ Nothing is the structure generated after development. Although the front gate photosensitive organic layer 6 of the top layer 8 is exposed to UV light and then proceed After development, it will paint & - μ μ the structure shown by the symbol 6a, 6b. Please note that 'in the outline fb, φ solid of Figure 1, the figure shows a positive photoresist type. Halftone mask; and Taigang (Α Figure 1 in the sketch (c), the figure shows the use of a negative photoresist type of abundance, sore thousand shade mask 7. As shown in the figure, use The semi-transparent ρ·+ + & 曰 in the light mask produces a medium-resistance thickness of 6b ° after development, and a step-by-step note, & using a halftone mask, using known The diffractive mask can also achieve the same contouring effect of the photo-patternable insulating layer 6 "7. It can also be used to generate the illuminating light. Different thickness techniques of the electrically insulating layer (preferably in a single processing step) are used to achieve the same result. For example, a known double exposure method can be used. The double exposure technique will apply one. The first mask is then coated with a second mask. The exposure light intensity or wavelength distribution between the first exposure and the second exposure may not be the same. Figure 2 is a known electronic circuit component. A schematic diagram of an embodiment. An active matrix display device typically includes a plurality of display elements, which will be referred to as pixels or pixels. The one shown in Figure 2 is based on a so-called bottom gate TFT. A schematic representation of a single pixel element of a display. This structure is typically constructed starting from a substrate having a first conductor layer. The conductor layer is then patterned to define a gate line 22' a gate electrode 23' of the TFT switch and an electrical 13200924107 pole 32 of the library capacitor 27. This layer can be directly covered by a non-conductor layer 33 which acts as an insulating layer and a dielectric layer. In the outer boundary of the display, the non-conductor layer is provided with a plurality of holes or through holes for facilitating electrical contact of the gate lines. Optionally, in order to reduce the possible yield loss due to the open gate line inside the display area, it may be partially paralleled by a second conductive layer 31 passing through the contact hole 30 in the non-conductive layer 33. Interpole line. The same way to create a parallel connection between two conductor layers can also be used for the line circuit (not shown here). In the latter case, the parallel structure is generated by the first conductor layer and is connected via the same via. Next, a second conductive layer is provided and patterned to define the data line or row line 21, the source electrode of the TFT, the channel region 24, the drain electrode 26 of the TFT, the pixel electrode 28, and the storage capacitor. The second electrode of = and will define the parallel layer 31 of the gate line 22. In order to create a functional TFT', a semiconductor layer may also be provided before or after the application of the second. This half (four) can be covered by a passivation layer to protect the semiconductor layer. Other designs can also be used, such as the top gate TFTe. In addition, the figure also shows: two sections 'see A-A, -c. The thickness of the dielectric layer 33 is the same in all of the display; the area of the dielectric layer 33 is very unfavorable. Figure 3 is a schematic illustration and diagram of an embodiment of the method according to the present invention. In accordance with the teachings of the present invention, a 2 patternable insulating layer is selected for the insulating layer, which is patterned using halftone exposure to produce regions of insulating material having different thicknesses. In an organic-based active matrix, the non-conductive layer 33 (which acts as 14 200924107::2::): can be made of an organic layer (for example, see the figure for it = 1 machine layer) It may be beneficial to manufacture flexible displays, because Method 2::: is superior to inorganic materials and can be used for flexibility and curling through a simple and inexpensive method. The display does not cause cracks in the layer 4 - in a preferred embodiment, the photopatternable material (for example, a photo-patternable organic layer): is a non-conductor layer because no additional The etching and stripping process steps can complete the construction operation. It will be obtained—including the structure of insulators having different thicknesses j Al, A2, B1, B2, C1, C2, and c3. The thicknesses A1, A2, B1, B2, 〇, c2, C3 are different from each other. For example, the difference is at least 10 to 20 percent, and the best is '20 150 percent, which is the best. The system, the difference is more than 50%. It should be understood that although the dielectric layer is formed to include two different The thickness may be sufficient; however, this embodiment also encompasses including more regions consisting of dielectric materials having individual specific thicknesses. In each region having a particular thickness, the thickness may vary less than its value. For example, 'the present invention finds that 'relative to a certain layer selected in the prior art' is preferred from a thicker layer composed of the insulating material'. See Figure 3. Layer The change in conductivity of 33a is achieved by using a halftone mask. In this example, the cross-sectional area of the insulating layer between conductors 29a and 32a is relatively thick as shown in section AA. The dielectric of the storage capacitor. The thickness will be chosen to be thinner in the storage capacitor region BB. In the TFT region, 'in the design of the proposed example, the channel region will exhibit a thinner 15 200924107, short circuit (ci and c2) The electric layer. In this case, the risk will decrease. μ will affect the on-current, because the channel area of the tft is 24, and the lei mass degree η is still very small. It should be understood that ', "匕 design, and Departing from the scope of the invention will. A schematic diagram of an embodiment of an electronic circuit system FIG. 4 is not in accordance with the method of the present invention is made = member. F comprising the method according to the present invention.

…驟。:在-基板上沉積一第一導電層，用以形成一由第一 電子益件與第二電子器件所組成的第一導體層"冗積一可 光圖案化電絕緣材料層，該層會被設計成在空間上被排列 在該第-導電層與一第二導電層之間；光圖案化該可光圖 案化電絕緣材料層，用以在被該第一電子器件覆蓋的區域 中提供該層的第一厚度以及在被該第二電子器件覆蓋的區 域中提供該層的第二厚度；ί冗積由料體材料所組成的第 一層。所生成的結構40包括複數個具有第一厚度的區域 42，一個第二厚度的區域4丨，以及視情況會有複數個具有 零厚度的區域43。在圖4的略圖（b)中，因而所形成的電絕 緣層會重疊一顯示器矩陣的像素區41，已參考圖2做過討 論。區域42a和該介電材料會被完全移除的區域有關。 圖5所示的係根據本發明的電子電路元件的另一實施 例的概略示意圖。導電層51、52會被一或多層電絕緣層分 離。其它的導電層54、54a、54b和該電子電路中所使用的 另外導體有關。導體51、54、54a以及54b會被產生在相同 的導體層之中。電絕緣層50可能係以由二或多層33a、33b 200924107 所組成的堆疊為基礎，其堆疊提供頂層…包括可光圖案化 類塑。接著便可以使用該可光圖索化層33a作為料來溶解 或蚀刻該絕緣層堆疊的其它層33b。可以濕式或乾式來完成 蝕刻。該些其它層可經過選擇，用以最佳化其功能，例如 經改善的電性崩潰，或者’於頂端間極裝置的情況中，其 可作為該半導體的保護層。元件符號33b所示的層可能為 有機或無機類型，其選擇的方式會使其針對較佳的操作I 命或功能或兩者而被最佳化。舉例來說，對層3儿來說可 可以選擇實質上沒有帶電载子的絕緣材料。舉例來說，可 以使用聚蝉烴。無機層33b的其中一範例包括石夕的氮化物 (隱）。於頂端間極TFT設計的情況中，層说可被加入 作為一合宜半導體的保護層。 圖6所㈣係根據本發明的電子裝置的一實施例。電 子設備60可能係關於一行動電話、一掌上型電腦、—電子 記事薄（electronic organizer)、或是包括—與殼體^協同運 作之顯示器的任何其它可攜式電子裝置。請注意，可能會 使用-可撓性顯示器作為該顯示器。對該可撓性顯示器來 說’殼體62可能會被排列成可展開並且可纏繞核心63，從 而讓可撓性顯示器64可被設計成在使料會從其摺疊_ 伸展為伸展狀態。為在使用期間支撐該可撓性顯示器並且 保屢該可撓性顯示器使其不會遭受機械性破壞，殼體 能包括剛性部分63a ’其會被設計成至少部分收納及 撐該可撓性顯示器的邊緣部分64a、64b。應該明白的係， 在忒體62的摺疊與展開期間，可撓性顯示器64的某些部 17 200924107 件會變形，而該可趙 任何變形。在勺括示器的其它部件則實質上不會有 二1在包括可撓性顯示器之根據本發明的電子設備 的替代實施例中，兮可枝t J c ^ x m 被排列在殼體62之°;的2顯示器可被排列成可以繞著-該可撓性顯示器的前端行捲繞。於此情況中， 用者在使用期間伸展琴已2具備一抓握部分，用以讓使 可撓㈣Μ ^ 可撓性顯示11。或者，該 上，俾使可以該此末端邱 月4被排列在個別的捲抽 r 展該可捷性顯示;ί彼此遠離的相對移動方式來伸 撓性顯示器的電子設備的其它實施例。會有G括該了 應該明白的係，絡扯， 施例；不過，、、、，"面已經說明過本發明的特定實 本發 …、可以上面所述以外的方式來實行本發明。 料，本發明的範，會H途而並非用來限制本發明的 出。此外，本文參考1 如申請專利範圍之中提 行組合。 > 5圖式所討論的獨立特點亦可以進 【圖式簡單說明 圖la、lb、以及 色調❹士、所示的係一習知曝光方法以及-半 法之實施例的概略示意圖。 圖2所不的係一已知的電子電路 示意圖 圖 意圖。 rai 件之實施例的概略 示 所示的係根據本發明的方法的—實施例的概略 200924107 電子 實施 圖4a與4b所示的係根據本發明的方法所製成的· 電路元件的實施例的概略示意圖。 圖5所示的係根據本發明的電子電路元件的另一 例的概略示意圖。 圖6所不的係根據本發明的電子裝置的一實施例 主要元件符號說明 1 UV透明區 2 uv不透明區 3 uv光半透明區 4 UV透明區 5 輻射強度下降 6 可光圖案化材料 6a 島狀體 6 b 島狀體 7 可光圖，案化材料 8 基板 10 半色調曝光方法 11 遮罩 11a 遮罩 12 (未定義） 13 生成結構 20 (未定義） 21 資料線路或行線路 19 200924107 22 閘極線路 23 閘極電極 24 通道區 25 源極電極 26 汲極電極 27 儲存電容器 28 像素電極 29 (未定義） 29a 導體 30 孔洞 31 第二導電層 32 儲存電容器電極 32a 導體 33 非導體層 33a 非導體層 33b 層 35 主動矩陣 40 生成結構 41 第二厚度區域 42 第一厚度區域 43 零厚度區域 50 絕緣層 51 導電層 52 導電層 20 200924107 54 導電層 54a 導電層 54b 導電層 60 電子設備 62 殼體 63 核心 63a 剛性部分 64 撓性顯示器 64a 邊緣部分 64b 邊緣部分 A1 介電質厚度 A2 介電質厚度 B1 介電質厚度 B2 介電質厚度 Cl 介電質厚度 C2 介電質厚度 C3 介電質厚度 21...then. Depositing a first conductive layer on the substrate to form a first conductor layer composed of the first electronic component and the second electronic device; a layer of a photo-patternable electrically insulating material Will be designed to be spatially arranged between the first conductive layer and a second conductive layer; photo patterning the photo-patternable electrically insulating material layer for use in the area covered by the first electronic device Providing a first thickness of the layer and providing a second thickness of the layer in a region covered by the second electronic device; 冗 redundantly forming a first layer of material. The resulting structure 40 includes a plurality of regions having a first thickness 42, a region 4 of a second thickness, and optionally a plurality of regions 43 having a thickness of zero. In the sketch (b) of Fig. 4, the thus formed electrically insulating layer overlaps the pixel region 41 of a display matrix, which has been discussed with reference to FIG. Region 42a and the dielectric material will be associated with a completely removed region. Fig. 5 is a schematic view showing another embodiment of an electronic circuit component according to the present invention. The conductive layers 51, 52 are separated by one or more layers of electrically insulating layer. The other conductive layers 54, 54a, 54b are associated with additional conductors used in the electronic circuit. The conductors 51, 54, 54a and 54b are produced in the same conductor layer. The electrically insulating layer 50 may be based on a stack of two or more layers 33a, 33b 200924107, the stack of which provides a top layer ... comprising a photopatternable plastic. The photo-patternable layer 33a can then be used as a material to dissolve or etch other layers 33b of the insulating layer stack. The etching can be done wet or dry. The other layers may be selected to optimize their function, such as an improved electrical collapse, or as a protective layer for the semiconductor in the case of a top interpole device. The layer shown by element symbol 33b may be of the organic or inorganic type, selected in such a way that it is optimized for better operation or function or both. For example, it is possible for layer 3 to select an insulating material that is substantially free of charged carriers. For example, polyfluorene hydrocarbons can be used. An example of the inorganic layer 33b includes a nitride (hidden) of Shi Xi. In the case of a top-end TFT design, the layer can be added as a protective layer for a suitable semiconductor. Fig. 6 (d) is an embodiment of an electronic device according to the present invention. The electronic device 60 may be associated with a mobile phone, a palmtop computer, an electronic organizer, or any other portable electronic device that includes a display that cooperates with the housing. Please note that a flexible display may be used as the display. For the flexible display, the housing 62 may be arranged to be deployable and wrap around the core 63 so that the flexible display 64 can be designed to stretch from its folded to extended position. To support the flexible display during use and to protect the flexible display from mechanical damage, the housing can include a rigid portion 63a that can be designed to at least partially receive and support the flexible display. Edge portions 64a, 64b. It should be understood that during the folding and unfolding of the carcass 62, certain portions of the flexible display 64 may be deformed, and any such deformation may occur. In the alternative embodiment of the electronic device according to the invention comprising a flexible display, the other components of the scoop singer are not arranged in the housing 62. The 2 displays can be arranged to be wound around the front end of the flexible display. In this case, the user has extended the piano 2 during use to have a grip portion for making the flexible (four) Μ ^ flexible display 11. Alternatively, the upper end of the electronic device that extends the flexible display can be arranged in a separate manner in the individual scrolling. The invention may be understood by a method other than that described above. It is to be understood that the scope of the invention is not intended to limit the invention. In addition, this document refers to 1 as proposed in the scope of patent application. < 5 The independent features discussed in the drawings can also be briefly described [Fig. 1a, lb, and the color tone gentleman, the conventional exposure method shown, and the schematic diagram of the embodiment of the semi-method. Figure 2 is a schematic view of a known electronic circuit. A schematic representation of an embodiment of a rai device is shown in accordance with the method of the present invention - an outline of an embodiment 200924107 electronically implementing the embodiment of a circuit component made in accordance with the method of the present invention shown in Figures 4a and 4b A schematic diagram. Fig. 5 is a schematic view showing another example of the electronic circuit component according to the present invention. 6 is an embodiment of an electronic device according to the present invention. Main component symbol description 1 UV transparent region 2 uv opaque region 3 UV light translucent region 4 UV transparent region 5 Radiation intensity reduction 6 Photopatternable material 6a Island Shape 6 b Island 7 Lighttable, material 8 Substrate 10 Halftone exposure method 11 Mask 11a Mask 12 (undefined) 13 Generating structure 20 (undefined) 21 Data line or line 19 200924107 22 Gate line 23 gate electrode 24 channel region 25 source electrode 26 drain electrode 27 storage capacitor 28 pixel electrode 29 (undefined) 29a conductor 30 hole 31 second conductive layer 32 storage capacitor electrode 32a conductor 33 non-conductor layer 33a Conductor layer 33b layer 35 active matrix 40 generating structure 41 second thickness region 42 first thickness region 43 zero thickness region 50 insulating layer 51 conductive layer 52 conductive layer 20 200924107 54 conductive layer 54a conductive layer 54b conductive layer 60 electronic device 62 housing 63 core 63a rigid portion 64 flexible display 64a edge portion 64b edge portion A1 dielectric A2 dielectric thickness of dielectric thickness B1 B2 dielectric thickness of dielectric thickness of dielectric thickness C2 dielectric thickness Cl C3 21

Claims (1)

200924107 、申請專利範困 種電子電路元件，其包括： _ 1 —電子 子器件以及該第电卞盗仵該第—電 用： 第一電子器件會被排列成用以共 _ 一第一導電層； "一第二導電層丨以及 - 一電絕緣層，1 a + Ba ^ 八在&間上係被排列在該第一導# 層與該第二導電層之間， .電 該電絕緣層包括一可本固& 子芎件霜甚Μ γ~ ^ 先圖案化材料，其在被該第一電 器件覆蓋的區域中且右笛 电 ΜΓ. ^ 八有第—厚度，而在被該第二電子_ 件覆盍的區域中具有第二厚度。 €子器 2_如申請專利範圍第丨項之 绍祕K电于電路70件，其中，該雷 '、、、彖層包括一可光圖案化有機材料。 〜3·如中請專利範圍第項之電子元件，其中， :電子器件及/或該第二電子器件可選自包括下面的；之 中·薄膜電晶體（TFT);雷宏 ;電谷态，或疋導電線路之間的跨接 緣路。 4.如任—前述中請專利範圍之電子元件，其中，該電絕 =層包括-由第-電絕緣材料所製成的底I卩及—由第二 =絕緣材料所製成的頂層，該第二電絕緣材料為可光圖案 5·如申請專利範圍第4項之電子元件，其中，該第一電 绝緣材料會利用該可光圖案化導電層作為圖案化遮罩而被 22 200924107 圖案化。 6·如申請專利範圍第5項之電子元件，其中，該第 絕緣材料係使用乾式蝕刻而被圖案化。 7. 一種電子裝置，其包括任-前述中請專 電路元件。 啤<电丁 8·如申請專利範圍第7項之電子裳置，其包括一顯示 器。 9.如申請專利範圍第8項之電 係一可挽性顯示器。 電子裳置，其中，該顯示器 -一種用以製造-包括-第—電子器件與一第二電子 器件的電子電路兀件的方法，其包括下面的步驟： -2 -基板上沉積一第一導電層，用以形成一由第 :電子器件與第二電子器件所組成的第—導體 層； 可光圖案化電絕緣材料層，該層會被設計 成在二間上被排列在#坌 3# π « 層之間； 層與一第二導電 •光圖案化該可光圖案化電絕緣材料届^ ^ % %啄柯料層，用以在被 : +器件覆蓋的區域中提供該層的第一厚 度以及在被該第二電子 廣的第二厚度； 牛覆羞的區域中提供該 Τ積由該導體材料所組成的第二層。 如申請專利範圍第1〇項之方法， 步驟：在沉積該可光圖宰 、，匕括下面 茉化電絕緣材料層之冑先沉積另一 23 200924107 電絕緣材料層。 12. 如申請專利範圍第10或u項之方法，其中，一半 色調遮罩會被使用於光圖案化該可光圖案化電絕緣材料層 的步驛。 13. 如申請專利範圍第10或11項之方法，其中，一繞 射遮罩會被使用於光圖案化該可光圖案化電絕緣材料層的 步驟。 項之方法，其中，一雙 可光圖案化電絕緣材料 ί200924107, applying for a patented electronic circuit component, comprising: _ 1 - an electronic sub-device and the first electronic device: the first electronic device is arranged to share a first conductive layer " a second conductive layer 丨 and - an electrically insulating layer, 1 a + Ba ^ 八 is interposed between the first conductive layer and the second conductive layer, The insulating layer comprises a sturdy & 芎 霜 Μ γ γ 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先 先The area covered by the second electron member has a second thickness. The sub-device 2_, as claimed in the scope of the patent application, is a 70-piece circuit in which the ',, and 彖 layers include a photo-patternable organic material. The electronic component of the above-mentioned patent scope, wherein: the electronic device and/or the second electronic device may be selected from the group consisting of: a thin film transistor (TFT); Lei Hong; , or the bridging path between the conductive lines. 4. The electronic component of the above-mentioned patent scope, wherein the electrical insulation layer comprises a bottom layer made of a first electrically insulating material and a top layer made of a second = insulating material. The second electrically insulating material is a light-emitting pattern. The electronic component of claim 4, wherein the first electrically insulating material is utilized as the patterned mask by the photo-patternable conductive layer 22 200924107 Patterned. 6. The electronic component of claim 5, wherein the first insulating material is patterned using dry etching. 7. An electronic device comprising any of the aforementioned circuit components. Beer <Electronics 8> The electronic skirt of claim 7 of the patent application includes a display. 9. The electrical system of claim 8 is a levisable display. Electronic display, wherein the display - a method for manufacturing an electronic circuit component comprising - a first electronic device and a second electronic device, comprising the steps of: - 2 - depositing a first conductive on the substrate a layer for forming a first conductor layer composed of: an electronic device and a second electronic device; a layer of photo-patternable electrically insulating material, the layer being designed to be arranged on two spaces at #坌3# π « between layers; a layer and a second conductive light patterning the photo-patternable electrically insulating material to provide a layer of the layer in the region covered by the + device A second layer consisting of the conductor material is provided in a thickness and in a region of the second thickness that is widened by the second electron; For example, in the method of claim 1, the method further comprises: depositing another 23 200924107 layer of electrically insulating material after depositing the photo-stainable layer, including the layer of the insulating layer of insulating material. 12. The method of claim 10, wherein the halftone mask is used to photopattern the layer of photopatternable electrically insulating material. 13. The method of claim 10, wherein a radiant mask is used to photopattern the layer of photopatternable electrically insulating material. The method of the item, wherein a pair of photopatternable electrically insulating materials ί 14.如申請專利範圍第1〇或u 重曝光方法會被使用於光圖案化該 層的步驟。 15.如申請專利範圍第14項之方法，其中，該雙重曝光 方Γ 第—遮罩來進行第1曝光，接著會使用 一第二遮罩來進行第二次曝光。 16. 如申請專利範圍第15項之方法，其中，第一次曝光 與第二次曝光的光強度並不相同。 17, 如申請專利範圍第15項之方 .^ , a . ^ 丹〒，苐一次曝光 與第二次曝光會使用不同的光波長分佈。 十一、圖式： 如次頁 2414. The method of photo-patterning the first layer or the u-exposure method will be used for the step of photo patterning the layer. 15. The method of claim 14, wherein the double exposure mask is used to perform the first exposure, and then a second mask is used for the second exposure. 16. The method of claim 15, wherein the light intensity of the first exposure and the second exposure is not the same. 17, such as the scope of the 15th patent application. ^, a. ^ Tanjong, 苐 one exposure and the second exposure will use different wavelength distribution of light. XI. Schema: as the next page 24
TW097137652A 2007-10-02 2008-10-01 An electronic circuit element with profiled photopatternable dielectric layer TW200924107A (en)

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