200903493 九、發明說明 【發明所屬之技術領域】 本發明是有關記憶被使用於電腦或各種電子機器 料之記憶裝置。 【先前技術】 近年來，作爲電腦的外部記憶裝置，有以CF c 〇 m p a c t f 1 a s h )(註冊商標）爲代表的記憶體卡，或 快閃磁碟機（USB flash drive)正普及著。在該等的 記憶裝置內藏有可重寫的非揮發性R Ο Μ的快閃記憶 對於快閃記憶體而言，有被稱爲SLC ( Single Level )型及 MLC( Multi Level Cell)型者（例如參照下 利文獻1 )。 〔專利文獻1〕特開2 0 0 2 - 8 3 8 0號公報 SLC型的快閃記憶體是從以往起被廣泛使用的記 ，每單記憶格（c el 1 )可記憶1位元的資訊之記憶體 下亦稱爲「二値記憶體」）。相對的，MLC型的快閃 體是每單記憶格可記億2位元以上的資訊之記億體（ 亦稱爲「多値記憶體」）。MLC型的快閃記憶體是各 格可取完全被充電的狀態、電力剩下3分之2的狀態 下3分之1的狀態、全部被放電的狀態等4個的狀態 每單記憶格記憶2位元的資訊。 一般，M L C型的快閃記憶體是具有動作低速，重 能次數少，相對的記憶容量比SLC型更大的特徴。另 的資 卡（ USB 外部 體。 Cell 記專 億體 (以 記億 以下 記憶 、剩 下， 寫可 一方 200903493 面，SLC型的快閃記憶體是具有動作高速，重寫可能次數 多，相對的記憶容量比M L C型更少的特徴。 【發明內容】 (發明所欲解決的課題） 考量如此的問題’本發明所欲解決的課題是在於提供 一種可活用S L C型的快閃記憶體及μ L C型的快閃記憶體 的兩者的特徴的優點之記憶裝置。 (用以解決課題的手段） 有鑑於上述課題，如其次般構成本發明之一形態的記 憶裝置。 亦即，一種記憶裝置，係可根據在記憶領域的開頭記 錄資料的管理資訊之特定的檔案系統來記憶資料之記憶裝 置’其特徵爲具備： 二値快閃記憶體，其係具有第1記憶領域，可每單記 憶格記憶2種類的値； 多値快閃記憶體，其係具有第2記憶領域，可每單記 憶格記憶3種類以上的値；及 控制部，其係一面將上述第1記憶領域配置於開頭的 領域，一面邏輯性地結合上述第1記憶領域與上述第2記 憶領域，而作爲單一的記憶領域之結合領域來進行資料的 讀寫。 若根據上述形態的記億裝置’則會將二値快閃記憶體 -5- 200903493 所具有的第1記憶領域配置於結合領域的開頭。因此，檔 案分配表（file allocation table，FAT)等的資料的管理 資訊會被寫入二値快閃記億體内。檔案分配表是〜旦進行 資料的寫入或消去則會被頻繁地重寫之管理資訊，因此藉 由將比多値快閃記憶體更能夠高速動作的二値快閃記憶體 配置於結合領域的開頭，可比全部的領域藉由多値快閃記 憶體所構成的記憶裝置更能高速地記憶資料。又，由於二 値快閃記憶體是具有比多値快閃記憶體更多重寫可能次數 的特徴，因此藉由將頻繁被重寫的檔案分配表寫入二値快 閃記憶體，能使資料記憶的可靠度提升。如此，若根據上 述形態的記億裝置，則可提供一面藉由使用多値快閃記憶 體來實現大容量化，一面藉由使用二値快閃記憶體來達成 動作的高速性或可靠度佳之記憶裝置。 在上述形態的記憶裝置中，上述控制部係具備： 位址變換部，其係進行上述結合領域與上述第1記憶 領域及上述第2記憶領域之間的位址變換；及 選擇部，其係按照上述位址變換的結果，從上述二値 快問記憶體及上述多値快閃記憶體之中選擇上述資料的讀 寫目的地。 若根據如此的形態，則可按照位址變換的結果來容易 /判別資料的讀寫目的地。 在上述形態的記憶裝置中，上述控制部係將藉由上述 @ ί止變換部來變換的位址傳送至上述二値快閃記憶體及上 ®多値快閃記憶體之後，將用以進行上述資料的讀寫之指 -6- 200903493 令傳送至上述所被選擇的快閃記憶體。 在如此的形態中，有關變換後的位址是傳送至全部的 快閃記憶體，然後，有關指令是只對所被選擇的快閃記憶 體傳送。若根據如此的形態，則不必從二値快閃記憶體及 多値快閃記憶體來選擇變換後的位址的傳送目的地，因此 可使處理速度提升。 在上述形態的記憶裝置中，上述第1記億領域可爲佔 上述結合領域的〇 . 5 %以上1 0 0 %未満的其中之一的比例之 領域。 藉由將第1記憶領域設定成如此的領域，可使檔案分 配表等的管理資訊確實地記憶於二値快閃記憶體内。 在上述形態的記憶裝置中，該記憶裝置係經由特定的 介面來與主裝置連接，上述控制部係按照來自上述主裝置 的指示來進行上述資料的讀寫。 若根據如此的形態，則可利用該記憶裝置作爲主裝置 的外部記憶裝置或内部記憶裝置。特定的介面是例如可利 用 USB、IEEE 1 3 94、並歹[J ( parallel ) ΑΤΑ、串歹IJ ( serial )ΑΤΑ等的介面。 在上述形態的記憶裝置中，上述控制部係從上述主裝 置接受該記憶裝置的記憶容量的詢問時，回覆上述結合領 域的記憶容量。 若根據如此的形態，則並非各快閃記憶體所個別具有 的記憶容量，而是可將結合領域全體的容量通知主裝置。 在上述形態的記憶裝置中，具備複數個上述多値快閃 -7- 200903493 記憶體，上述控制部係一面將上述第1記憶領域配置於開 頭的領域，一面邏輯性地結合上述第1記憶領域與複數的 上述第2記憶領域。 若根據如此的形態’則可形成具備複數個多値快閃記 憶體的形態，因此可提供具有大容量的記憶領域之記憶裝 置。 本發明亦可作爲其次那樣形態的記憶裝置使用。 亦即，一種記憶裝置’係可根據在記憶領域的開頭記 錄資料的管理資訊之特定的檔案系統來記憶資料之記億裝 置，其特徵爲具備： 二値快閃記憶體，其係具有第1記憶領域，可每單記 憶格記憶2種類的値； 多値快閃記億體，其係具有比上述第1記憶領域更廣 的第2記憶領域，可每單記憶格記憶3種類以上的値； 比較部，其係比較由連接至該記億裝置的主裝置所指 定的位址與根據上述第1記億領域的最大容量所定之特定 的臨界値； 控制部，其係當上述位址爲上述臨界値内的位址時， 將資料的讀寫目的地切換至上述二値快閃記憶體，當上述 位址爲超過上述臨界値的位址時，將上述讀寫目的地切換 至上述多値快閃記憶體。 此形態的記憶裝置是藉由進行單純的控制，亦即按照 所指定的位址在多値快閃記憶體與二値快閃記憶體之間切 換資料的讀寫目的地，而可對特性相異的該等快閃記憶體 -8- 200903493 進行資料的讀寫。其結果，可提供一面藉由使用多値快閃 記憶體來實現大容量化，一面藉由使用二値快閃記憶體來 達成動作的高速性或可靠度佳之記憶裝置。 在上述形態的記憶裝置中，上述控制部，係上述讀寫 目的地被切換至上述二値快閃記憶體及上述多値快閃記憶 體的其中之一時，皆原封不動使用上述位址的値，而來對 上述二値快閃記憶體或上述多値快閃記憶體進行資料的讀 寫。 若根據如此的形態，則不需要將由主裝置所指定的位 址變換成其他體系的位址之處理，因此可謀求處理的單純 化。 在上述形態的記憶裝置中，上述控制部係從上述主裝 置接受該記憶裝置的記憶容量的詢問時，回覆上述第2記 憶領域的記憶容量。上述形態的記憶裝置的最大記憶容量 係與第2記憶領域一致。因此，可藉由原封不動返送第2 記憶領域的記憶容量之單純的處理來將該記憶裝置的記憶 容量通知主裝置。 【實施方式】 以下，爲了更明確上述本發明的作用·效果，根據實 施例來説明本發明的實施形態。 A.第1實施例： 圖1是表示作爲本發明的實施例之記憶裝置1 〇的槪 -9- 200903493 略構成的説明圖。本實施例的記憶裝置〗〇是經由USB介 面來與以電腦爲代表的主裝置8 〇連接’作爲外部記憶裝 置使用。主裝置80是以特定的檔案系統（Fati6或 F A T 3 2等）來將記憶裝置丨〇格式化而進行資料的讀寫。 如圖示，記憶裝置1 0是具備主控制器2〇，更具備與 該主控制器20連接’分別具有NAND快閃記憶體的第i 曰己億體單兀3 0、桌2 g己憶體單元4 0、第3記憶體單元5 0 、及第4記憶體單元6 0。 第1記憶體單元30是具備SLC ( Single Level Cell) 型的NAND快閃記憶體的二値記憶體3 1。又，第1記憶 體單兀3 0具備按照電氣特性來控制該二値記憶體31的第 1單元控制器32。在本實施例中，第1單元控制器32爲 採用泛用的CF卡用的記憶體控制器。第！單元控制器32 是從主控制器20接收根據ΑΤΑ規格的指令或資料，對二 値記憶體3 1進行資料的讀寫。在本實施例中，第1記憶 體單元3 0是具有1 G位元組（b y t e )份的記憶領域。無法 以1個的二値記憶體3 1來實現1 G位元組份的記憶領域時 ，可對第1單元控制器3 2連接複數個的二値記憶體31， 藉此來實現1 G位元組的記憶領域。 第2記憶體單元40是具備MLC ( Multi Level Cell ) 型的NAND快閃記憶體的多値記憶體4 1。本實施例的多 値記憶體41是可記憶4値（2位元）的資訊之記憶體。當 然，多値記憶體4 1可以採用能夠記憶3値以上的資訊之 記憶體。第2記億體單元40更具備按照電氣特性來控制 -10- 200903493 該多値記億體4 1的第2單元控制器42。在本實施例中， 第2單元控制器42是與第1記億體單元30同樣，採用泛 用的CF卡用的記憶體控制器。第3記憶體單元50及第4 記憶體單元60是與第2記憶體單元40同一構成。在本實 施例中，第2記憶體單元4 0、第3記憶體單元5 0、及第4 記憶體單元6 0是分別具有1 5 G位元組份的記憶領域。因 此’本實施例的記憶裝置 10全體爲具有 46G ( 1G+15G+15G + 15G)位元組份的記憶領域。另外，無法以 1個的多値記憶體來實現1 5 G位元組份的記憶領域時，可 對單元控制器連接複數個的多値記憶體來實現1 5 G位元組 的記憶領域。 主控制器20是按照來自經由USB介面而連接的主裝 置80之指示，對各記憶體單元30〜60控制資料的讀寫之 積體電路。主控制器20具備匯流排變換電路21及單元管 理電路22作爲内部電路。 匯流排變換電路21是具備將從主裝置80接受之根據 USB規格的信號予以變換成根據 ATA ( Advanced Technology Attachment)規格的信號之機能。所謂 ΑΤΑ 是電腦與記憶裝置之標準的通信介面。根據ΑΤΑ規格的 信號，例如有3個的位址信號A 0〜A2，或1 6的資料信號 D00〜D 1 5，復位信號等的控制信號。 單元管理電路22是具有邏輯性結合各記憶體單元30 〜6 0所具備的二値記憶體或多値記憶體的記憶領域而作爲 單一的記憶領域處理的機能。單元管理電路22是根據藉 -11 - 200903493 由匯流排變換電路21而變換的ΑΤΑ信號的LBA ( Logical Block Addressing)位址來進行位址變換，而實現各記億 體單元3 0〜60的邏輯性結合。所謂LB A是在記憶領域的 所有扇區（sector)分配序號，依據該序號來指定進行存 取的扇區之方式。LBA位址是依據該序號來表示。另外， 「L B A位址」亦稱爲「L B A參數」。 圖2是表示藉由單元管理電路22來進行的位址變換 的槪念説明圖。在圖的左側是表示單元管理電路22所管 理的各記憶體單元3 0〜60的記憶領域。如圖示，在本實 施例中，第1記憶體單元3 0内的記憶領域是以「〇」〜「 W」的LB A位址來表示。又，第2記憶體單元40是以「〇 」〜「X」的LBA位址來表示，第3記憶體單元是以「〇 」〜「Y」的LBA位址來表示，第4記憶體單元是以「〇 」〜「Z」的L B A位址來表示。 圖2的右側是表示結合各記億體單元30〜6〇的記憶 領域之後的記憶領域。如圖示，單元管理電路2 2是將第1 記憶體單元3 0所具備的二値記憶體3 1的記憶領域配置於 開頭的領域，然後’配置其他的記憶體單元40〜60所具 備的多値記憶體4 1〜6 1的記憶領域。結合後的記憶領域 ，如圖2所示，以「0」〜「W + X + Y + Z」的LBA位址來表 示。在單元管理電路22如此地進行記憶領域的結合下， 主裝置8 0可將記憶裝置1 〇内的記憶領域當作以「〇」〜 「W + X + Y + Z」的連續LBA位址所表示者來辨識。在以下 的説明中是將結合後的記憶領域稱爲「結合領域UA」。 -12- 200903493 圖3是表示單元管理電路22的内部構成的模式方塊 圖。單元管理電路2 2，除了上述的位址變換以外，還具有 將從主裝置8 0發行的A T A指令或資料轉送至各記億體單 元3 0〜6 0的機能。圖3是表示用以實現此轉送機能的内 部構成。 各記憶體單元30〜60所具備的單元控制器32〜62是 分別具備準照ΑΤΑ規格之所謂指令區塊暫存器的8種類 的暫存器。此8種類的暫存器是分別爲（1 )特徵暫存器 (Feature Register) 、（2)扇區g十數暫存器、（3)裝置 /磁頭暫存器、（4 )磁柱高位暫存器（Cylinder High Register) 、 （5)磁柱低位暫存器（Cylinder Low200903493 IX. Description of the Invention [Technical Field] The present invention relates to a memory device in which memory is used in a computer or various electronic devices. [Prior Art] In recent years, as an external memory device of a computer, a memory card represented by CF c 〇 m p a c t f 1 a s h ) (registered trademark), or a flash drive (USB flash drive) is becoming widespread. Flash memories with rewritable non-volatile R Ο 内 in these memory devices are known as SLC (Single Level) and MLC (Multi Level Cell) for flash memory. (For example, refer to the following document 1). [Patent Document 1] Japanese Patent Publication No. 2 0 0 2 - 8 3 8 0 The flash memory of the SLC type is widely used from the past, and each memory cell (c el 1 ) can memorize one bit. The memory of information is also known as "two-dimensional memory". In contrast, the MLC-type flash is a piece of information (also known as "multiple memory") in which information can be recorded in more than two hundred bits per single memory. The MLC type flash memory is a state in which each cell can be completely charged, a state in which one third of the power is left in two thirds, and a state in which all are discharged. Bit information. In general, the M L C type flash memory has the characteristics of low speed operation, low number of repetitions, and relatively large memory capacity than the SLC type. Another card (USB external body. Cell record special billion body (to remember less than 100 million memory, left, write one can be 200,903,493 face, SLC type flash memory is high speed, rewrite possible times, relative [Explanation] The problem to be solved by the present invention is to solve the problem of the present invention. The problem to be solved by the present invention is to provide a flash memory and μ LC which can utilize the SLC type. A memory device that is advantageous in both of the types of flash memory. (Means for Solving the Problem) In view of the above problems, a memory device according to one aspect of the present invention is configured as a second. A memory device that memorizes data according to a specific file system that records management information of data at the beginning of the memory field. It is characterized by: two flash memory, which has a first memory field and can be used for each memory cell. Memory 2 types of 値; multi-flash memory, which has a second memory field, can store more than 3 types of 每 in each memory; and control department, its system The first memory area is placed in the first field, and the first memory area and the second memory area are logically combined, and data is read and written as a combination field of a single memory field. The device of the device will be placed in the beginning of the field of integration in the first memory area of the second flash memory-5-200903493. Therefore, management information of data such as file allocation table (FAT) It will be written into the body of the flash memory. The file allocation table is the management information that is frequently rewritten when the data is written or erased, so that it can be faster than the multi-flash memory. The two-flash memory of the action is placed at the beginning of the combination field, and the data can be memorized more quickly by the memory device composed of multiple flash memory than all the fields. Moreover, since the two-flash memory has More than the flash memory, it rewrites the characteristics of the number of possible times, so by writing the frequently rewritten file allocation table to the second flash memory, the data memory can be made available. In this way, according to the above-described form of the device, it is possible to provide a high-speed operation by using a multi-turn flash memory while achieving a large capacity by using a multi-flash memory. In the memory device of the above aspect, the control unit includes: an address conversion unit that performs address conversion between the combination field and the first memory area and the second memory area; And a selection unit that selects a read/write destination of the data from the two-dimensional fast memory and the plurality of flash memories according to the result of the address conversion. In the memory device of the above aspect, the control unit transmits the address converted by the @?? After the memory and the upper flash memory, the -6-200903493 command for reading and writing the above data is transmitted to the selected flash memory. In such a form, the translated address is transferred to all of the flash memory, and then the instructions are transmitted only to the selected flash memory. According to this aspect, it is not necessary to select the transfer destination of the converted address from the binary flash memory and the multi-flash memory, so that the processing speed can be improved. In the memory device of the above aspect, the first field can be a field in which the proportion of one of the above-mentioned combination fields is 5% or more. By setting the first memory area to such a field, management information such as a file allocation table can be surely memorized in the flash memory. In the memory device of the above aspect, the memory device is connected to the host device via a specific interface, and the control unit reads and writes the data in accordance with an instruction from the host device. According to such a form, the memory device can be used as an external memory device or an internal memory device of the master device. The specific interface is, for example, an interface that can utilize USB, IEEE 1 3 94, parallel [J (parallel), serial IJ (serial), etc. In the memory device of the above aspect, the control unit replies to the memory capacity of the combination area when the main unit receives an inquiry about the memory capacity of the memory device. According to such an aspect, the memory capacity of each of the flash memories is not the same, and the capacity of the entire area of the combination can be notified to the host device. In the memory device of the above aspect, the memory device includes a plurality of the plurality of flash memory -7-200903493 memories, and the control unit logically combines the first memory region by arranging the first memory region in a field of the beginning. With the above plural second memory field. According to such a form, a form having a plurality of multi-flash flash memories can be formed, so that a memory device having a large capacity in the memory field can be provided. The present invention can also be used as a memory device of the next form. That is, a memory device is a device that memorizes data according to a specific file system that records management information of data at the beginning of the memory field, and is characterized by: two-flash memory, which has the first In the field of memory, you can remember two types of 每 in each memory; more than one billion, the system has a second memory field that is wider than the first memory field, and can store more than three types of 每 in each memory; a comparison unit that compares an address specified by a host device connected to the device and a specific threshold determined according to a maximum capacity of the first channel; and a control unit, wherein the address is When the address in the threshold is changed, the read/write destination of the data is switched to the second flash memory, and when the address is an address exceeding the critical threshold, the read/write destination is switched to the multi-turn Flash memory. The memory device of this form is capable of switching the data read/write destination between the flash memory and the binary flash memory by performing simple control, that is, according to the specified address, Different such flash memory-8- 200903493 for reading and writing data. As a result, it is possible to provide a high-speed or reliable memory device that achieves a large capacity by using a multi-flash memory and achieves an operation by using a two-flash memory. In the memory device of the above aspect, the control unit is configured to use the address address as it is when the read/write destination is switched to one of the two-way flash memory and the multi-turn flash memory. And reading and writing data to the above-mentioned two-flash memory or the above-mentioned multi-flash memory. According to this aspect, it is not necessary to convert the address specified by the host device into the address of another system, so that the processing can be simplified. In the memory device of the above aspect, the control unit replies to the memory capacity of the second memory area when the main device receives an inquiry about the memory capacity of the memory device. The maximum memory capacity of the memory device of the above aspect is consistent with the second memory field. Therefore, the memory capacity of the memory device can be notified to the host device by a simple process of returning the memory capacity of the second memory area as it is. [Embodiment] Hereinafter, in order to clarify the actions and effects of the present invention described above, embodiments of the present invention will be described based on the embodiments. A. First Embodiment: Fig. 1 is an explanatory view showing a schematic configuration of a memory device 1 作为 -9-200903493 as an embodiment of the present invention. The memory device of the present embodiment is used as an external memory device via a USB interface to be connected to a host device 8 represented by a computer. The main device 80 formats the memory device by a specific file system (Fati6 or F A T 3 2, etc.) to read and write data. As shown in the figure, the memory device 10 is provided with a main controller 2, and further has a connection with the main controller 20, which has a NAND flash memory, respectively, and a table ii. The body unit 40, the third memory unit 50, and the fourth memory unit 60. The first memory unit 30 is a binary memory 31 having a SLC (Single Level Cell) type NAND flash memory. Further, the first memory unit 30 has a first unit controller 32 that controls the binary memory 31 in accordance with electrical characteristics. In the present embodiment, the first unit controller 32 is a memory controller for a general-purpose CF card. The first! The unit controller 32 receives the command or data according to the ΑΤΑ specification from the main controller 20, and reads and writes the data to the memory 31. In the present embodiment, the first memory unit 30 is a memory area having 1 G bytes (b y t e ). When the memory area of the 1 G-bit component cannot be realized by one binary memory 3 1 , a plurality of binary memory 31 can be connected to the first unit controller 32 to realize the 1 G-bit. The memory area of the tuple. The second memory unit 40 is a multi-turn memory 41 having an MLC (Multi Level Cell) type NAND flash memory. The multi-layer memory 41 of this embodiment is a memory that can memorize information of 4 値 (2 bits). Of course, the memory 4 1 can use a memory capable of memorizing more than 3 inches of information. The second unit unit 40 is further controlled in accordance with electrical characteristics. -10-200903493 The second unit controller 42 of the multi-body unit 41 is provided. In the present embodiment, the second unit controller 42 is a memory controller for a general-purpose CF card, similarly to the first unit cell 30. The third memory unit 50 and the fourth memory unit 60 have the same configuration as the second memory unit 40. In the present embodiment, the second memory unit 40, the third memory unit 50, and the fourth memory unit 60 are memory areas each having a 15 G bit composition. Therefore, the memory device 10 of the present embodiment is a memory field having a 46G (1G+15G+15G + 15G) bit component as a whole. In addition, when the memory area of the 1 5 G bit component cannot be realized in one multi-turn memory, a plurality of multi-turn memories can be connected to the cell controller to realize the memory field of the 1 5 G byte. The main controller 20 is an integrated circuit for controlling the reading and writing of data to the respective memory cells 30 to 60 in accordance with an instruction from the main device 80 connected via the USB interface. The main controller 20 includes a bus bar conversion circuit 21 and a cell management circuit 22 as internal circuits. The bus bar conversion circuit 21 is provided with a function of converting a signal according to the USB standard received from the host device 80 into a signal according to the ATA (Advanced Technology Attachment) standard. The so-called ΑΤΑ is the standard communication interface between computers and memory devices. According to the signal of the ΑΤΑ specification, for example, there are three address signals A 0 to A2, or 16 data signals D00 to D 1 5, and control signals such as reset signals. The unit management circuit 22 is a function of processing in a single memory area by logically combining the memory areas of the two-dimensional memory or the multi-turn memory of each of the memory units 30 to 60. The unit management circuit 22 performs address conversion based on the LBA (Logical Block Addressing) address of the ΑΤΑ signal converted by the bus line conversion circuit 21 by -11 - 200903493, thereby realizing the logic of each unit of the body unit 3 0 to 60 Sexual union. The LB A is a sector number assigned to all sectors in the memory area, and the manner in which the sector to be accessed is specified according to the sequence number. The LBA address is represented by the serial number. In addition, "L B A address" is also called "L B A parameter". Fig. 2 is a conceptual explanatory view showing an address conversion performed by the unit management circuit 22. On the left side of the figure, the memory area of each of the memory cells 30 to 60 managed by the cell management circuit 22 is shown. As shown in the figure, in the present embodiment, the memory area in the first memory unit 30 is represented by the LB A address of "〇" to "W". Further, the second memory unit 40 is represented by an LBA address of "〇" to "X", and the third memory unit is represented by an LBA address of "〇" to "Y", and the fourth memory unit It is represented by the LBA address of "〇" to "Z". The right side of Fig. 2 shows the field of memory after combining the memory areas of the respective unit cells 30 to 6〇. As shown in the figure, the unit management circuit 2 2 arranges the memory area of the binary memory 3 1 included in the first memory unit 30 in the first field, and then "disposes the other memory units 40 to 60. Multi-値 memory 4 1~6 1 memory area. The combined memory area, as shown in Fig. 2, is represented by the LBA address of "0" to "W + X + Y + Z". In the combination of the memory management area by the unit management circuit 22, the main device 80 can treat the memory area in the memory device 1 as a continuous LBA address of "〇"~"W + X + Y + Z". The indicator is to identify. In the following description, the combined memory area is referred to as "combination field UA". -12- 200903493 Fig. 3 is a schematic block diagram showing the internal configuration of the unit management circuit 22. The unit management circuit 2 2 has a function of transferring the A T A command or data issued from the host device 80 to the respective units 100 to 60 in addition to the address conversion described above. Fig. 3 is a view showing the internal configuration for realizing this transfer function. The unit controllers 32 to 62 included in each of the memory units 30 to 60 are eight types of registers each having a so-called command block register of a standard specification. The eight types of registers are (1) Feature Register, (2) Sector g tens register, (3) Device/head register, (4) Magnetic column high Cylinder High Register, (5) Magnetic Column Low Register (Cylinder Low)
Register ) 、 （6)扇區號碼暫存益、（7)指令暫存器、 (8 )資料暫存器。單元控制器32〜62是按照設定於該等 的暫存器之各種的參數來控制對二値記憶體或多値記憶體 之資料的讀寫。主裝置80是在進行資料的讀寫時，將對 該等的暫存器之存取信號傳送至記憶裝置1 〇。 單元管理電路2 2是一旦經由U S B介面及匯流排變換 電路2 1來從主裝置8 0接受上述的存取信號，則可按照存 取對象的暫存器的種類來使對各記億體單元30〜60之存 取信號的轉送方法改變。單元管理電路22爲了判別存取 對象的暫存器的種類，而具備暫存器判別電路78。 暫存器判別電路7 8是按照從匯流排變換電路2 1輸入 的位址信號A 0〜A 2的狀態，根據A T A規格來判別存取對 象的暫存器的種類。暫存器判別電路7 8是例如圖示那樣 -13- 200903493 ，若位址信號A 2爲「0」，位址信號A1爲「〇」，位址 信號Α0爲「1」，則可判別輸入對特徵暫存器的存取信號 〇 單元管理電路22是有關在從主裝置80接受對特徵暫 存器及扇區計數暫存器的存取信號時，原封不動通過，而 對全部的記憶體單元30〜60傳送此存取信號。因爲該等 的暫存器並非是用以直接指定結合領域UA内的位置者。 具體而言，特徵暫存器是爲了按照ΑΤΑ指令來指定各種 的參數而使用的暫存器，扇區計數暫存器是在連續存取複 數的扇區時，用以指定該扇區數的暫存器。有關連續存取 時的「開頭扇區」的指定是使用後述的裝置/磁頭暫存器 、磁柱高位暫存器、磁柱低位暫存器、扇區號碼暫存器。 裝置/磁頭暫存器、磁柱高位暫存器、磁柱低位暫存 器、扇區號碼暫存器是爲了指定結合領域UA内的位置（ 扇區）而使用的暫存器。在該等的暫存器分別輸入有表示 結合領域UA内的扇區之LBA位址的一部份。具體而言， 右LBA位址爲28位兀長的爹數，則在扇區號碼暫存益輸 入第〇位元〜第7位元的位元列，在磁柱低位暫存器輸入 第8位元〜第1 5位元的位元列。並且，在磁柱高位暫存 器輸入第1 6位元〜第23位元的位元列，在裝置/磁頭暫 存器輸入第24位元〜第27位元的位元列。若單元管理電 路22接受對該等的暫存器之存取信號，則會將該信號一 旦問鎖於問鎖電路7 0〜7 3而記憶。 被閂鎖於閂鎖電路70〜73的存取信號會被輸入至位 -14- 200903493 址解碼器90。位址解碼器90是具備結合離散於各閂鎖電 路7 0〜7 3而記憶的L B A位址，使2 8位元長的L B A位址 復原的機能。又，位址解碼器90具備比較復原後的LB A 位址與各記憶體單元的最大扇區數之機能。有關此機能的 詳細會在往後敘述。 指令暫存器是用以指定根據ΑΤΑ規格的各種指令之 暫存器。就如此的指令而言，例如有從指定的扇區讀出資 料的讀出扇區指令、對指定的扇區寫入資料的寫入扇區指 令。一旦單元管理電路22接受對指令暫存器的指令信號 ’則會將該信號輸入至指令解碼器9 1及閂鎖電路7 4。 一旦指令解碼器9 1輸入指令信號，則會判別輸入的 指令種類，將該判別結果輸出至位址變換電路9 2及單元 選擇器94。被輸入至閂鎖電路74的指令信號會至有來自 單元選擇器94的輸出指示爲止，保持於閂鎖電路74。 位址變換電路92’如圖2所示，具備將有關從位址解 碼器9 0輸入的結合領域υ Α的L Β Α位址變換成各記憶體 單元30〜60的LBA位址之機能。具體而言，位址變換電 路92是從位址解碼器90輸入LBA位址，更從指令解碼 器9 1輸入指令的種別。然後’判斷輸入的指令種別是否 爲需要LBA位址的指令。所謂需要LBA位址的指令，一 般是指定位址（扇區），而對指定的位址進行何種的存取 之’例如有「讀出扇區指令」、「寫入扇區指令」、 「讀出多工（multiple )指令」、「寫入多工指令」、「 讀出DMA指令」、「寫入DMA指令」、「讀出確認（ 200903493 verify)扇區指令」「尋找（seek)指令」等。若位址變 換電路9 2判斷輸入的指令種別爲需要l B A位址的指令， 則會將從位址解碼器9 0輸入的L B A位址變換成各記憶體 單元的LBA位址（有關變換方法會在往後敘述），且將 變換後的LBA位址轉送至全部的記憶體單元30〜60。如 後述，主控制器20不是對複數的記憶體單元同時轉送需 要LBA位址的ΑΤΑ指令，因此變換後的LBA位址可轉送 至所有的記憶體單元3 0〜6 0。如此一來，位址變換電路 92可省略選擇轉送目的地的處理。當然，可只對該當的記 憶體單元轉送變換後的LBA位址。 若從指令解碼器9 1輸入的指令種別爲不需要LBΑ位 址的指令，則位址變換電路92會將從位址解碼器90輸入 的參數予以原封不動轉送至全部的記憶體單元3 0〜60。因 爲在不需要LBA位址的指令時，輸入至裝置/磁頭暫存器 等的存取信號並非限於表示LBA位址。所謂不需要LBA 位址的指令是不進行位址（扇區）的指定來對快閃記憶體 進行何種的操作之指令，例如有「識別裝置指令」、「設 定特徵指令」、「檢查功率模式指令」、「靜止狀態（ sleep)指令」、「待命指令」、「空轉指令」等。另外， 位址變換電路92是即使從指令解碼器9 1輸入的指令種別 爲不需要LBA位址的指令時，照樣可與需要LBA位址的 指令同樣，對記憶體單元3 0〜60傳送變換後的LB A位址 。因爲不需要LBA位址的指令是無關LBA位址的有無來 執行的指令。當然，至變換爲止進行傳送’但亦可爲不傳 -16- 200903493 送有關變換後的L B A位址之構成。 單元選擇器94是根據從位址解碼器90輸入的 位址來選擇指令的轉送目的地的記憶體單元之電路。 而言，單元選擇器94會從位址解碼器90輸入LB A ，更從指令解碼器91輸入指令的種別。然後，判斷 的指令種類是否爲需要LBA位址的指令。若爲需要 位址的指令，則單元選擇器94會根據輸入的LBA位 進行選擇指令的轉送目的地的記憶體單元之處理。該 的詳細會在往後述敘述。一旦單元選擇器94進行轉 的地的記憶體單元的選擇，則控制第1開關電路96， 該轉送目的地的記憶體單元與閂鎖電路74。如此一來 保持於閂鎖電路74的指令信號會被傳送至所選擇的 體單元。 被保持於閂鎖電路7 4的指令信號輸出至各單元 序是被設定成位址變換後的LBA位址會從位址變換 92傳送至各記憶體單元，且依單元選擇器94來完成 開關電路96的開關之後的時序。因爲ΑΤΑ規格是規 傳送需要L Β Α位址的指令之前，必須預先將l Β Α位 定於暫存器。另外，若輸入的種類爲不需要LB a位 指令’則單元選擇器94會控制第1開關電路96，而 鎖電路74能夠連接至所有的記億體單元。如此一來 關不需要LBA位址的指令，可對全部的記憶體單元 轉送。當輸入的指令種類爲不需要LBA位址的指令 閃鎖電路74可爲不使指令的輸出延遲者。 LBA 具體 位址 輸入 LB A 址來 處理 送目 連接 ，被 記億 的時 電路 第1 定在 址設 址的 使閂 ，有 進行 時， -17- 200903493 若單元選擇器94根據輸入的Lba位址來控制第1開 關電路9 6 ’則同樣’第2開關電路9 8也控制。第2開關 電路9 8是用以切換對資料暫存器的存取信號之開關。一 旦根據單元選擇器9 4來切換第2開關電路9 8，則資料信 號也會被轉送至與被轉送需要LBA位址的指令的記憶體 單元相同的記憶體單元。 在第2開關電路9 8與暫存器判別電路7 8之間連接狀 態記憶電路79。在狀態記憶電路79中記憶有結合領域 UA全體的容量（全扇區數）、或表示記憶裝置10的製造 者資訊的裝置ID。通常，由主裝置8 〇要求狀態資訊的取 得時，是從以第2開關電路9 8所選擇的記憶體單元來返 送狀態資訊。但，例如依照「識別裝置」指令等，有記億 裝置1 〇所具有的扇區數的詢問、或裝置ID等的詢問時， 從該狀態記憶電路79對主裝置80返送狀態資訊。若爲如 此可從狀態記憶電路79返送狀態資訊的構成，則可對主 裝置80正確地傳達有關在各記憶體單元不能對應的記億 裝置1 0全體的狀態資訊。 圖4是表示藉由位址解碼器90及位址變換電路92來 實現的位址變換處理、及單元選擇器94所實現之記憶體 單元的選擇處理的流程之流程圖。以下將該處理稱爲「單 元管理處理」。 位址變換電路92會判斷從指令解碼器9 1輸入的指令 的種類是否爲需要LB A位址的指令（步驟S 1 0 )。其結果 ，若爲不需要LB A位址的指令（步驟S 1 0 : No )，則位址 -18- 200903493 變換電路92不進行位址變換’對全部的單元原封不動地 轉送輸入至裝置磁頭暫存器等的參數。另一方面’單元選 擇器94選擇全部的記憶體單元（步驟S20 )’終了處理 。如此一來，對全部的記憶體單兀轉送同一指令。另外， 如前述，在步驟S10中，即使判斷爲輸入不需要LBA位 址的指令時，位址變換電路92還是可與需要LBA位址的 指令同樣，進行以下那樣的位址變換。 在上述步驟S10中，若輸入的指令爲需要LBA位址 的指令（步驟S 1 0 : Yes )’則位址解碼器90會判斷輸入 的L B A位址η爲第1記憶體單元3 0的L B A位址的最大値 W (參照圖2 )以下（步驟S30 )。若LBA位址n爲最大 値W以下（步驟S3 0 : Yes )，則藉由位址變換電路92來 將變換後的LBA位址m設爲從位址解碼器90輸入之原封 不動的LBA位址η (步驟S40 )。然後，此情況，單元選 擇器94是選擇第1記憶體單元3 0作爲指令的轉送目的地 (步驟S 5 0 )。 在上述步驟S 3 0中，當判斷L Β Α位址η非爲第1記 億體單元3 0的LB Α位址的最大値W以下時（步驟s 3 0 : No)，位址解碼器9 0會判斷L Β A位址η是否爲第1記憶 體單元30的LBA位址的最大値W與第2記憶體單元4〇 的LBA位址的最大値X的和（W + X )以下（步驟S60 )。 若LBA位址η爲上述和（W + X)以下（步驟S60: Yes) ，則藉由位址變換電路92來將變換後的l β A位址m設爲 從L Β A位址η扣除弟1目己憶體單兀3 0的l Β A位址的最大 -19- 200903493 値w之値（步驟S70 )。然後，此情況，單元選擇器94 是選擇第2記憶體單元4〇作爲指令的轉送目的地（步驟 S80 ) ° 在上述步驟S 6 0中，當判斷L B A位址η非爲上述和 (W + X )以下時（步驟S60 : No )，位址解碼器90會判 斷LBA位址n是否爲第1記憶體單元30的LBA位址的最 大値W、第2記憶體單元4 〇的l B A位址的最大値X、與 第3記憶體單元5〇的lb A位址的最大値Y的和（W + X + Y )以下（步驟S90 )。若LBA位址η爲上述和（W + X + Y )以下（步驟S90 : Yes )、則藉由位址變換電路92來將 變換後的L B A位址m設爲從l B A位址η扣除W及X的 値（步驟S1 〇〇 )。然後，此情況，單元選擇器94是選擇 第3記憶體單元5 〇作爲指令的轉送目的地（步驟S i丨〇 ) ο 在上述步驟S90中，當判斷LBA位址η非爲上述和 (W + X + Y )以下時（步驟S90 : No )，位址解碼器90會 判斷LB A位址n是否爲第1記憶體單元3 0的LB A位址的 最大値W、第2記憶體單元40的LBA位址的最大値X、 第3記憶體單元5 0的LB A位址的最大値Y、與第4記憶 體單元60的最大値Z的和（W + X + Y + Z)以下（步驟S120 )。若LBA位址η爲上述和（W + X + Y + Z )以下（步驟 S1 20 : Yes )，則藉由位址變換電路92來將變換後的LB A 位址m設爲從LBA位址η扣除W、X及Y的値（步驟 S 1 3 0 )。然後，此情況，單元選擇器94是選擇第4記憶 -20- 200903493 體單元6 0作爲指令的轉送目的地（步驟S 1 4 0 )。 在上述步驟S 1 20中，當判斷LBA位址η非爲上述和 (W + X + Y + Z)以下時（步驟S120: No),超過結合領域 UA的LBA位址會被指定。因此，此情況，特定的錯誤處 理會被執行（步驟S 1 5 0 )。所謂特定的錯誤處理是例如 放棄現在輸入的指令等的處理。若根據以上説明的單元管 理處理，則只要單純的比較運算，便可容易地進行位址的 變換與記憶體單元的選擇。 以上，說明有關本實施例的記憶裝置1 0的構成及動 作。如上述’本實施例的記億裝置1 0是以能夠在結合領 域UA的開頭分配SLC型的快閃記憶體亦即二値記憶體3 } 之方式來進行位址變換。因此，一旦記憶裝置1 0根據 FAT16或FAT32等的檔案系統來格式化，則資料的管理資 訊亦即檔案分配表（以下稱爲「F AT資訊」）會被生成於 二値記憶體3 1内。FAT資訊是一旦進行資料的寫入或消 去則會被頻繁地重寫之管理資訊。本實施例是在寫入如此 的管理資訊之領域中配置比MLC型的快閃記憶體（多値 記憶體4 1〜6 1 )更快寫入速度的S LC型的快閃記憶體。 因此，若根據本實施例，則可一面藉由採用MLC型的快 閃記憶體來實現大容量化，一面相較於僅以MLC型的快 閃記憶體來構成的記憶裝置，可使資料的寫入速度更爲提 升。若在MLC型的快閃記億體寫入FAT資訊的時間爲 600nSeC ’則在SLC型的快閃記憶體寫入FAT資訊的時間 大槪爲200nsec。 -21 - 200903493 在此，顯示寫入速度的比較例。如習知，FATl 6或 FAT 3 2是在管理資訊内寫入2個同一内容的FAT資訊。如 此一來，若爲僅以MLC型的快閃記憶體來構成的記憶裝 置，則第1個FAT資訊的重寫需要60〇nsec，第2個FAT 資訊的重寫需要600nsec，且資料的重寫需要600nsec。如 此一來，全體須花費1 8 00nsec的時間。相對的，本實施 例是在寫入FAT資訊的領域使用SLC型的快閃記憶體， 因此第1個FAT資訊的重寫需要200nsec，第2個FAT資 訊的重寫需要20〇nSec，（多値記憶體内的）資料的重寫 需要600nsec。如此一來，全體以l〇〇〇nsec來完成資料的 重寫。亦即，若根據此例，則對於僅以MLC型的快閃記 憶體來構成的記憶裝置而言，可將資料的重寫時間削減 45%程度。 又，一般SLC型的快閃記憶體，相較於MLC型的快 閃記憶體，資料的重寫可能次數多1 0〜2 0倍程度。因此 ’如本實施例那樣，藉由在寫入頻繁被重寫的管理資訊的 領域中配置S L C型的快閃記憶體，可大幅度使資料記憶的 可靠度提升。其結果，並非只作爲外部記憶裝置，與以往 的硬碟同樣，可容易作爲操作系統的啓動用驅動器（boot drive)利用。 又，本實施例中，控制二値記憶體或多値記憶體的單 元控制器爲使用CF卡用的控制器。一般，CF卡是泛用性 高’且可控制各種特性的快閃記憶體。因此，如本實施例 那樣’若在各記憶體單元具備CF卡控制器，則即使採用 -22- 200903493 各記憶體單元不同製造商的快閃記憶體，還是可吸收特性 的不同，使正常動作。其結果，可容易構成混載二値記憶 體或多値記憶體的記憶裝置。另外，在本實施例中雖是採 用CF卡用的控制器作爲單元控制器，但亦可使用SD記 憶體用的控制器、或多媒體卡用的控制器。 在本實施例中，主控制器20所具有的機能爲硬體的 構成。相對的，亦可將主控制器20設爲內藏CPU、ROM 及RAM的微電腦構成，藉此以軟體實現上述位址變換或 單元管理的機能。並且，主控制器20可採用RAID晶片 ，使在該RAID晶片產生動作，藉此控制各記憶體單元。 又，本實施例中是合計具備4個記憶體單元，但並非 限於此數。最低限度，只要具備二値記憶體的記憶體單元 有1個、及具備多値記憶體的記憶體單元有1個即可。 又，本實施例中是將二値記憶體的容量設爲1 G位元 組，但此容量可如其次般決定。例如，記憶裝置1 0是以 FAT32來格式化，記憶裝置1 0的全體記憶容量爲X十億 位元組（gigabyte )。就FAT32而言，大多是每1扇區 爲4K位元組的容量，因此全體爲（X/4 )百萬個的扇區數 。並且，FAT32爲了表現1個位址’而需要4位元組的資 料量。因此’每1個的F A T資訊，需要X百萬位元組（ megabyte ) ( =4位元組* ( x/4 )百萬個）的容量。如上 述，FAT32大多是被寫入2個FAT資訊，因此合計需要（ 2 * X )百萬位元組的管理領域。另外，管理資訊並非僅 FAT資訊’主開機記錄或目錄登錄等的資訊也會被記錄， -23- 200903493 因此全體需要更多的管理領域。在此舉一具體例，亦即若 記億裝置10的全體容量爲128十億位元組（gigabyte ), 則根據上述算出方法’ FAT資訊所必要的容量是形成256 百萬位兀組（megabyte )。又’若加上用以記錄主開機記 錄（master boot record)或目錄登錄（Directory Entry) 等的領域’則全體需要5 0 0百萬位元組程度容量的二値記 憶體。亦即’對於記憶裝置1 0的全體領域（結合領域UA )而言’至少需要0.5%的二値記憶體的容量，若有1%程 度的容量’則可充裕記憶管理資訊。當然，二値記憶體在 動作速度或可靠度上，具有比多値記憶體更佳的特性，因 此超過1 %的容量也無妨。 B .第2實施例： 圖5是表示作爲本發明的第2實施例之記憶裝置的槪 略構成的説明圖。如圖示，本實施例的記憶裝置1 1 0是具 備主控制器20、搭載二値記憶體3 1的第1記憶體單元3〇 、搭載多値記憶體41的第2記憶體單元40。主控制器2〇 是與第1實施例同樣，具備匯流排變換電路2 1及單元管 理電路122。其中，本實施例的單元管理電路122是具有 按照由主裝置8 0所指定的位址或資料、指令，在第1記 憶體單元3 0與第2記憶體單元40之間切換進行資料的讀 寫之對象的機能。 圖6是表示藉由單元管理電路122來進行的記憶體_ 元的切換控制的槪念説明圖。在圖6中’由左側依序顯示 -24- 200903493 從主裝置8 0來看記億裝置1 1 0時之記憶裝置u 〇的全體 記憶領域U A 2、第1記憶體單元3 0的記憶領域、及第2 記憶體單元40的記憶領域。 在本實施例中，第1記憶體單元3 0内的記億領域是 以「0」〜「W」的LB A位址來表示。另一方面，第2記 憶體單元4 0内的記憶領域是以「0」〜「X」的L B A位址 來表示。LBA位址「X」是比LBA位址「W」更大的値。 在本實施例中，一旦由主裝置80指定「0」〜「W」 的LB A位址，則單元管理電路〗22會將資料的讀寫對象 切換成搭載二値記憶體3 1的第1記憶體單元3 0。相對的 ，若超適「W」的LB A位址被指定，則單元管理電路1 22 會將資料的讀寫對象切換成搭載多値記憶體41的第2記 憶體單元40。亦即，在本實施例中，單元管理電路122是 將由主裝置80所指定的LB A位址與臨界値「W」作比較 ，藉此來切換所使用的記憶體單元。另外，進行上述那樣 的切換控制的結果，本實施例會在第2記憶體單元40的 一部份產生未被使用的領域（LBA位址「〇」〜「W」） 〇 圖7是表示單元管理電路122的内部構成的模式方塊 圖。如圖示，本實施例的單元管理電路122是具備暫存器 判別電路1 78、切換控制電路1 94、第1開關電路1 96、及 第2開關電路198。 暫存器判別電路1 78是被連接至圖5所示的匯流排變 換電路2 1。暫存器判別電路1 7 8是與第1實施例同樣，按 -25- 200903493 照從匯流排變換電路2 1輸入的位址信號AO〜A2的狀 ，根據ΑΤΑ規格，判別存取對象的暫存器的種類。然 ，按照判別後的暫存器的種類，將自匯流排變換電路 接受的存取信號轉送至切換控制電路194。 切換控制電路1 9 4是根據暫存器判別電路1 7 8所判 後的存取對象的暫存器的種類、或由主裝置8 0所指定 位址、資料、指令，來進行將存取對象的記憶體單元切 於第1記憶體單元3 0與第2記憶體單元40之間的控制 第1開關電路1 9 6是根據來自切換控制電路1 94的 示，開閉匯流排變換電路2 1與第1記憶體單元3 0間的 接。 第2開關電路1 9 8是根據來自切換控制電路1 94的 示，開閉匯流排變換電路2 1與第2記憶體單元40間的 接。 如圖不，切換控制電路194是具備位址解碼器190 位址比較電路1 92、大小暫存器（Size Register ) 1 79及 令解碼器1 9 1。 位址解碼器1 9 0是根據對裝置/磁頭暫存器、磁柱 位暫存器、磁柱低位暫存器、扇區號碼暫存器的存取信 來解析主裝置8 0所指定的LB A位址。並且，指令解碼 191是進行由主裝置80所指不的指令的解析。 在大小暫存器1 7 9中記憶有根據第1記憶體單元 的最大容量所定的臨界値。在本實施例中，第1記憶體 元3 0的最大容量是5 1 2 Μ位元組（b y t e )，記憶於大小 態 後 2 1 別 的 換 〇 指 連 指 連 指 尚 號 器 30 單 暫 -26- 200903493 存器179的臨界値是表示比該最大容量少 元組的容量之LBA位址。因爲有時會在 生缺陷區塊（壞區塊），所以有時無法利, 的全部。當然，臨界値可使表示第1記憶 大容量之LBA位址原封不動記憶。另外， 可用LBA方式的2進數來表示「 0000000011110000000000000000J 〇 因此 爲480M位元組，則由主裝置80所指定 LBA位址中，可按照上位8位元的値是否 」以上來判斷所被指定的位址是否超過臨 元組）。亦即，後述的位址比較電路1 9 2 的裝置/磁頭暫存器、及8位元的磁柱高位 位元，便可不使用磁柱低位暫存器或扇區 ’來容易進行是否超過臨界値的判斷。 位址比較電路1 92是在於比較位址解u 後的LBA位址與記憶於大小暫存器1 79的 所示，在第1記憶體單元3 0與第2記憶儀 擇存取對象的候補之記憶體單元。 圖8是表示藉由切換控制電路1 94來 的詳細説明圖。圖中「切換」是意指對於 路1 92所選擇的記憶體單元進行存取。相 取」是與藉由位址比較電路1 92的選擇無 憶體單元3 0及第2記憶體單元40的兩者 若干的4 8 0 Μ位 快閃記憶體中產 用 5 1 2 Μ位元組 體單元3 0的最 4 8 0 Μ位元組， ，若將臨界値設 的2 8位元長的 形成「 00000000 界値（4 8 0 Μ位 只要使用4位元 暫存器的上位4 號碼暫存器的値 碼器1 9 0所解析 臨界値，如圖6 !單元40之間選 進行的切換動作 藉由位址比較電 對的，「同時存 關，對於第1記 進行同一的存取 -27- 200903493 又，圖8中所示「寫入時」是表示從主裝置80發行 寫入指令的狀況。寫入指令是包含：對指令暫存器之指令 的寫入命令、對資料暫存器之資料的寫入命令、及對其他 暫存器之LBA位址等的各種參數的寫入命令。又，「讀 出時」是表示從主裝置80發行讀出指令的狀況。讀出指 令是包含從記憶體單元讀出各種的狀態或資料的命令。 如圖8所示，對資料暫存器及指令暫存器的存取，原 則上寫入時、讀出時皆是對藉由位址比較電路1 92所選擇 的記憶體單元進行。相對的，對其他暫存器的存取則是只 在讀出時對所選擇的記憶體單元進行，在寫入時對2個的 記億體單元進行同一存取。資料暫存器及指令暫存器以外 的暫存器，主要是用以指定位址的暫存器。因此，只要寫 入對象的資料或指令適當地對所選擇的記憶體單元轉送， 即使在寫入時，對第1記憶體單元3 0及第2記憶體單元 4 0兩者的暫存器寫入同一位址，照樣不會有特別的障礙。 另外’圖8中所示「例外1」是藉由指令解碼器1 9 1 來進行指令的解析之結果，從主裝置8 0轉送的指令爲切 換空轉（idle )指令或待命（standby )指令等之記憶體單 元全體的動作狀態的指令時。當如此的指令被轉送時，切 換控制電路1 94會例外地對第1記憶體單元3 0及第2記 憶體單元4 0兩者進行該指令的轉送。 又’圖8中所示「例外2」是根據識別裝置指令等來 進行記憶裝置1 1 0的資料容量（全扇區數）的讀出時。在 如此的情況中，切換控制電路1 94會例外地對第2記憶體 -28- 200903493 單元40進行存取。如圖6所示，因爲在本實施例中記憶 裝置1 1 〇的資料容量是與第2記憶體單元4〇的資料容量 一致。 若根據以上說明有關作爲第2實施例的記憶裝置1 1 〇 的構成及動作之本實施例的記憶裝置1 1 0，則與H 1胃施 例的gB憶裝置1 〇问樣’可在記憶領域的開頭的領域分配 SLC型的快閃記億體，在除此以外的領域分配MLC型的 快閃記憶體。因此，對於重寫可能次數多，動作高速的 SLC型的快閃記憶體而言，可使頻繁地被重寫的FAT資訊 記億。其結果’與第1實施例同樣，一面藉由採用MLC 型的快閃記憶體來實現大容量化，一面相較於僅以MLC 型的快閃記億體來構成的記憶裝置，可使資料的寫入速度 及資料記憶的可靠度更爲提升。 又，若根據本實施例的記憶裝置1 1 〇，則可原封不動 使用由主裝置8 0所指定的位址，對2種類的記憶體單元 進行資料的讀寫。其結果，不需要進行複雜的位址變換之 電路，因此可縮小主控制器20的電路規模。其結果，可 謀求製造成本的低減。 以上說明有關本發明的各種實施例，但本發明並非限 於該等的實施例，只要不脫離其主旨範圍，當然亦可採用 各種的構成。例如，上述實施例是採用USB介面作爲連 接記憶裝置與主裝置的介面，但介面的種類並非限於此。 亦可採用IEEE1394介面、串列ΑΤΑ介面、並列ΑΤΑ介 面等各種的介面。 -29- 200903493 【圖式簡單說明】 圖1是表不作爲第1實施例的記憶裝置的槪略構成説 明圖。 圖2是表示藉由第丨實施例的單元管理電路來進行的 位址變換的槪念説明圖。 圖3是表示第1實施例的單元管理電路的内部構成的 模式方塊圖。 圖4是表示第丨實施例的單元管理處理的流程圖. 圖5是表示作爲第2實施例的記憶裝置的槪略構成説 明圖。 圖6是表示藉由第2實施例的單元管理電路來進行的 Μ己憶體單元的切換控制的槪念説明圖。 圖7是表示第2實施例的單元管理電路的内部構成的 模式方塊圖。 圖8是表示藉由第2實施例的切換控制電路來進行的 切換動作的詳細説明圖。 【主要元件符號說明】 1 〇 :記憶裝置 2 0 :主控制器 21 :匯流排變換電路 2 2 :單元管理電路 :第1單元 -30- 200903493 3 1 :二値記憶體 3 2 :第1單元控制器（S LC控制器） 40 :第2單元 41，5 1，61 :多値記憶體 42 :第2單元控制器（MLC控制器） 50 :第3單元 60 :第4單元 7 〇〜7 4 :閂鎖電路 78 :暫存器判別電路 79 :狀態記憶電路 80 :主裝置 90 :位址解碼器 9 1 :指令解碼器 92 :位址變換電路 94 :單元選擇器 9 6 :第1開關電路 9 8 :第2開關電路 1 1 〇 :記憶裝置 1 2 2 :單元管理電路 178 :暫存器判別電路 179 :大小暫存器 1 9 0 :位址解碼器 1 9 1 :指令解碼器 1 9 2 :位址比較電路 -31 - 200903493 194 :切換控制電路 1 9 6 :第1開關電路 1 9 8 :第2開關電路 -32-Register ) , (6) sector number temporary storage, (7) instruction register, (8) data register. The unit controllers 32 to 62 control the reading and writing of data to the binary memory or the plurality of memories in accordance with various parameters set in the registers. The master device 80 transmits an access signal to the registers to the memory device 1 when reading and writing data. When the unit management circuit 22 receives the above-described access signal from the host device 80 via the USB interface and the busbar conversion circuit 21, the cell management circuit 22 can make each of the cells in accordance with the type of the register to be accessed. The transfer method of the access signals of 30 to 60 is changed. The unit management circuit 22 includes a register discriminating circuit 78 for discriminating the type of the register to be accessed. The register discriminating circuit 7 8 determines the type of the register to access the object based on the A T A specification in accordance with the state of the address signals A 0 to A 2 input from the bus bar converting circuit 2 1 . The register discriminating circuit 78 is, for example, 13-200903493 as shown in the figure. If the address signal A 2 is "0", the address signal A1 is "〇", and the address signal Α 0 is "1", the input can be discriminated. The access signal to the feature register 〇 unit management circuit 22 is related to the access signal to the feature register and the sector count register from the host device 80, and the entire memory is intact. Units 30-60 transmit this access signal. Because these registers are not intended to directly specify the location within the UA. Specifically, the feature register is a temporary register used to specify various parameters according to a command, and the sector count register is used to specify the number of sectors when consecutively accessing a plurality of sectors. Register. The "starting sector" for continuous access is specified by the device/head register, the magnetic column upper register, the magnetic column lower register, and the sector number register which will be described later. The device/head register, the magnetic column high register, the magnetic low register, and the sector number register are registers used to specify the location (sector) in the field UA. A portion of the LBA address indicating the sector within the combined domain UA is input to each of the registers. Specifically, if the right LBA address is 28 bits long, the sector number is temporarily stored in the bit column of the seventh bit to the seventh bit, and the eighth column is input in the magnetic column low register. The bit column of the bit ~ the 15th bit. Further, the bit column of the 16th to 23rd bits is input to the magnetic column high register, and the bit column of the 24th to 27th bits is input to the device/head register. If the unit management circuit 22 receives an access signal to the register, it will be locked by the lock circuit 7 0~7 3 once. The access signals latched to the latch circuits 70 to 73 are input to the bit decoder -14-200903493 address decoder 90. The address decoder 90 is provided with a function of recovering the L B A address of the 28-bit long by combining the L B A address stored in the respective latch circuits 7 0 to 7 3 . Further, the address decoder 90 has a function of comparing the restored LB A address with the maximum number of sectors of each memory unit. The details of this function will be described later. The instruction register is a register for specifying various instructions according to the specification. For such an instruction, for example, there is a read sector command for reading data from a designated sector, and a write sector command for writing data to a designated sector. Once the unit management circuit 22 accepts the command signal to the instruction register, the signal is input to the instruction decoder 9 1 and the latch circuit 74. When the command decoder 9 1 inputs the command signal, the type of the input command is discriminated, and the result of the discrimination is output to the address conversion circuit 92 and the unit selector 94. The command signal input to the latch circuit 74 is held by the latch circuit 74 until an output instruction from the unit selector 94 is reached. As shown in Fig. 2, the address conversion circuit 92' has a function of converting the L Β Α address of the combination field 输入 输入 input from the address decoder 90 into the LBA address of each of the memory units 30 to 60. Specifically, the address conversion circuit 92 inputs the LBA address from the address decoder 90, and inputs the type of the instruction from the instruction decoder 91. Then 'determine whether the input instruction type is an instruction requiring an LBA address. The instruction that requires the LBA address is generally a designated address (sector), and the access to the specified address is, for example, "read sector instruction", "write sector instruction", "Read Multiplex Command", "Write Multiplex Command", "Read DMA Command", "Write DMA Command", "Read Confirmation (200903493 verify) Sector Command" "seek" Instructions, etc. If the address conversion circuit 92 determines that the input instruction type is an instruction requiring the l BA address, the LBA address input from the address decoder 90 is converted into the LBA address of each memory unit (related conversion method) As will be described later, the converted LBA address is transferred to all of the memory cells 30 to 60. As will be described later, the main controller 20 does not simultaneously transfer a command requiring an LBA address to a plurality of memory cells, so that the converted LBA address can be transferred to all of the memory cells 30 to 60. In this way, the address conversion circuit 92 can omit the process of selecting the transfer destination. Of course, only the converted memory unit can be forwarded to the converted LBA address. If the command type input from the command decoder 9 1 is an instruction that does not require an LB address, the address conversion circuit 92 transfers the parameters input from the address decoder 90 to all the memory units 3 0~ 60. Since the access signal to the device/head register or the like is not limited to the LBA address when the instruction of the LBA address is not required. The instruction that does not require the LBA address is an instruction to perform any operation on the flash memory without specifying the address (sector), for example, "identification device command", "set feature command", "check power" Mode command", "quiet command", "standby command", "idle command", etc. Further, the address conversion circuit 92 transmits the conversion to the memory cells 30 to 60 in the same manner as the instruction requiring the LBA address, even if the instruction type input from the command decoder 9 1 is an instruction that does not require the LBA address. After the LB A address. Because the instruction that does not require the LBA address is an instruction that is executed regardless of the presence or absence of the LBA address. Of course, the transmission is performed until the conversion, but the configuration of the converted L B A address may be sent without transmission -16-200903493. The unit selector 94 is a circuit for selecting a memory unit of a transfer destination of the command based on the address input from the address decoder 90. In other words, the unit selector 94 inputs LB A from the address decoder 90 and inputs the type of the instruction from the instruction decoder 91. Then, it is judged whether the type of the instruction is an instruction requiring an LBA address. In the case of an instruction requiring a bit address, the unit selector 94 performs processing of the memory unit of the transfer destination of the selection command based on the input LBA bit. The details will be described later. When the unit selector 94 selects the memory unit of the ground, the first switch circuit 96, the memory unit of the transfer destination, and the latch circuit 74 are controlled. As a result, the command signal held in the latch circuit 74 is transmitted to the selected body unit. The command signal held by the latch circuit 74 is output to each unit sequence, and the LBA address set to the address conversion is transmitted from the address conversion 92 to each memory unit, and the switch is completed according to the unit selector 94. The timing after the switching of circuit 96. Since the ΑΤΑ specification is to transfer instructions that require an L Β Α address, the l Β 必须 must be pre-defined in the scratchpad. Further, if the type of input is that the LB a bit command is not required, the unit selector 94 controls the first switch circuit 96, and the lock circuit 74 can be connected to all of the cells. In this way, the instruction that does not require the LBA address can be transferred to all memory units. When the type of instruction input is an instruction that does not require an LBA address, the flash lock circuit 74 may not delay the output of the instruction. The LBA specific address is input to the LB A address to process the destination connection, and the latched circuit is set to address the latch of the address, when it is in progress, -17-200903493 if the unit selector 94 is based on the input Lba address In order to control the first switching circuit 9 6 ', the same as the 'second switching circuit 98' is also controlled. The second switch circuit 9.8 is a switch for switching an access signal to the data register. Once the second switch circuit 9 8 is switched in accordance with the unit selector 94, the data signal is also transferred to the same memory unit as the memory unit to which the instruction requiring the LBA address is transferred. A state memory circuit 79 is connected between the second switching circuit 98 and the register determining circuit 78. The state memory circuit 79 stores the capacity (the total number of sectors) of the entire area UA or the device ID indicating the manufacturer information of the memory device 10. Normally, when the master device 8 requests the status information, the status information is returned from the memory unit selected by the second switch circuit 98. However, for example, in response to an inquiry by the "identification device" command or the like, or an inquiry of the number of sectors of the device, or the device ID, the status memory circuit 79 returns status information to the host device 80. In the case where the status information can be returned from the state memory circuit 79, the master device 80 can correctly convey the status information about the entire device 100 that cannot be associated with each memory unit. Fig. 4 is a flow chart showing the flow of the address conversion processing by the address decoder 90 and the address conversion circuit 92 and the selection processing of the memory unit by the unit selector 94. Hereinafter, this processing will be referred to as "unit management processing". The address conversion circuit 92 judges whether or not the type of the instruction input from the instruction decoder 9 1 is an instruction requiring the LB A address (step S 1 0 ). As a result, if it is an instruction that does not require the LB A address (step S 1 0 : No ), the address -18 - 200903493 conversion circuit 92 does not perform address conversion 'to all the units to transfer the input to the device head as it is. Parameters such as the scratchpad. On the other hand, the unit selector 94 selects all the memory units (step S20)' to end the processing. In this way, the same instruction is transferred to all the memory units. Further, as described above, in step S10, even if it is determined that an instruction that does not require an LBA address is input, the address conversion circuit 92 can perform the following address conversion as in the case of an instruction requiring an LBA address. In the above step S10, if the input command is an instruction requiring an LBA address (step S1 0 : Yes ), the address decoder 90 determines that the input LBA address η is the LBA of the first memory unit 30. The maximum 値W (refer to FIG. 2) of the address is below (step S30). If the LBA address n is the maximum 値W or less (step S3 0 : Yes ), the converted LBA address m is set to the original LBA bit input from the address decoder 90 by the address conversion circuit 92. Address η (step S40). Then, in this case, the unit selector 94 selects the first memory unit 30 as the transfer destination of the command (step S50). In the above step S30, when it is judged that the L Β Α address η is not the maximum 値W of the LB Α address of the first octet unit 30 (step s 3 0 : No), the address decoder 90 will determine whether the L Β A address η is the sum of the maximum 値W of the LBA address of the first memory unit 30 and the maximum 値X of the LBA address of the second memory unit 4 (W + X ). (Step S60). If the LBA address η is equal to or less than the above sum (W + X) (step S60: Yes), the transformed l β A address m is set to be deducted from the L Β A address η by the address conversion circuit 92. The brother 1 remembers the body 兀 30 l Β A address of the largest -19- 200903493 値 w (step S70). Then, in this case, the unit selector 94 selects the second memory unit 4 as the transfer destination of the command (step S80). In the above step S60, when it is judged that the LBA address η is not the above sum (W + X) In the following (step S60: No), the address decoder 90 determines whether the LBA address n is the maximum 値W of the LBA address of the first memory unit 30 and the l BA bit of the second memory unit 4 〇 The maximum 値X of the address is equal to or less than the sum (W + X + Y ) of the maximum 値Y of the lb A address of the third memory unit 5 (step S90). If the LBA address η is equal to or lower than the sum (W + X + Y ) (step S90: Yes), the converted LBA address m is set to be deducted from the l BA address η by the address conversion circuit 92. And the X of X (step S1 〇〇). Then, in this case, the unit selector 94 selects the third memory unit 5 as the transfer destination of the command (step S i ). In the above step S90, when it is judged that the LBA address η is not the above sum (W) + X + Y ) In the following (step S90: No), the address decoder 90 determines whether the LB A address n is the maximum 値W and the second memory unit of the LB A address of the first memory unit 30. The maximum 値X of the LBA address of 40, the maximum 値Y of the LB A address of the third memory unit 50, and the sum of the maximum 値Z of the fourth memory unit 60 (W + X + Y + Z) (Step S120). If the LBA address η is equal to or less than (W + X + Y + Z ) (step S1 20 : Yes ), the converted LB A address m is set to the slave LBA address by the address conversion circuit 92. η deducts 値 of W, X, and Y (step S 1 3 0 ). Then, in this case, the unit selector 94 selects the fourth memory -20-200903493 body unit 60 as the transfer destination of the command (step S 1 4 0 ). In the above step S120, when it is judged that the LBA address η is not equal to or lower than the above sum (W + X + Y + Z) (step S120: No), the LBA address exceeding the combined domain UA is specified. Therefore, in this case, a specific error handling is performed (step S1 5 0 ). The specific error processing is, for example, a process of giving up an instruction currently input or the like. According to the unit management processing described above, the address conversion and the selection of the memory unit can be easily performed by a simple comparison operation. The configuration and operation of the memory device 10 of the present embodiment will be described above. The above-described "the device 100 of the present embodiment performs address conversion so that the SLC type flash memory, that is, the binary memory 3} can be allocated at the beginning of the binding area UA. Therefore, once the memory device 10 is formatted according to a file system such as FAT16 or FAT32, the management information of the data, that is, the file allocation table (hereinafter referred to as "F AT information") is generated in the memory 3 1 . . FAT information is management information that is frequently rewritten once data is written or erased. This embodiment is an S LC type flash memory in which a writing speed faster than that of an MLC type flash memory (multiple memories 4 1 to 6 1 ) is set in the field of writing such management information. Therefore, according to the present embodiment, it is possible to realize a large capacity by using an MLC type flash memory, and a data storage device can be realized as compared with a memory device constructed only by an MLC type flash memory. The write speed is even higher. If the time for writing the FAT information in the MLC type flash memory is 600nSeC', the time for writing the FAT information in the SLC type flash memory is 200nsec. -21 - 200903493 Here, a comparison example of the write speed is displayed. As is conventional, FAT16 or FAT 3 2 is a FAT message in which two identical contents are written in the management information. In this way, if the memory device is configured only by the MLC type flash memory, the rewriting of the first FAT information requires 60 〇 nsec, the rewriting of the second FAT information requires 600 nsec, and the weight of the data is heavy. Writing requires 600nsec. As a result, it takes a total of 1 800 sec. In contrast, in this embodiment, the SLC type flash memory is used in the field of writing FAT information, so the rewriting of the first FAT information requires 200 nsec, and the rewriting of the second FAT information requires 20 〇 nSec, (multiple Rewriting of data in memory is 600nsec. In this way, the entire data is rewritten by l〇〇〇nsec. That is, according to this example, for a memory device constructed only of an MLC type flash memory, the data rewriting time can be reduced by about 45%. Moreover, in general, the flash memory of the SLC type is more than 10 to 20 times more rewritten than the MLC type flash memory. Therefore, as in the present embodiment, by arranging the S L C type flash memory in the field of writing management information that is frequently rewritten, the reliability of data memory can be greatly improved. As a result, it is not only used as an external memory device, but can be easily used as a boot drive for an operating system, similarly to a conventional hard disk. Further, in the present embodiment, the unit controller for controlling the binary memory or the multi-turn memory is a controller for using the CF card. In general, a CF card is a flash memory that is highly versatile and can control various characteristics. Therefore, if the CF card controller is provided in each memory unit as in the present embodiment, even if the flash memory of the manufacturer of each memory unit of -22-200903493 is used, the absorption characteristics are different, so that the normal operation is performed. . As a result, it is easy to constitute a memory device in which two or more memories are mixed. Further, in the present embodiment, a controller for a CF card is used as the unit controller, but a controller for the SD memory or a controller for the multimedia card may be used. In the present embodiment, the main controller 20 has a function of a hardware. On the other hand, the main controller 20 can be configured as a microcomputer including a CPU, a ROM, and a RAM, thereby realizing the above-described function of address conversion or unit management in software. Further, the main controller 20 can employ a RAID chip to cause an operation on the RAID wafer, thereby controlling each of the memory cells. Further, in the present embodiment, a total of four memory cells are provided, but the number is not limited thereto. At the very least, there is one memory unit having two memory and one memory unit having multiple memory. Further, in the present embodiment, the capacity of the binary memory is set to 1 Gbyte, but this capacity can be determined as follows. For example, the memory device 10 is formatted by FAT32, and the total memory capacity of the memory device 10 is X gigabytes. As far as FAT32 is concerned, it is a capacity of 4K bytes per sector, and therefore the total number of sectors is (X/4) million. Also, FAT32 requires a 4-bit data amount in order to represent one address'. Therefore, the capacity of X megabytes (=4 bytes* (x/4) million) is required for every F A T information. As mentioned above, FAT32 is mostly written with two FAT information, so the total management area of (2 * X) megabytes is required. In addition, management information is not only FAT information, such as the main boot record or directory login information will be recorded, -23- 200903493 Therefore all need more management areas. In a specific example, if the total capacity of the device 100 is 100 gigabytes, the capacity required for the FAT information according to the above calculation method is 256 million megabytes (megabyte). ). In addition, if a field for recording a master boot record or a directory entry is added, a total of 500 megabytes of capacity is required. That is, 'at least 0.5% of the capacity of the binary memory is required for the entire field of the memory device 10 (in combination with the field UA), and if there is a capacity of 1%, the memory management information can be sufficient. Of course, the second memory has better characteristics than the multi-turn memory in terms of speed or reliability, so it is no problem to exceed 1% of the capacity. B. Second Embodiment FIG. 5 is an explanatory view showing a schematic configuration of a memory device according to a second embodiment of the present invention. As shown in the figure, the memory device 110 of the present embodiment is a second memory unit 40 having a main controller 20, a first memory unit 3A on which the binary memory 3 1 is mounted, and a multi-turn memory 41. The main controller 2A includes a bus bar conversion circuit 21 and a cell management circuit 122 as in the first embodiment. In the unit management circuit 122 of the present embodiment, the data is read between the first memory unit 30 and the second memory unit 40 in accordance with the address, data, and command designated by the host device 80. The function of the object being written. FIG. 6 is a conceptual explanatory view showing switching control of the memory cell by the cell management circuit 122. In Fig. 6, 'the left side is sequentially displayed -24-200903493. From the main device 80, the memory area u of the memory device u 〇 is seen from the main device 80. The memory area of the UA 2, the first memory unit 30 And the memory area of the second memory unit 40. In the present embodiment, the area of the billion in the first memory unit 30 is represented by the LB A address of "0" to "W". On the other hand, the memory area in the second memory unit 40 is represented by the L B A address of "0" to "X". The LBA address "X" is a larger number than the LBA address "W". In the present embodiment, when the LB A address of "0" to "W" is designated by the host device 80, the unit management circuit 222 switches the read/write target of the data to the first of the second memory 3 1 . Memory unit 30. On the other hand, if the LB A address of the "W" is specified, the unit management circuit 1 22 switches the read/write target of the data to the second memory unit 40 in which the plurality of memories 41 are mounted. That is, in the present embodiment, the unit management circuit 122 compares the LB A address specified by the host device 80 with the threshold 値 "W", thereby switching the used memory unit. Further, as a result of the above-described switching control, in this embodiment, an unused area (LBA address "〇" to "W") is generated in a part of the second memory unit 40. FIG. 7 shows unit management. A schematic block diagram of the internal structure of circuit 122. As shown, the unit management circuit 122 of the present embodiment includes a register discriminating circuit 1 78, a switching control circuit 94, a first switching circuit 196, and a second switching circuit 198. The register discriminating circuit 1 78 is connected to the bus bar converting circuit 21 shown in Fig. 5 . In the same manner as in the first embodiment, the register discriminating circuit 1 7 8 is in the form of the address signals AO to A2 input from the busbar converting circuit 2 1 in the range of -25 to 200903493, and the temporary access target is determined based on the ΑΤΑ specification. The type of storage. However, the access signal received from the busbar conversion circuit is transferred to the switching control circuit 194 in accordance with the type of the identified register. The switching control circuit 194 is to access according to the type of the temporary register to be accessed by the register determining circuit 178 or the address, data, and instruction specified by the host device 80. The memory unit of the object is cut between the first memory unit 30 and the second memory unit 40. The first switching circuit 1 6 6 opens and closes the bus line converting circuit 2 1 based on the indication from the switching control circuit 94. Connected to the first memory unit 30. The second switching circuit 1 9 8 is connected between the open/close bus line converting circuit 21 and the second memory unit 40 in accordance with the switching control circuit 1 94. As shown in the figure, the switching control circuit 194 is provided with an address decoder 190 address comparison circuit 192, a size register (Size Register) 1 79, and a decoder 191. The address decoder 1 90 is configured to parse the master device 80 according to the access information to the device/head register, the magnetic column register, the magnetic column low register, and the sector number register. LB A address. Further, the command decode 191 is to perform analysis of an instruction indicated by the host device 80. A threshold 値 according to the maximum capacity of the first memory unit is stored in the size register 179. In this embodiment, the maximum capacity of the first memory cell 30 is 5 1 2 Μbytes (byte), and after being stored in the size state, the other is replaced by the 连 指 连 连 尚 尚 30 30 30 30 -26- 200903493 The threshold 存 of the 179 is the LBA address indicating the capacity of the tuple less than the maximum capacity. Because it sometimes happens in a defective block (bad block), sometimes it is not profitable. Of course, the critical 値 can make the LBA address representing the first memory large capacity intact. In addition, it can be expressed by the binary number of the LBA method "0000000011110000000000000000J 〇 Therefore, it is 480M bytes, and the LBA address specified by the host device 80 can be judged according to whether or not the upper octet is "above" or more. Whether the address exceeds the Linyuan group). That is, the device/head register of the address comparison circuit 192 described later and the 8-bit magnetic column high-order bit can easily perform the over-limit without using the magnetic column low-order register or sector ' Awkward judgment. The address comparison circuit 1 92 is an LBA address after comparing the address solution u and is stored in the size register 1 79, and is selected in the first memory unit 30 and the second memory device. Memory unit. Fig. 8 is a detailed explanatory diagram showing the switching control circuit 94. "Switching" in the figure means accessing the memory cells selected by the channel 92. "Phase" is a 5 1 2 Μ bit in the 4 0 0 快 flash memory that is selected by the address comparison circuit 1 92 and the second memory unit 30 The most 480-bit byte of the group unit 30, if the critical length of the 28-bit length is formed, the "00000000 boundary" (the 4,800-bit position is as long as the upper 4 of the 4-bit register is used) The value of the identifier of the number register of the number register is as shown in Fig. 6. The switching operation between the units 40 is compared by the address comparison, "at the same time, the same is performed for the first record. Access -27-200903493 In addition, the "writing time" shown in Fig. 8 indicates a state in which a write command is issued from the host device 80. The write command includes a write command to the instruction of the instruction register, and a pair. The write command of the data of the data register and the write command of various parameters such as the LBA address of the other register, and the "reading" means that the read command is issued from the host device 80. The read command is a command that includes reading various states or materials from the memory unit. As shown in FIG. 8, the data is temporarily stored. And the access of the instruction register is, in principle, written and read by the memory unit selected by the address comparison circuit 192. In contrast, access to other registers is The selected memory unit is only read at the time of reading, and the same access is made to the two units of the unit when writing. The data register and the register other than the instruction register are mainly used for The register of the specified address is stored. Therefore, as long as the data or instruction to be written is appropriately transferred to the selected memory unit, even when writing, the first memory unit 30 and the second memory unit 4 are 0 The registers of both registers are written to the same address, and there is no special obstacle. In addition, the "exception 1" shown in Figure 8 is the result of parsing the instruction by the instruction decoder 1 9 1 . The command transferred by the host device 80 is an instruction to switch the operation state of the entire memory unit such as an idle command or a standby command. When such an instruction is transferred, the switching control circuit 94 will be exceptionally The first memory unit 30 and the second memory unit 4 0 The transfer of the command is performed. The "exception 2" shown in Fig. 8 is when the data capacity (the total number of sectors) of the memory device 1 10 is read based on the identification device command or the like. In such a case. The switching control circuit 94 will access the second memory -28-200903493 unit 40 exceptionally. As shown in FIG. 6, since the data capacity of the memory device 1 〇 is the same as the second memory in this embodiment. The data capacity of the unit 4A is the same. According to the memory device 1 10 of the present embodiment which is the configuration and operation of the memory device 1 1 第 of the second embodiment, the gB memory device of the H 1 stomach embodiment is used. In the field of the beginning of the memory field, the SLC type flash memory is allocated, and the MLC type flash memory is allocated in other fields. Therefore, for an SLC type flash memory in which the number of rewrites is large and the operation speed is high, the FAT information that is frequently rewritten can be recorded. As a result, in the same manner as in the first embodiment, the memory can be realized by using the MLC type flash memory, and the data can be made compared to the memory device which is constituted only by the MLC type flash memory. Write speed and data memory reliability are even higher. Further, according to the memory device 1 1 of the present embodiment, the address specified by the host device 80 can be used as it is, and the data can be read and written for the two types of memory cells. As a result, a complicated circuit of the address conversion is not required, so that the circuit scale of the main controller 20 can be reduced. As a result, it is possible to reduce the manufacturing cost. The various embodiments of the present invention have been described above, but the present invention is not limited to the embodiments, and various configurations may be employed without departing from the scope of the invention. For example, the above embodiment uses a USB interface as an interface for connecting the memory device to the host device, but the type of the interface is not limited thereto. Various interfaces such as an IEEE1394 interface, a serial port interface, and a parallel port interface can also be used. -29-200903493 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram showing a schematic configuration of a memory device according to a first embodiment. Fig. 2 is a conceptual explanatory view showing address conversion by the cell management circuit of the second embodiment. Fig. 3 is a schematic block diagram showing the internal configuration of a cell management circuit of the first embodiment. Fig. 4 is a flowchart showing a unit management process of the second embodiment. Fig. 5 is a schematic diagram showing a schematic configuration of a memory device as a second embodiment. Fig. 6 is a view for explaining the switching control of the memory unit by the unit management circuit of the second embodiment. Fig. 7 is a schematic block diagram showing the internal configuration of a cell management circuit of a second embodiment. Fig. 8 is a detailed explanatory diagram showing a switching operation performed by the switching control circuit of the second embodiment. [Description of main component symbols] 1 〇: Memory device 2 0 : Main controller 21 : Bus bar conversion circuit 2 2 : Unit management circuit: Unit 1 - 30 - 200903493 3 1 : Two-dimensional memory 3 2 : Unit 1 Controller (S LC controller) 40: 2nd unit 41, 5 1, 61 : Multi-turn memory 42: 2nd unit controller (MLC controller) 50: 3rd unit 60: 4th unit 7 〇~7 4: Latch circuit 78: register discriminating circuit 79: state memory circuit 80: main device 90: address decoder 9 1 : command decoder 92: address conversion circuit 94: unit selector 9 6 : first switch Circuit 9 8 : 2nd switch circuit 1 1 〇: Memory device 1 2 2 : Unit management circuit 178 : Register discriminating circuit 179 : Size register 1 9 0 : Address decoder 1 9 1 : Command decoder 1 9 2 : Address comparison circuit -31 - 200903493 194 : Switching control circuit 1 9 6 : 1st switching circuit 1 9 8 : 2nd switching circuit -32-