CN103246615B - The method of data management in a kind of flash memory device and device - Google Patents
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Abstract
The present invention is applicable to the technical field of data storage of storer, provide method and the device of data management in a kind of flash memory device, described flash memory device comprises reads cacheable memory region and generic storage region, the described memory capacity reading cacheable memory region is less than the memory capacity in described generic storage region, and described method comprises: judge whether the data in described flash memory device are dsc data; If so, read cacheable memory region described in described data being stored to, otherwise described data are stored to described generic storage region.The present invention by described dsc data is stored to memory capacity less read cacheable memory region, make when reading described dsc data, directly read cacheable memory region from described reading, thus address-time when dsc data reads can be greatly reduced, improve the reading efficiency of dsc data.
Description
Technical field
The invention belongs to the technical field of data storage of storer, particularly relate to method and the device of data management in a kind of flash memory device.
Background technology
Flash storage device, is also flash memory device, is a kind of programmable storage device, has that volume is little, capacity is large, shockproof, energy consumption is low and the feature such as data are not volatile.
In flash memory device, the reading times of some data is relatively more frequent, and such as directory information, log information, learning data etc., need in the possible short time repeatedly to be read, the data that these reading times are greater than preset value are called dsc data by us.Because the capacity of existing flash memory device is all larger, the reading of dsc data each time, all needs to spend many address-time, thus greatly reduces the reading efficiency of dsc data.
Summary of the invention
The object of the embodiment of the present invention is the method providing data management in a kind of flash memory device, to solve the lower problem of existing dsc data reading efficiency.
The embodiment of the present invention realizes like this, the method of data management in a kind of flash memory device, described flash memory device comprises reads cacheable memory region and generic storage region, the described memory capacity reading cacheable memory region is less than the memory capacity in described generic storage region, and described method comprises:
Judge whether the data in described flash memory device are dsc data;
If so, read cacheable memory region described in described data being stored to, otherwise described data are stored to described generic storage region.
Another object of the embodiment of the present invention is the device providing data management in a kind of flash memory device, described flash memory device comprises reads cacheable memory region and generic storage region, the described memory capacity reading cacheable memory region is less than the memory capacity in described generic storage region, and described device comprises:
First judging unit, for judging whether the data in described flash memory device are dsc data;
Storage unit, for when described judging unit judged result is for being, reads cacheable memory region described in described data being stored to, when described judging unit judged result is no, described data being stored to described generic storage region.
An object again of the embodiment of the present invention is to provide a kind of flash memory device, and described flash memory device comprises the device of data management in described flash memory device.
The beneficial effect that the embodiment of the present invention compared with prior art exists is: the embodiment of the present invention by arrange storage area less read cacheable memory region, to be judged to be that the data of dsc data are read in cacheable memory region described in being stored to, make when reading described dsc data, directly read cacheable memory region from described reading, thus the address-time that can greatly reduce when dsc data reads, improve the reading efficiency of dsc data, there is stronger practicality.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the realization flow figure of data managing method in the flash memory device that provides of the embodiment of the present invention one;
Fig. 2 is the composition structural drawing of data administrator in the flash memory device that provides of the embodiment of the present invention two;
Fig. 3 is the composition structural drawing of the flash memory device that the embodiment of the present invention three provides.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
In order to technical solutions according to the invention are described, be described below by specific embodiment.
embodiment one:
Fig. 1 shows the realization flow of data managing method in the flash memory device that the embodiment of the present invention one provides, and details are as follows for the method process:
In step S101, judge whether the data in flash memory device are dsc data, if judged result is "Yes", then perform step S102, if judged result is "No", then perform step S103.
In the present embodiment, divide in flash memory device in advance and one read cacheable memory region and generic storage region, described in read cacheable memory region memory capacity be less than the memory capacity in described generic storage region.Wherein, described in, to read cacheable memory region and generic storage region can be different storage zone that same storer marks off also can be two independently different storage zone of providing of storer, at this not in order to limit the present invention.
Preferably, the storage area that the Hash memory pages reading storage area that cacheable memory region can provide for the least significant bit page of multi-layered unit flash memory storage block in flash memory device and/or single layer cell flash memory storage block described in provides.
In the present embodiment, because the digital independent of the least significant bit page of multi-layered unit flash memory storage block in flash memory device and the Hash memory pages of single layer cell flash memory storage block and write time are much smaller than the digital independent of not least significance bit page and write time, and least significant bit page and single layer cell Hash memory pages are reliable and stable Hash memory pages, therefore in order to improve the efficiency of reading and writing data, strengthen the stability of data, the storage area that the Hash memory pages of the storage area that the least significant bit page of multi-layered unit flash memory storage block in flash memory device provides by the present embodiment and/or single layer cell flash memory storage block provides is divided into reads cacheable memory region.
In step s 102, described data are stored to described in read cacheable memory region.
It should be noted that, described data be dsc data and described data not described read cacheable memory region time, cacheable memory region is read described in then needing described data to be stored to from generic storage region, if described data read cacheable memory region described in being stored in, then transfer is not needed to store.
In step s 103, described data are stored to described generic storage region.
It should be noted that, described data be not dsc data and described data not in described generic storage region time, just described data being stored to described generic storage region from reading cacheable memory region, if these data have been stored in described generic storage region, then not needing transfer to store.
Further, if when in generic storage region, the read-write number of times of certain data is greater than preset value, the present embodiment also comprises:
Read the storage block of cacheable memory region hollow described in acquisition, the data batchmove reading and writing number of times and be greater than preset value is stored to the storage block of described sky in generic storage region.
Further, if described in read not exist in cacheable memory region empty storage block, then judge the read-write number of times of these data in generic storage region is read to read and write the minimum data of number of times in cacheable memory region described in whether being greater than, if, then read in cacheable memory region, to read and write the minimum data batchmove of number of times be stored to generic storage region by described, read described in cacheable memory region, to read and write storage block corresponding to the minimum data of number of times described in this data batchmove in generic storage region is stored to.
Wherein, the storage block of described sky is the storage block not writing data.
Further, before judging whether the data in described flash memory device are dsc data, the present embodiment also comprises:
Create address field tables of data and weighted data table, described address field tables of data is for recording the logical address section depositing dsc data, and described weighted data table is for recording the weighted value of each described logical address section correspondence.
Wherein, described logical address section can be logical sector address, also can be logical page address or LBA (Logical Block Addressing), at this not in order to limit the present invention.The size of described address field tables of data is that each logical address section of 2nbyte(can with a word record, 1word=2byte); The size of described weighted data table is that a nbyte(byte records the weighted value of logical address section correspondence).Size about n can be determined by following two principles: one is that the differentiation of the cold and hot data of memory device in actual applications does not need to be mapped to whole logical address segment limit, only needs to be mapped to Dynamic System some logical address sections the most frequently; Two is sizes of the memory headroom that storage device controller can provide.Both can ensure to be applicable to each memory device by which, and can ensure again the effect that cold and hot data separation manages to reach practical purpose.Described weighted value is the number of times at every turn reading and writing logical address section, and described in the operational order at every turn receiving a host computer system, weighted value adds 1.
In addition, it should be noted that, re-create in internal memory after described address field tables of data and each electric initialization on a storage device of weighted data table, do not preserve after power-off.Be kept at after can certainly creating in memory device, do not limit at this.
Further, the present embodiment also comprises:
The read operation order of Receiving Host system, carries logical address segment information in described read operation order;
Judge whether the described logical address section of carrying in read operation order has been present in described address field tables of data;
If exist, then determine that the data of this logical address section correspondence are dsc data, read corresponding data cacheable memory region from described reading, and after having read, the weighted value corresponding with this logical address section in described weighted data table is added 1;
If do not exist, then determine that the data of this logical address section correspondence are cold data, corresponding data are read from described generic storage region, and after having read, judge whether described address field tables of data and weighted data table are filled with data, if not, then the described logical address section of carrying in read operation order is updated in described address field tables of data, and in described weighted data table, record the weighted value of this logical address section correspondence, read cacheable memory region described in the data that this logical address section stores being stored to simultaneously, if described address field tables of data and weighted data table are filled with data, then search weighted value minimum in described weighted data table, logical address section corresponding for the described minimum weighted value found is updated to the described logical address section of carrying in read operation order, and described MINIMUM WEIGHT weight values is added 1 or the mean value that described MINIMUM WEIGHT weight values replaced with entitlement weight values in described weighted data table add 1, read cacheable memory region described in the data that the described logical address section of carrying in read operation order stores being stored to simultaneously, the data that the logical address section that described minimum weighted value is corresponding stores are stored to described generic storage region.
In the present embodiment, described host computer system system is any system that can store data, and such as computer system, digital camera, video camera, communicator, reproducing apparatus for phonotape, video signal broadcast the systems such as device.
Namely the described mean value described MINIMUM WEIGHT weight values being replaced with entitlement weight values in described weighted data table add 1(
x
1... x
nweighted value in weighted data table) object be that the weighted value of the dsc data newly added is positioned at more than mean value, have the weighted value that is higher, ensure that the real-time update of cold and hot data.
When there is multiple identical MINIMUM WEIGHT weight values in described weighted data table, then upgrade the logical address section that wherein any one MINIMUM WEIGHT weight values is corresponding.Preferably, logical address section corresponding to the MINIMUM WEIGHT weight values that finds at first is upgraded.
Illustrate said process, for convenience of explanation the present invention, with n=10, and the weighted value that have recorded 9 logical address sections and correspondence thereof is example, as shown in table 1,
Table 1
The address that first time reads is logical address section 12, search rear discovery and be not arranged in address field tables of data, then be judged as cold data, by cold data processing, corresponding data (data that logical address section 12 stores) are read from described generic storage region, and after having read, logical address section 12 is updated to (described address field tables of data and weighted data table are not filled with data) in address field tables of data, and in weighted data table, record the weighted value of its correspondence, the data that logical address section 12 stores are stored into and read memory buffer, because logical address section 12 is read first time, therefore its weighted value is 1, address field tables of data after renewal and weighted data table as shown in table 2:
Table 2
The address that second time reads is logical address section 5, search rear discovery and be arranged in address field tables of data, then be judged as dsc data, by dsc data process, read corresponding data cacheable memory region from described reading, and after having read, the more weighted value of new logical addresses section 5, new weighted value is that former weighted value adds 1, is 5, the address field tables of data after renewal and weighted data table as shown in table 3:
Table 3
The address read for 3rd time is logical address section 15, search rear discovery and be not arranged in address field tables of data, then be judged as cold data, by cold data processing, corresponding data are read from described generic storage region, and after having read, think that logical address section 15 is for dsc data logical address section, but described address field tables of data and weighted data table are filled with data, now need to replace the minimum logical address section of weighted value, the logical address section of searching rear right of discovery weight values minimum is respectively logical address section 2, logical address section 9, logical address section 80, logical address section 12, upgrade and find logical address section 2 at first, by logical address section 15 replacement logic address field 2, and the weighted value of logical address section 2 correspondence is added 1, be 2, after scheduler segment data table, also need the data in logical address section 15 to be stored to read cacheable memory region, the data that logical address section 2 stores are stored to generic storage region.Address field tables of data after renewal and weighted data table as shown in table 4:
Table 4
More than citing just the present invention for convenience of explanation, be not that the actual value of n is 10, the recording mode of the weighted value of logical address section and its correspondence neither necessarily adopt above-mentioned form.
The embodiment of the present invention by arrange storage area less read cacheable memory region, to be judged to be that the data of dsc data are read in cacheable memory region described in being stored to, make when reading described dsc data, directly read cacheable memory region from described reading, thus the address-time that can greatly reduce when dsc data reads, improve the reading efficiency of dsc data, there is stronger practicality.
embodiment two:
Fig. 2 shows the composition structure of data administrator in the flash memory device that the embodiment of the present invention two provides, and for convenience of explanation, illustrate only the part relevant to the embodiment of the present invention.
In this flash memory device, data administrator can be applied in flash memory device, can be the software unit run in flash memory device, the unit that combines of hardware cell or software and hardware, also can be integrated in flash memory device as independently suspension member or run in the application system of flash memory device.
In this flash memory device, data administrator comprises the first judging unit 21 and storage unit 22, wherein:
First judging unit 21, for judging whether the data in described flash memory device are dsc data;
Storage unit 22, for when described judging unit 21 judged result is for being, reading cacheable memory region described in described data being stored to, when described judging unit 21 judged result is no, described data being stored to described generic storage region.
Preferably, the storage area that the Hash memory pages reading storage area that cacheable memory region provides for the least significant bit page of multi-layered unit flash memory storage block in flash memory device and/or single layer cell flash memory storage block described in provides.
Further, described device also comprises:
Information table creating unit 23, for creating address field tables of data and weighted data table, described address field tables of data is for recording the logical address section depositing dsc data, and described weighted data table is for recording the weighted value of each described logical address section correspondence.
Further, described device also comprises:
Operational order receiving element 24, for the read operation order of Receiving Host system, carries logical address segment information in described read operation order;
Second judging unit 25, for judging whether the described logical address section of carrying in read operation order has been present in described address field tables of data;
First processing unit 26, for when described second judging unit 25 judged result is for being, reads corresponding data from described reading, and after having read, the weighted value corresponding with this logical address section in described weighted data table is added 1 cacheable memory region;
Second processing unit 27, for when described second judging unit 25 judged result is no, corresponding data are read from described generic storage region, and after having read, judge whether described address field tables of data and weighted data table are filled with data, if not, then the described logical address section of carrying in read operation order is updated in described address field tables of data, and in described weighted data table, record the weighted value of this logical address section correspondence, read cacheable memory region described in the data that this logical address section stores being stored to simultaneously, if described address field tables of data and weighted data table are filled with data, then search weighted value minimum in described weighted data table, logical address section corresponding for the described minimum weighted value found is updated to the described logical address section of carrying in read operation order, and described MINIMUM WEIGHT weight values is added 1 or the mean value that described MINIMUM WEIGHT weight values replaced with entitlement weight values in described weighted data table add 1, read cacheable memory region described in the data that the described logical address section of carrying in read operation order stores being stored to simultaneously, the data that the logical address section that described minimum weighted value is corresponding stores are stored to described generic storage region.
Further, described second processing unit 27 also for:
When there is multiple identical MINIMUM WEIGHT weight values in described weighted data table, then upgrade the logical address section that the MINIMUM WEIGHT weight values that finds at first is corresponding.
Those skilled in the art can be well understood to, for convenience and simplicity of description, only be illustrated with the division of above-mentioned each functional unit, module, in practical application, can distribute as required and by above-mentioned functions and be completed by different functional units or module, inner structure by device is divided into different functional units or module, to complete all or part of function described above.Each functional unit in embodiment, module can be integrated in a processing unit, also can be that the independent physics of unit exists, also can two or more unit in a unit integrated, above-mentioned integrated unit both can adopt the form of hardware to realize, and the form of SFU software functional unit also can be adopted to realize.In addition, the concrete title of each functional unit, module, also just for the ease of mutual differentiation, is not limited to the protection domain of the application.The specific works process of unit, module in said apparatus, with reference to the corresponding process in preceding method embodiment, can not repeat them here.
embodiment three:
Fig. 3 shows the composition structure of the flash memory device that the embodiment of the present invention three provides, and for convenience of explanation, illustrate only the part relevant to the embodiment of the present invention.
As shown in Figure 3, data administrator 31, at least one multi-layered unit flash memory 32 and/or single layer cell flash memory 33 during this flash memory device 3 comprises described in embodiment two flash memory device.
In the present embodiment, divide in flash memory device 3 in advance and one read cacheable memory region and generic storage region, the storage area that the wherein said Hash memory pages reading storage area that least significant bit page that cacheable memory region is multi-layered unit flash memory in flash memory device 32 storage block provides and/or single layer cell flash memory 33 storage block provides.In flash memory device, data administrator 31 will be judged to be that the data of dsc data read cacheable memory region described in being stored to, and will be judged to be that the data of cold data are stored to described generic storage region.
In flash memory device, the specific embodiment process of data administrator 31 is as described in embodiment two, does not repeat them here.
In addition, it should be noted that, those skilled in the art should be well understood to described flash memory device 3 can also comprise printed circuit board (PCB) (pcb board), capacitance-resistance electric capacity etc., and in described flash memory device, data administrator 31 can be integrated on described pcb board.
In sum, the embodiment of the present invention by arrange storage area less read cacheable memory region, to be judged to be that the data of dsc data are read in cacheable memory region described in being stored to, make when reading described dsc data, directly read cacheable memory region from described reading, thus the address-time that can greatly reduce when dsc data reads, improve the reading efficiency of dsc data, there is stronger practicality.
Those of ordinary skill in the art it is also understood that, the all or part of step realized in above-described embodiment method is that the hardware that can carry out instruction relevant by program has come, described program can be stored in a computer read/write memory medium, described storage medium, comprises ROM/RAM, disk, CD etc.
Above content is in conjunction with concrete preferred implementation further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention; make some equivalent alternative or obvious modification without departing from the inventive concept of the premise; and performance or purposes identical, all should be considered as belonging to the scope of patent protection that the present invention is determined by submitted to claims.
Claims (6)
1. the method for data management in a flash memory device, it is characterized in that, described flash memory device comprises reads cacheable memory region and generic storage region, described in read cacheable memory region memory capacity be less than the memory capacity in described generic storage region, described method comprises:
Create address field tables of data and weighted data table, described address field tables of data is for recording the logical address section depositing dsc data, and described weighted data table is for recording the weighted value of each described logical address section correspondence;
Judge whether the data in described flash memory device are dsc data;
If so, read cacheable memory region described in described data being stored to, otherwise described data are stored to described generic storage region;
Described method also comprises:
The read operation order of Receiving Host system, carries logical address segment information in described read operation order;
Judge whether the described logical address section of carrying in read operation order has been present in described address field tables of data;
If exist, read corresponding data cacheable memory region from described reading, and after having read, the weighted value corresponding with this logical address section in described weighted data table is added 1;
If do not exist, corresponding data are read from described generic storage region, and after having read, judge whether described address field tables of data and weighted data table are filled with data, if not, then the described logical address section of carrying in read operation order is updated in described address field tables of data, and records the weighted value of this logical address section correspondence in described weighted data table, described in the data that this logical address section stores being stored to, read cacheable memory region simultaneously, if described address field tables of data and weighted data table are filled with data, then search weighted value minimum in described weighted data table, logical address section corresponding for the described minimum weighted value found is updated to the described logical address section of carrying in read operation order, and described MINIMUM WEIGHT weight values is added 1 or the mean value that described MINIMUM WEIGHT weight values replaced with entitlement weight values in described weighted data table add 1, read cacheable memory region described in the data that the described logical address section of carrying in read operation order stores being stored to simultaneously, the data that the logical address section that described minimum weighted value is corresponding stores are stored to described generic storage region.
2. the method for claim 1, it is characterized in that, described in read storage area that cacheable memory region provides for the least significant bit page of multi-layered unit flash memory storage block in flash memory device and/or single layer cell flash memory storage block the storage area that provides of Hash memory pages.
3. the method for claim 1, is characterized in that, described method also comprises:
When there is multiple identical MINIMUM WEIGHT weight values in described weighted data table, then upgrade the logical address section that the MINIMUM WEIGHT weight values that finds at first is corresponding.
4. the device of data management in a flash memory device, it is characterized in that, described flash memory device comprises reads cacheable memory region and generic storage region, described in read cacheable memory region memory capacity be less than the memory capacity in described generic storage region, described device comprises:
Information table creating unit, for creating address field tables of data and weighted data table, described address field tables of data is for recording the logical address section depositing dsc data, and described weighted data table is for recording the weighted value of each described logical address section correspondence;
First judging unit, for judging whether the data in described flash memory device are dsc data;
Storage unit, for when described judging unit judged result is for being, reads cacheable memory region described in described data being stored to, when described judging unit judged result is no, described data being stored to described generic storage region;
Described device also comprises:
Operational order receiving element, for the read operation order of Receiving Host system, carries logical address segment information in described read operation order;
Second judging unit, for judging whether the described logical address section of carrying in read operation order has been present in described address field tables of data;
First processing unit, for when described second judging unit judged result is for being, reads corresponding data from described reading cacheable memory region, and after having read, the weighted value corresponding with this logical address section in described weighted data table is added 1;
Second processing unit, for when described second judging unit judged result is no, corresponding data are read from described generic storage region, and after having read, judge whether described address field tables of data and weighted data table are filled with data, if not, then the described logical address section of carrying in read operation order is updated in described address field tables of data, and in described weighted data table, record the weighted value of this logical address section correspondence, read cacheable memory region described in the data that this logical address section stores being stored to simultaneously, if described address field tables of data and weighted data table are filled with data, then search weighted value minimum in described weighted data table, logical address section corresponding for the described minimum weighted value found is updated to the described logical address section of carrying in read operation order, and described MINIMUM WEIGHT weight values is added 1 or the mean value that described MINIMUM WEIGHT weight values replaced with entitlement weight values in described weighted data table add 1, read cacheable memory region described in the data that the described logical address section of carrying in read operation order stores being stored to simultaneously, the data that the logical address section that described minimum weighted value is corresponding stores are stored to described generic storage region.
5. device as claimed in claim 4, is characterized in that, described second processing unit also for:
When there is multiple identical MINIMUM WEIGHT weight values in described weighted data table, then upgrade the logical address section that the MINIMUM WEIGHT weight values that finds at first is corresponding.
6. a flash memory device, is characterized in that, described flash memory device comprises the device of data management in the flash memory device described in claim 4 or 5.
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| CN103823766B (en) * | 2014-03-03 | 2017-03-22 | 山西科泰航天防务技术股份有限公司 | high-efficiency storage method of Flash memory |
| CN106528002A (en) * | 2016-12-06 | 2017-03-22 | 郑州云海信息技术有限公司 | Time-based storage scheduling method |
| CN112673359A (en) * | 2018-10-12 | 2021-04-16 | 华为技术有限公司 | Data processing method and device |
| CN111813573B (en) * | 2020-06-29 | 2022-09-20 | 中国平安人寿保险股份有限公司 | Communication method of management platform and robot software and related equipment thereof |
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