200849177 九、發明說明： ，【电明所屬之技術領域】 法。本發明係關於一種液晶顯示器及其公共電壓驅動方 【先前技術】 液晶顯示器因1且土一 特點，故於使用1日新Γ 輕薄短小及耗電低等 新，1種畔π 曰漸廣泛，且隨著相關技術之成熟及創 祈，其種類亦日益繁多。 請參閱圖1，传一錄Λ义 _、夜曰1§_種先珂技術液晶顯示器之示意圖。 包括—液晶顯示面板u 12、一掃描驅動器13、_ 才序&制。口 生器15。該掃描驅動界13及二乂4及-公共電壓產 液晶顯干面柘Μ 貢料驅動器14用於驅動該 狀日日，、、、貝不面板11，該時 器13及該資料驅動哭14卫〇Q用於控制該掃描驅動 液曰@ -、—動°。14。該公共電壓產生器15用於為該 液日日顯不面板只提供公共電壓。 、為口乂 131(=ί顯示…1包括複數平行之掃描線 資料線^(D1 複=订_且與言1掃描線131絕緣垂直相交之 16、複數金辛”:”公共電壓、線101、複婁丈薄膜電晶體 之公共電才^ 及—與該複數晝素電極相對設置 接至= 極連接至該掃描㈣，源極連200849177 IX. Description of invention: , [Technical field to which Mingming belongs] Law. The invention relates to a liquid crystal display and a common voltage driving method thereof. [Prior Art] Since the liquid crystal display has a characteristic of 1 and soil, the use of the new one is light and short, and the power consumption is low, and the first type of π is gradually widened. And with the maturity and innovation of related technologies, the types are also increasing. Please refer to Figure 1, a biography of Λ _, 曰 曰 1 § _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Including - liquid crystal display panel u 12, a scan driver 13, _ order & Mouthpiece 15. The scan driving interface 13 and the second and fourth common-voltage liquid crystal display dry surface 柘Μ tributary driver 14 is used to drive the shape of the day, day, and shell no panel 11, the time device 13 and the data drive cry 14 Defending Q is used to control the scanning drive liquid 曰 @ -, - movement °. 14. The common voltage generator 15 is used to provide only a common voltage for the liquid day display panel. For the mouth 131 (= ί display ... 1 includes a plurality of parallel scan line data lines ^ (D1 complex = set _ and 16 perpendicular to the insulated line of the scanning line 131, vertical complex): "common voltage, line 101 And the common electric circuit of the 娄 娄 薄膜 电 电 及 及 及 及 及 及 及 及 及 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜
壓產生器至該晝素電極W .該晝素電二7I==f 1G1連接至該公共電極 一亥公共電極18構成-液晶電容Qc。 7 200849177 该公共電壓線101平行於該資料線141設置於該液晶顯示 .面板11之一側。與該掃描線131及該資料線i4i絕緣。 ‘导°亥日守序控制益12產生複數掃描同步訊號用於控制該 掃描驅動器13’以及複數該資料同步訊號用於控制該資^ 驅動14。 、 "亥掃描驅動器13根據掃描同步訊號依次提供複數掃 ，，號至該掃描線131，該掃描線131所連接之複數薄膜 弘晶體16依次導通。在該掃描線131被掃描時，該資料驅 動器14根據資料同步訊號提供複數灰階電壓至該複數資 料線141。該灰階電壓經由對應導通之薄膜電晶體16施加 至該晝素電極17。 該公共電壓產生器15產生一 5 V直流公共電壓VcQm， / A ’、龟壓Vcom經由该公共電壓線施加至該公共電極 17 ’用於驅動該液晶顯示面板u。 通常，該公共電壓線1〇1與該資料線141之間具有一 閘極絕緣層’於是該公共電壓線1〇1與該資料線141之間 形成一寄生電容。故而當該複數資料線141之灰階電壓值 快速變化時，該公共電壓線101上之實際公共電壓會因液 曰日兒谷Clc之耦合作用而產生尖波（ripple)。從而使該液晶 顯示态ίο之顯示畫面發生串擾（cr〇sstalk)，該液晶顯示器 工〇之顯示晝面質量降低。 【發明内容】 有鏗於此，提供一種顯示晝面質量較高之液晶顯示器 實為必要。 200849177 提供一種顯示畫面質量較高之液晶顯示器之公共電壓 .驅動方法亦為必要。 一種液晶顯示器，其包括一液晶顯示面板、一公共電 壓產生器及一公共電壓補償器。該液晶顯示面板包括一公 共電極、一第一公共電壓線及一第二公共電壓線。該公共 電壓補償器包括一輸入端及一輸出端。該公共電壓產生器 經由該第一公共電壓線連接至該公共電極。該公共電壓補 償器之輸入端經由該第一公共電壓線連接至該公共電極， # 輸出端經由該第二公共電壓線連接至該公共電極。該公共 電壓產生器用於為該液晶顯示面板提供公共電壓，該公共 電壓補償器用於根據該實際公共電壓提供補償公共電壓至 該液晶顯示面板。 一種液晶顯示器之公共電壓驅動方法，其包括提供一 預定之公共電壓至一第一公共電壓線，檢測該第一公共電 壓線實際公共電壓，根據該實際公共電壓提供補償公共電 壓，輸出該補償公共電壓至一第二公共電壓線以補償實際 k 公共電壓。 相較於先前技術，本發明液晶顯示器及其公共電壓驅 動方法根據實際公共電壓提供補償公共電壓，使得公共電 壓保持穩定，因此該液晶顯示器之顯示畫面不會發生串 擾，進而具有較高之顯示晝面質量。 【實施方式】 請參閱圖2，係本發明液晶顯示器20 —較佳實施方式 之示意圖。該液晶顯示器20包括一液晶顯示面板21、一 9 200849177 時序控制器22、一掃描驅動器23、一資料驅動器24、一 .公共電壓產生器25及一公共電壓補償器29。該掃描驅動 器23及該資料驅動器24用於驅動該液晶顯示面板21，該 時序控制裔2 2用於控制該掃描驅動為2 3及該貧料驅動為 24。該公共電壓產生器25用於為該液晶顯示面板21提供 公共電壓。該公共電壓補償器29用於對該液晶顯示面板 21提供補償公共電壓。 該液晶顯示面板21包括複數平行之掃描線 231(G1〜Gn)、複數平行且與該掃描線231絕緣垂直相交之 資料線241(D1〜Dm)、一第一公共電壓線201、一第二公共 電壓線202、複數薄膜電晶體26、複數晝素電極27及一與 該複數晝素電極27相對設置之公共電極28。 該公共電壓補償器包括一輸入端296及一輸出端297。 該薄膜電晶體26之閘極連接至該掃描線231，源極連 接至該資料線241，汲極連接至該晝素電極27。該晝素電 極27與該公共電極28構成一液晶電容Clc。該公共電壓產 ^ 生器25經由該第一公共電壓線201連接至該公共電極 28。該公共電壓補償器29之輸入端296經由該第一公共電 壓線201連接至該公共電極28,輸出端297經由該第二公 共電壓線202連接至該公共電極28。該第一及第二公共電 壓線201、202平行於該資料線241設置於該液晶顯示面板 21二側。該第一公共電壓線201及該第二公共電壓202線 與該掃描線231及該資料線241絕緣。 請一併參閱圖3，係該公共電壓補償器29之電路結構 10 200849177 示意圖。該公共電壓補償器29進一步包括一第一薄膜電晶 ，體291、一第二薄膜電晶體292、一隔直電容293、一第一 ，直流端294及一第二直流端295。該第一薄膜電晶體291 之閘極連接至該第一直流端294並連接至該第一薄膜電晶 體291之源極。該第一薄膜電晶體291之汲極經由該第二 薄膜電晶體292之汲極、源極連接至該第二直流端295。 該第二薄膜電晶體292之閘極連接至該輸入端296。該隔 直電容293之一端連接至第二薄膜電晶體292之汲極，另 一端連接至該輸出端297。該第一直流端294提供一 20V 之高電壓電源Vgh，該第二直流端295提供一 IV之低電壓 電源Vdd。 該時序控制器22產生複數掃描同步訊號用於控制該 掃描驅動器23，以及複數資料同步訊號用於控制該資料驅 動器24。 該掃描驅動器23根據掃描同步訊號依次提供掃描訊 號至該掃描線231，該掃描線231所連接之複數薄膜電晶 ， 體26依次導通。在該掃描線231被掃描時，該資料驅動器 24根據資料同步訊號提供複數灰階電壓至該複數資料線 241。該灰階電壓經由對應導通之薄膜電晶體26施加至該 晝素電極27。 該公共電壓產生器25產生一 5 V之公共電壓VCQm，用 於驅動該液晶顯示面板21。該公共電壓VCQm經由該第一 公共電壓線201施加至該公共電極28。 該公共電壓補償器29之輸入端296接收來自該第一公 11 200849177 共電壓線201之實際公共電壓，輸出端297輸出補償公共 ，電壓至該第二公共電壓線202。 通常，該公共電壓線201與該資料線241之間具有一 閘極絕緣層，於是該公共電壓線201與該資料線241之間 形成一寄生電容。故當該複數資料線241之灰階電壓值快 速變化時，該公共電壓線201上之實際公共電壓會因液晶 電容Clc之|禺合作用而產生尖波（ripple)。 請一併參閱圖4，係該實際公共電壓與補償公共電壓 / 之波形圖。其中，係該第一公共電壓線201上之實際公 共電壓波形，因耦合作用而具有向上或向下方向之尖波。 w2係該補償公共電壓之波形，為一系列離散之向上或向下 方向之尖波，且與Wi之尖波對應，方向相反。 以ti〜t2期間為例對該公共電壓補償器之工作原理進 行說明： 當Wi所示實際公共電壓無尖波時，由於該第一薄膜 電晶體291之閘極連接至該第一直流端294，所以該第一 〔 薄膜電晶體291導通。該第二薄膜電晶體292之閘極連接 至該第一公共電壓線201，其閘極電壓為VCQm，所以該第 二薄膜電晶體292導通。此時該隔直電容293二端電壓無 變化，補償公共電壓為零。 當Wi所示實際公共電壓向下產生一小於VC()m之尖波 時，第二薄膜電晶體292之閘極電壓減小。該第二薄膜電 晶體292之閘極與源極間電壓減小，源極與汲極間導通電 阻增大。所以該第二薄膜電晶體292之源極與汲極間分壓 12 200849177 增大。該第二薄膜電晶體292之汲極之電壓升高。該補償 .公共電壓由於該隔直電容293之耦合作用產生一向上之正 電壓之尖波，如圖中W2波形所示。 當所示實際公共電壓向上產生一大於Vc_之尖波 時，該第二薄膜電晶體292之閘極電壓增大。該第二薄膜 電晶體292之閘極與源極間電壓增大，源極與汲極間導通 電阻減小。所以該第二薄膜電晶體292之源極與汲極間分 壓減小。該第二薄膜電晶體292之汲極之電壓降低。該補 ' 償公共電壓由於該隔直電容293之耦合作用產生一向下之 負電壓之尖波，如圖中W2波形所示。 即，每當該第一公共電壓線201上之實際公共電壓產 生尖波時，該公共電壓補償器29便輸出一相位相反之尖 波。該反方向之尖波經由該第二公共電壓線202施加至該 公共電極28，反相補償公共電壓之尖波，從而消除公共電 壓之尖波。 該液晶顯示器20包括一公共電壓補償器用於根據實 ^際公共電壓提供補償公共電壓，使公共電壓保持穩定，從 而該液晶顯示器之顯示晝面不會發生串擾，進而具有較高 之顯示晝面質量。 事實上，只需滿足高電壓直流電源Vgh範圍在15VS VghS25V，低電壓直流電源Vdd範圍在0V$ VddS3.3V即 可使本發明液晶顯示器具有較高之顯示晝面質量。 綜上所述，本發明確已符合發明專利之要件，爰依法 提出專利申請。惟，以上所述者僅為本發明之較佳實施方 13 200849177 式，本發明之範圍並不以上述實施方式為限，舉凡熟習本 -案技藝之人士援依本發明之精神所作之等效修飾或變化， _皆應涵蓋於以下申請專利範圍内。 【圖式簡早說明】 圖1係一種先前技術液晶顯示器之示意圖。 圖2係本發明液晶顯示器一較佳實施方式之示意圖。 圖3係圖2中公共電壓補償器之電路結構圖。 圖4係實際公共電壓與補償公共電壓之波形圖。 【主要元件符號說明】 液晶顯示器 20 晝素電極 27 第一公共電壓線 201 公共電極 28 第二公共電壓線 202 公共電壓補償器 29 液晶顯不面板 21 第一薄膜電晶體 291 時序控制器 22 第二薄膜電晶體 292 掃描驅動器 23 隔直電容 293 掃描線 231 第一直流端 294 貧料驅動為 24 第二直流端 295 資料線 241 輸入端 296 公共電壓產生器 25 輸出端 297 薄膜電晶體 26 14The voltage generator is connected to the halogen electrode W. The halogen electrode 2I==f 1G1 is connected to the common electrode, and the common electrode 18 constitutes a liquid crystal capacitor Qc. 7 200849177 The common voltage line 101 is disposed parallel to the data line 141 on one side of the liquid crystal display panel 11. It is insulated from the scanning line 131 and the data line i4i. The </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The "Hai scan driver 13 sequentially supplies a plurality of scans according to the scan sync signal to the scan line 131, and the plurality of thin films 16 connected by the scan line 131 are sequentially turned on. When the scan line 131 is scanned, the data drive 14 provides a complex gray scale voltage to the complex data line 141 based on the data sync signal. The gray scale voltage is applied to the halogen electrode 17 via the correspondingly turned-on thin film transistor 16. The common voltage generator 15 generates a 5 V DC common voltage VcQm, / A ', and the turtle voltage Vcom is applied to the common electrode 17' via the common voltage line for driving the liquid crystal display panel u. Generally, the common voltage line 〇1 and the data line 141 have a gate insulating layer ′, and a parasitic capacitance is formed between the common voltage line 〇1 and the data line 141. Therefore, when the gray scale voltage value of the complex data line 141 changes rapidly, the actual common voltage on the common voltage line 101 will generate a ripple due to the coupling of the liquid valley and the valley Clc. Therefore, crosstalk (cr〇sstalk) occurs in the display screen of the liquid crystal display state, and the quality of the display surface of the liquid crystal display device is lowered. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a liquid crystal display having a high quality of the kneading surface. 200849177 A common voltage for a liquid crystal display with a high picture quality is provided. A driving method is also necessary. A liquid crystal display comprising a liquid crystal display panel, a common voltage generator and a common voltage compensator. The liquid crystal display panel includes a common electrode, a first common voltage line and a second common voltage line. The common voltage compensator includes an input and an output. The common voltage generator is coupled to the common electrode via the first common voltage line. An input of the common voltage compensator is coupled to the common electrode via the first common voltage line, and an #output terminal is coupled to the common electrode via the second common voltage line. The common voltage generator is configured to provide a common voltage to the liquid crystal display panel, and the common voltage compensator is configured to provide a compensation common voltage to the liquid crystal display panel according to the actual common voltage. A common voltage driving method for a liquid crystal display, comprising: providing a predetermined common voltage to a first common voltage line, detecting an actual common voltage of the first common voltage line, providing a compensation common voltage according to the actual common voltage, and outputting the compensation common The voltage is applied to a second common voltage line to compensate for the actual k common voltage. Compared with the prior art, the liquid crystal display of the present invention and the common voltage driving method thereof provide a compensation common voltage according to the actual common voltage, so that the common voltage is kept stable, so that the display screen of the liquid crystal display does not crosstalk, and thus has a high display. Surface quality. [Embodiment] Please refer to Fig. 2, which is a schematic view of a preferred embodiment of a liquid crystal display 20 of the present invention. The liquid crystal display 20 includes a liquid crystal display panel 21, a 9 200849177 timing controller 22, a scan driver 23, a data driver 24, a common voltage generator 25, and a common voltage compensator 29. The scan driver 23 and the data driver 24 are used to drive the liquid crystal display panel 21, and the timing control device 2 2 is for controlling the scan drive to be 23 and the lean drive to be 24 . The common voltage generator 25 is for supplying a common voltage to the liquid crystal display panel 21. The common voltage compensator 29 is for supplying a compensation common voltage to the liquid crystal display panel 21. The liquid crystal display panel 21 includes a plurality of parallel scan lines 231 (G1 GGn), a plurality of parallel data lines 241 (D1 DDm) perpendicularly intersecting the scan lines 231, a first common voltage line 201, and a second The common voltage line 202, the plurality of thin film transistors 26, the plurality of halogen electrodes 27, and a common electrode 28 disposed opposite to the plurality of halogen electrodes 27. The common voltage compensator includes an input 296 and an output 297. The gate of the thin film transistor 26 is connected to the scan line 231, the source is connected to the data line 241, and the drain is connected to the germane electrode 27. The halogen electrode 27 and the common electrode 28 constitute a liquid crystal capacitor Clc. The common voltage generator 25 is connected to the common electrode 28 via the first common voltage line 201. An input 296 of the common voltage compensator 29 is coupled to the common electrode 28 via the first common voltage line 201, and an output 297 is coupled to the common electrode 28 via the second common voltage line 202. The first and second common voltage lines 201 and 202 are disposed on the two sides of the liquid crystal display panel 21 in parallel with the data line 241. The first common voltage line 201 and the second common voltage 202 line are insulated from the scan line 231 and the data line 241. Please refer to FIG. 3 together, which is a schematic diagram of the circuit structure 10 200849177 of the common voltage compensator 29. The common voltage compensator 29 further includes a first thin film transistor, a body 291, a second thin film transistor 292, a DC blocking capacitor 293, a first, a DC terminal 294 and a second DC terminal 295. The gate of the first thin film transistor 291 is connected to the first DC terminal 294 and is connected to the source of the first thin film transistor 291. The drain of the first thin film transistor 291 is connected to the second DC terminal 295 via the drain and source of the second thin film transistor 292. The gate of the second thin film transistor 292 is coupled to the input terminal 296. One end of the blocking capacitor 293 is connected to the drain of the second thin film transistor 292, and the other end is connected to the output terminal 297. The first DC terminal 294 provides a 20V high voltage power supply Vgh, and the second DC terminal 295 provides a IV low voltage power supply Vdd. The timing controller 22 generates a complex scan sync signal for controlling the scan driver 23, and a plurality of data sync signals for controlling the data driver 24. The scan driver 23 sequentially supplies scan signals to the scan lines 231 according to the scan sync signals. The plurality of thin film transistors connected to the scan lines 231 are sequentially turned on. When the scan line 231 is scanned, the data driver 24 provides a complex gray scale voltage to the complex data line 241 based on the data sync signal. The gray scale voltage is applied to the halogen electrode 27 via the correspondingly turned-on thin film transistor 26. The common voltage generator 25 generates a common voltage VCQm of 5 V for driving the liquid crystal display panel 21. The common voltage VCQm is applied to the common electrode 28 via the first common voltage line 201. The input 296 of the common voltage compensator 29 receives the actual common voltage from the first common voltage line 201 of 200849177, and the output 297 outputs the compensation common voltage to the second common voltage line 202. Generally, the common voltage line 201 and the data line 241 have a gate insulating layer, and a parasitic capacitance is formed between the common voltage line 201 and the data line 241. Therefore, when the gray scale voltage value of the complex data line 241 changes rapidly, the actual common voltage on the common voltage line 201 generates a ripple due to the cooperation of the liquid crystal capacitor Clc. Please refer to FIG. 4 together, which is a waveform diagram of the actual common voltage and the compensation common voltage /. Wherein, the actual common voltage waveform on the first common voltage line 201 has a sharp wave in an upward or downward direction due to the coupling action. W2 is the waveform of the compensation common voltage, which is a series of discrete sharp waves in the upward or downward direction, and corresponds to the sharp wave of Wi, and the direction is opposite. Taking the period of ti~t2 as an example, the working principle of the common voltage compensator is explained: when the actual common voltage indicated by Wi has no sharp wave, since the gate of the first thin film transistor 291 is connected to the first direct current end 294, so the first [thin film transistor 291 is turned on. The gate of the second thin film transistor 292 is connected to the first common voltage line 201, and the gate voltage thereof is VCQm, so the second thin film transistor 292 is turned on. At this time, the voltage at the two terminals of the DC blocking capacitor 293 does not change, and the compensation common voltage is zero. When the actual common voltage indicated by Wi produces a sharp wave that is less than VC()m, the gate voltage of the second thin film transistor 292 decreases. The voltage between the gate and the source of the second thin film transistor 292 is reduced, and the conduction resistance between the source and the drain is increased. Therefore, the source voltage between the source and the drain of the second thin film transistor 292 is increased by 12 200849177. The voltage of the drain of the second thin film transistor 292 is increased. The compensation. The common voltage generates a sharp wave of upward positive voltage due to the coupling of the DC blocking capacitor 293, as shown by the waveform of W2 in the figure. When the actual common voltage is shown to generate a sharp wave greater than Vc_, the gate voltage of the second thin film transistor 292 increases. The voltage between the gate and the source of the second thin film transistor 292 is increased, and the on-resistance between the source and the drain is reduced. Therefore, the voltage between the source and the drain of the second thin film transistor 292 is reduced. The voltage of the drain of the second thin film transistor 292 is lowered. The compensated common voltage generates a downward negative voltage spike due to the coupling of the DC blocking capacitor 293, as shown by the W2 waveform in the figure. That is, whenever the actual common voltage on the first common voltage line 201 produces a sharp wave, the common voltage compensator 29 outputs a sharp wave of opposite phase. The sharp wave in the opposite direction is applied to the common electrode 28 via the second common voltage line 202, and the sharp wave of the common voltage is inverted in reverse, thereby eliminating the sharp wave of the common voltage. The liquid crystal display 20 includes a common voltage compensator for providing a compensation common voltage according to the actual common voltage, so that the common voltage is kept stable, so that the display surface of the liquid crystal display does not crosstalk, thereby having a high display surface quality. . In fact, it is only necessary to satisfy the high voltage DC power supply Vgh range of 15VS VghS25V, and the low voltage DC power supply Vdd range of 0V$VddS3.3V to enable the liquid crystal display of the present invention to have a higher display quality. In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above is only the preferred embodiment 13 200849177 of the present invention, and the scope of the present invention is not limited to the above embodiments, and those skilled in the art will be equivalent to the spirit of the present invention. Modifications or variations, _ should be covered by the following patents. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view of a prior art liquid crystal display. 2 is a schematic view of a preferred embodiment of the liquid crystal display of the present invention. Figure 3 is a circuit diagram of the common voltage compensator of Figure 2. Figure 4 is a waveform diagram of the actual common voltage and the compensated common voltage. [Main component symbol description] Liquid crystal display 20 halogen electrode 27 First common voltage line 201 Common electrode 28 Second common voltage line 202 Common voltage compensator 29 Liquid crystal display panel 21 First thin film transistor 291 Timing controller 22 Second Thin film transistor 292 Scan driver 23 DC blocking capacitor 293 Scan line 231 First DC terminal 294 Lean material drive 24 Second DC terminal 295 Data line 241 Input terminal 296 Common voltage generator 25 Output terminal 297 Thin film transistor 26 14