TW200840079A - Eutectic bonding material of LED and packaging method - Google Patents

Eutectic bonding material of LED and packaging method Download PDF

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Publication number
TW200840079A
TW200840079A TW096109715A TW96109715A TW200840079A TW 200840079 A TW200840079 A TW 200840079A TW 096109715 A TW096109715 A TW 096109715A TW 96109715 A TW96109715 A TW 96109715A TW 200840079 A TW200840079 A TW 200840079A
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Taiwan
Prior art keywords
solid crystal
bonding
die
fluxing
eutectic
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TW096109715A
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Chinese (zh)
Inventor
zhi-hao Yang
cai-xue Lin
meng-nan Ji
heng-de Zhao
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High Power Lighting Corp
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Publication of TW200840079A publication Critical patent/TW200840079A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

The present invention is applicable to all packaging structures having a metallic die supporting base. The die fixation method adopted by the present invention is by eutectic bonding. In an embodiment of the present invention, an eutectic bonding material is first coated over the metallic supporting base upon which the LED die is positioned. The combination is then provided with an appropriate temperature to achieve eutectic bonding.

Description

200840079 九、發明說明： 【發明所屬之技術領域】 本發明係關於發光二極體之封裝，尤其是有關於發光二 極體封裝時固晶的接著材料及固晶之方法。 - 【先前技術】 .帛la〜Id ®所示係習知的發光二極體封裝所涉及的幾個 主要步驟。睛注意到’本例是採用本發明人所提出之中華民 (國發明專利申請號94M0253號之封褒結構。其中，底座1〇〇 包含基座102、電極104、以及隔離電極1〇4與基座1〇2的絕 緣物ι〇6,而以-體成型的方式形成。基座1〇2與電極1〇4 都是由高導電性與高導熱性的金屬材料所構成。絕緣物1〇6 則是由樹脂或類似的絕緣材料所構成。 首先，如第la圖所示，在基座1〇2的上表面塗佈一層適 當範圍的接著材料108。接著，如第lb圖所示，將發光二極 、 體晶粒150固著在基座102的接著材料108上而完成固晶的 ” 步驟。接下來，如第1c圖所示，將發光二極體晶粒15Q的正 ，負電極（未圖示）用導線（b〇nding wire或g〇id wire ) 12〇和 不同的電極104連接，而完成打線的步驟。在本例中，為了 使發光二極體晶粒150所發出的光線集中朝上與朝外，本封 裝結構還包含一個反射板11()，以適當的接著劑16〇與底座 100黏連，其内部具有一適當口徑且上下貫通的穿孔，以將 發光二極體晶粒150暴露出來並包圍其週緣。反射板n〇是 5 200840079 以高反射率的金屬材質（例如鋁）構成，或是由樹脂或類似 的絕緣材質構成但於穿孔壁面施以白塗裝、或塗佈有高反射 率的薄膜（例如鍍銀）。因此發光二極體晶粒150所發出的光 線得經由反射板110的穿孔内壁的反射而向上、向外射出。 再來，如第1 d圖所示，在反射板110的穿孔内填充透光性填 充物130，以封固與保護發光二極體晶粒150、導線120等元 件。透光性填充物130 —般是由矽膠或環氧樹脂或類似的透 明材料所構成的。 其中，固晶所用的接著材料108多數是使用環氧樹酯類 的材料，其優點是使用方法簡單，但其缺點就是易受到發光 二極體晶粒150所產生高溫而劣化、或是受到發光二極體晶 粒150所發出光線的傷害。當接著材料108劣化時，首先接 著材料108的接著力明顯下降，很容易造成發光二極體晶粒 150與基座102之間有間隙或無法緊密接合；此外，接著材 料108的導電性會明顯下降，相對的消耗功率就會升高。這 些都會造成整個封裝結構的熱散不良，最後導致發光二極體 晶粒150的故障。若接著材料108採用錫膏或合金來提供固 著與導通，這雖然沒有材料劣化及導電性明顯下降的問題， 但是由於金屬熔接所需溫度偏高，且設備複雜昂貴。 【發明内容】 因此，本發明之主要目的在提供發光二極體封裝過程中 6 200840079 固晶階段所用的接著材料以及固晶的方法，以解決前述習知 的接著材料在散熱與製程上的不盡理想之處。 本發明係適用於所有封裝結構中、承載晶粒之基座係以 金屬為材料者。本發明所採用的固晶方法主要是利用基板的 金屬材質而採用共晶接合。在本發明的一個實施例中，封裝 結構的金屬基座的上表面首先塗佈一層適當範圍的共晶接著 材料。接著，將發光二極體晶粒設置於基座的共晶接著材料 上。元成的成品再經由熱板、烤箱或隨道爐提供適當溫度而 完成共晶接合。共晶接著材料可以是無鉛的200840079 IX. Description of the Invention: [Technical Field] The present invention relates to a package for a light-emitting diode, and more particularly to a method for bonding a die-bonding material and a die bond for a light-emitting diode package. - [Prior Art] 帛la~Id® shows several main steps involved in the conventional LED package. It is noted that the present example is a sealing structure of the Chinese Patent Application No. 94M0253 proposed by the inventor of the present invention. The base 1 includes a susceptor 102, an electrode 104, and an isolating electrode 1〇4. The insulator 〇6 of the susceptor 1 〇 2 is formed by body molding. The susceptor 1 〇 2 and the electrode 1 〇 4 are both made of a metal material having high conductivity and high thermal conductivity. 〇6 is composed of a resin or a similar insulating material. First, as shown in Fig. 1a, a suitable range of the bonding material 108 is applied on the upper surface of the susceptor 1 〇 2. Next, as shown in Fig. 1b a step of fixing the light-emitting diodes and the bulk crystal grains 150 on the bonding material 108 of the susceptor 102 to complete the solid crystal. Next, as shown in FIG. 1c, the light-emitting diode crystal grains 15Q are positive. A negative electrode (not shown) is connected to a different electrode 104 by a wire (b〇nding wire or g〇id wire) 12〇, and the wire bonding step is completed. In this example, in order to make the light-emitting diode die 150 The emitted light is concentrated upwards and outwards, and the package structure also includes a reflector 11() for proper The primer 16 is adhered to the base 100, and has a proper diameter and a perforation penetrating through the upper and lower sides to expose the light-emitting diode die 150 and surround the periphery thereof. The reflector n〇 is 5 200840079 with high reflectivity Made of a metal material (such as aluminum), or made of resin or similar insulating material, but white coated on the perforated wall or coated with a high reflectivity film (such as silver plating). The light emitted by 150 is emitted upward and outward through the reflection of the inner wall of the perforation of the reflector 110. Next, as shown in Fig. 1d, the perforation of the reflector 110 is filled with a light-transmissive filler 130 to seal The light-emitting diodes 150, the wires 120, and the like are fixed and protected. The light-transmissive filler 130 is generally composed of silicone or epoxy resin or the like, and the majority of the bonding material 108 used for the solid crystal is used. It is a material using epoxy resin, which has the advantage that the method of use is simple, but the disadvantage is that it is susceptible to high temperature degradation of the light-emitting diode die 150 or is exposed to light emitted by the light-emitting diode die 150. When the subsequent material 108 is degraded, the adhesion force of the material 108 is firstly lowered, and the gap between the LED die 150 and the susceptor 102 is easily caused or not tightly bonded; further, the conductivity of the material 108 is followed. Will significantly decrease, the relative power consumption will increase. These will cause poor heat dissipation of the entire package structure, and finally lead to the failure of the LED die 150. If the material 108 is followed by solder paste or alloy to provide fixation and Turning on, although there is no problem of material deterioration and significant decrease in conductivity, the temperature required for metal welding is high, and the equipment is complicated and expensive. Accordingly, the main object of the present invention is to provide a light emitting diode package process. 6 200840079 The following materials used in the solid phase and the method of solid crystal to solve the above-mentioned unsatisfactory heat dissipation and process of the following materials. The present invention is applicable to all package structures in which the substrate carrying the die is made of metal. The die bonding method used in the present invention mainly uses eutectic bonding using the metal material of the substrate. In one embodiment of the invention, the upper surface of the metal pedestal of the package structure is first coated with a suitable range of eutectic bonding materials. Next, the light emitting diode crystal grains are placed on the eutectic bonding material of the susceptor. Yuancheng's finished product is then eutectic bonded via a hot plate, oven or accompanying furnace to provide the proper temperature. The eutectic bonding material can be lead-free

Sn、In、InSn、Sn, In, InSn,

InAg、BiSn、SnAg、SnSb、SnAgSb、SnAgCu、AuSn、AuGe、 AuSi 等材料、或是有鉛的 PbAg、BiPb、SnPbCd、SnPbBi、 SnPbAg、SnPbln、SnPb、SnPbSb、Pbln、PblnAg、Pb 等材 料。 茲配合所附圖示、實施例之詳細說明及申請專利範圍， 將上述及本發明之其他目的與優點詳述於後。然而，當可了 解所附圖示純係為解說本發明之精神而設，不當視為本發明 範疇之定義。有關本發明範疇之定義，請參照所附之申請專 利範圍。 【實施方式】 本發明是有關於發光二極體封裝過程中固晶階段所用的 接著材料以及固晶的方法。本發明係適用於所有封裝結構 7 200840079 中、承載晶粒之基座係以金屬為材質者。可能的例子之一就 是第la〜Id圖所示之、本發明人所提出之中華民國發明專利 申請號94140253 5虎之封裝結構。如圖所示，此封裝結構至少 包含底座1〇〇、反射板110、發光二極體晶粒150、複數條導 線120、以及透光性填充物130。底座100是由金屬基座1〇2、 複數個電極104、與絕緣物1〇6所一體成型構成而具有一扁 平的形狀。散熱座102與電極104都是由高導電性與高導熱 性的金屬材料所構成。絕緣物106則是由樹脂或類似的絕緣 材料所構成。唯此結構僅為適用的可能封裝結構之一，其他 以金屬材質作為基座者，均為本發明所得適用之環境。 封裝結構中採用金屬材質之基座之最大優點就是具有極 佳的散熱性，因此用於封裝尚凴度、高功率的發光二極體時 特別具有實效。但是在採用習知的接著方式將發光二極體晶 粒固定在金屬基座上時，除了接著材料有前述劣化的缺點 外，金屬的大膨脹係數，也會使得封裝過程中接著的良率降 低，因此需要不同於傳統的固晶方法。 本發明所採用的固晶方法主要是彻基板的金屬材質而 採用共晶接合（euteetie bonding)。共晶接合主要是基於二種 材料合金(aUoy)之雜會低料兩種材料各自的熔點，因此 可以較低的溫度進行接合。比如說，金f用於接合二個石夕晶 片i與石夕的共晶溫度約3630C，比例{ 9711wt〇/〇的金與 200840079 2.9wt%的矽。因此在矽晶片的接合面濺鍍一層金，再施予適 當的溫度即可將二個石夕晶片接合在一起。共晶是—種常用於 將二片以上的晶圓永久接合在一起的技術（稱為Μ知 bondmg)，另外亦有先前技術是以共晶方法接合晶粒與陶瓷 基板，但據本發明人瞭解，尚未有在發光二極體封裝過程中， 採用共晶方法接合發光二極體晶粒與金屬基座者。 第2a圖所示係本發明一第一實施例之示意圖。如圖所 示，基座102的上表面首先塗佈一層適當範圍的共晶接著材 料200。接著，將發光二極體晶粒15〇設置於基座1〇2的共 晶接著材料200上。第2a圖所示的成品再經由熱板、烤箱或 隨道爐&供適當溫度而完成共晶接合。共晶接著材料2〇〇可 以是無錯的 Sn、In、InSn、InAg、BiSn、SnAg、SnSb、SnAgSb、 SnAgCu、AuSn、AuGe、AuSi 等材料、或是有錯的 pbAg、 BiPb、SnPbCd、SnPbBi、SnPbAg、SnPbln、SnPb、SnPbSb、Materials such as InAg, BiSn, SnAg, SnSb, SnAgSb, SnAgCu, AuSn, AuGe, AuSi, or lead PbAg, BiPb, SnPbCd, SnPbBi, SnPbAg, SnPbln, SnPb, SnPbSb, Pbln, PblnAg, Pb, and the like. The above and other objects and advantages of the present invention will be described in detail with reference to the accompanying drawings and claims. However, it is to be understood that the appended drawings are merely illustrative of the scope of the invention. For the definition of the scope of the invention, please refer to the attached patent application. [Embodiment] The present invention relates to a subsequent material and a method of solid crystal for use in a solid crystal phase in a package process of a light-emitting diode. The present invention is applicable to all package structures. In 200840079, the pedestal carrying the die is made of metal. One of the possible examples is the packaging structure of the Chinese Inventor Patent Application No. 94140253 5, which is shown by the inventor of the present invention. As shown, the package structure includes at least a base 1 , a reflector 110 , a light emitting diode die 150 , a plurality of wires 120 , and a light transmissive filler 130 . The base 100 has a flat shape formed by integrally forming a metal base 1 2, a plurality of electrodes 104, and an insulator 1〇6. Both the heat sink 102 and the electrode 104 are made of a metal material having high conductivity and high thermal conductivity. The insulator 106 is made of a resin or a similar insulating material. However, the structure is only one of the possible possible package structures, and other metal materials are used as the base, which are suitable environments for the present invention. The biggest advantage of the metal-based pedestal in the package structure is its excellent heat dissipation, so it is particularly effective for packaging light-emitting diodes with high power and high power. However, when the light-emitting diode die is fixed on the metal pedestal in a conventional bonding manner, in addition to the disadvantage that the material has the aforementioned deterioration, the large expansion coefficient of the metal causes the subsequent yield in the packaging process to decrease. Therefore, it is required to be different from the conventional solid crystal method. The die bonding method used in the present invention mainly uses the metal material of the substrate to employ euteetie bonding. The eutectic bonding is mainly based on the melting point of each of the two material alloys (aUoy), which can be joined at a lower temperature. For example, gold f is used to join the two eutectic wafers i and Shi Xi's eutectic temperature of about 3630 C, the ratio of { 9711 wt〇 / 〇 gold and 200840079 2.9 wt% 矽. Therefore, a layer of gold is sputtered on the bonding surface of the germanium wafer, and then the appropriate temperature is applied to bond the two stone wafers together. Eutectic is a technique commonly used to permanently bond two or more wafers together (called known as bondmg). In addition, the prior art is to join the die and the ceramic substrate by eutectic method, but according to the inventor It is understood that there has not been a eutectic method for bonding light-emitting diode dies and metal pedestals in a light-emitting diode package process. Figure 2a is a schematic view of a first embodiment of the present invention. As shown, the upper surface of the susceptor 102 is first coated with a suitable range of eutectic backing material 200. Next, the light-emitting diode die 15 is placed on the eutectic bonding material 200 of the susceptor 1 〇 2 . The finished product shown in Figure 2a is then eutectic bonded via a hot plate, oven or accompanying furnace & The eutectic bonding material 2〇〇 may be an error-free material such as Sn, In, InSn, InAg, BiSn, SnAg, SnSb, SnAgSb, SnAgCu, AuSn, AuGe, AuSi, or erroneous pbAg, BiPb, SnPbCd, SnPbBi. , SnPbAg, SnPbln, SnPb, SnPbSb,

Pbln、PblnAg、Pb 等材料。 在前述的實施例裡，除了使用的共晶接著材料外，還可 以輔以適當的助銲材料。以下是一些可能的助銲材料： 1. 由60.0〜75.0%的Bi及40.0〜25.0%的In所組成。 2. 由40.0〜60.0%的In及60.0〜40.0%的Sn所組成。 3. 由50.0〜65.0%的Bi及50.0〜35.0%的Sn所組成。 4. 由90.0〜99.0%的In及10.0〜1.0%的Ag所組成。 9 200840079 5. 由 45·0〜55.0%的 Sn、40.0〜25.0%鉛(Pb)、及 15.0〜25.0%的Ag所組成。 6. 由 75.0〜85.0%的 In、10.0〜20.0%的 Pb、及 1.0〜15.0% 的Ag所組成。 7. 由 40.0〜45.0%的 Sn、40.0〜45.0%的 Pb、及 10.0〜15.0%的Bi所組成。 8. 由100%的銦所組成。 f 9. 由 55·0〜70.0%的 Sn、40.0〜25.0%的 Pb、及 1.0〜5.0% 的Ag所組成。 10. 由 30.0〜45.0%的 Sn、30.0〜45.0%的 Pb、及 10.0〜35.0%的In所組成。 11. 由60.0〜80.0%的Sn、及40.0〜20.0%的Pb所組成。 12. 由 45.0〜55.0%的 Bi、30.0〜25.0%的 Pb、20.0〜10.0% 的Sn及10.0〜15.0%的的Sb所組成。 ^ 13.由 85.0〜99.0°/。的 In 及 15·0〜1.0%的 Ag 所組成。 14. 由90.0〜99.0%的Sn及10.0〜1.0%的Au所組成。 15. 由 90.0〜99.0%的 Sn、5.0〜1.0%的 Ag 及 1.0〜0.5%的 Cu所組成。 16. 由90.0〜99.0%的Sn及10.0〜1.0%的Ag所組成。 17. 由90.0〜99·0%的Sn及10.0〜1.0%的Sb所組成。 18. 由70.0〜85.0%的Pb及30.0〜15.0%的In所組成。 10 200840079 19.由25·0〜15.0%的Sn、及75.0〜85.0%的Au所組成。 20·由 85.0〜95.0%的 Pb、1〇.〇〜1.〇〇/〇的 Sn、及 5 〇〜！·〇〇/〇 的Ag所組成。 21·由 90.0〜99.0%的 Sn、及 10.04 0〇/〇的 Ge 所組成。 22. 由80.0〜99.0%的Au、及20.0〜ι·〇%的Ge所組成。 23. 由 90.0〜99.0%的 Au、及 lo.oq 〇〇/。的 si 所組成。 24·由90.0〜99.0%的Pb、及1〇·〇〜的知所組成。 V 第2b圖所示係本發明一第二實施例之示意圖。如圖所 示，發光二極體晶粒150之與基座102的接合面首先塗佈一 層共晶接觸材料202 (請注意，和共晶接著材料2〇〇不同）。 接著，直接將發光二極體晶粒150設置於基座1〇2上。第2b 圖所示的成品再經由熱板、烤箱或隧道爐提供適當溫度而完 成共晶接合。共晶接觸材料202可以是Sn、In、InSn、InAg、Pbln, PblnAg, Pb and other materials. In the foregoing embodiments, in addition to the eutectic bonding material used, a suitable fluxing material may be added. The following are some possible fluxing materials: 1. It consists of 60.0~75.0% Bi and 40.0~25.0% In. 2. It consists of 40.0~60.0% In and 60.0~40.0% Sn. 3. It consists of 50.0~65.0% Bi and 50.0~35.0% Sn. 4. It consists of 90.0~99.0% In and 10.0~1.0% Ag. 9 200840079 5. It consists of 45·0~55.0% Sn, 40.0~25.0% lead (Pb), and 15.0~25.0% Ag. 6. It consists of 75.0~85.0% In, 10.0~20.0% Pb, and 1.0~15.0% Ag. 7. It consists of 40.0~45.0% Sn, 40.0~45.0% Pb, and 10.0~15.0% Bi. 8. Consists of 100% indium. f 9. It consists of 55·0~70.0% Sn, 40.0~25.0% Pb, and 1.0~5.0% Ag. 10. It consists of 30.0~45.0% Sn, 30.0~45.0% Pb, and 10.0~35.0% In. 11. It consists of 60.0~80.0% Sn and 40.0~20.0% Pb. 12. It consists of 45.0~55.0% Bi, 30.0~25.0% Pb, 20.0~10.0% Sn and 10.0~15.0% Sb. ^ 13. From 85.0 to 99.0 ° /. In and 15·0~1.0% of Ag are composed. 14. It consists of 90.0~99.0% Sn and 10.0~1.0% Au. 15. It consists of 90.0~99.0% Sn, 5.0~1.0% Ag and 1.0~0.5% Cu. 16. It consists of 90.0~99.0% Sn and 10.0~1.0% Ag. 17. It consists of 90.0~99·0% of Sn and 10.0~1.0% of Sb. 18. It consists of 70.0~85.0% Pb and 30.0~15.0% In. 10 200840079 19. It consists of 25·0~15.0% of Sn and 75.0~85.0% of Au. 20· From 85.0 to 95.0% of Pb, 1〇.〇~1.〇〇/〇 of Sn, and 5 〇~! · 〇〇 / 〇 Ag consists of. 21· It consists of 90.0~99.0% Sn and 10.04 0〇/〇 Ge. 22. It consists of 80.0 to 99.0% of Au and 20.0 to 1% of Ge. 23. From 90.0 to 99.0% Au, and lo.oq 〇〇/. The composition of si. 24· It consists of 90.0 to 99.0% of Pb and 1〇·〇~. V Figure 2b is a schematic view of a second embodiment of the present invention. As shown, the junction of the LED die 150 with the pedestal 102 is first coated with a layer of eutectic contact material 202 (note that it is different from the eutectic bonding material 2). Next, the light emitting diode die 150 is directly placed on the susceptor 1 〇2. The finished product shown in Figure 2b is then comminuted by providing the appropriate temperature via a hot plate, oven or tunnel furnace. The eutectic contact material 202 can be Sn, In, InSn, InAg,

BiSn、SnAg、SnSb、SnAgSb、SnAgCu、AuSn、AuGe、AuSi、 v PbAg、BiPb、SnPbCd、SnPbBi、SnPbAg、SnPbln、SnPb、BiSn, SnAg, SnSb, SnAgSb, SnAgCu, AuSn, AuGe, AuSi, v PbAg, BiPb, SnPbCd, SnPbBi, SnPbAg, SnPbln, SnPb,

SnPbSb、Pbln、PblnAg、Pb 等材料。 苐2c圖所示係本發明一第三實施例之示意圖。如圖所 示，共晶接觸材料202是先塗佈在基座102上的適當範圍内。 接著，再將發光二極體晶粒150設置於基座102的共晶接觸 材料202上。第2c圖所示的成品再經由熱板、烤箱或隧道爐 提供適當溫度而完成共晶接合。 11 200840079 在前述的第二、三實施例裡，除了使用共晶接觸材料202 外，還可以輔以前述的助銲材料。 本發明可以批次的方式在包含多個底座的金屬基板上一 起施作前述固晶的動作（包含經由熱板、烤箱或隧道爐的迴 銲），完成後再予以切割分離。也可以先將個別的底座切割分 離，然後針對個別底座分別施作前述固晶的動作（包含經由 熱板、烤箱或隧道爐的迴銲）。為了避免金屬基座的熱漲冷縮 受溫度衝擊而影響共晶的效果，後者是良率比較高的作法。 藉由以上較佳具體實施例之詳述，係希望能更加清楚描 述本創作之特徵與精神，而並非以上述所揭露的較佳具體實 施例來對本創作之範疇加以限制。相反地，其目的是希望能 涵蓋各種改變及具相等性的安排於本創作所欲申請之專利範 圍的範缚内。 【圖式簡單說明】 第la〜Id圖所示係習知的發光二極體封裝所涉及的幾個主要 步驟。 第2a圖所示係本發明的封裝結構一第一實施例的側視剖面 圖。 第2b圖所示係本發明的封裝結構一第二實施例的側視剖面 圖。 第2c圖所示係本發明的封裝結構一第三實施例的側視剖面 12 200840079 圖。 【主要元件符號說明】 100 底座 102 基座 104 電極 106 絕緣物 108 接著材料 110 反射板 120 導線 130 透光性填充物 150 二極體晶粒 160 接著劑 200 共晶接著材料 202 共晶接觸材料 13SnPbSb, Pbln, PblnAg, Pb and other materials. Figure 2c is a schematic view of a third embodiment of the present invention. As shown, the eutectic contact material 202 is first coated on a suitable extent on the susceptor 102. Next, the LED die 150 is placed on the eutectic contact material 202 of the susceptor 102. The finished product shown in Fig. 2c is then subjected to eutectic bonding by providing a suitable temperature via a hot plate, oven or tunnel furnace. 11 200840079 In the foregoing second and third embodiments, in addition to the use of the eutectic contact material 202, the aforementioned fluxing material may be supplemented. The present invention can be applied in a batch manner on the metal substrate including a plurality of bases to perform the aforementioned solid crystal action (including reflow through a hot plate, an oven or a tunnel furnace), and then cut and separated. It is also possible to first separate the individual bases and then apply the aforementioned solid crystal action (including reflow through a hot plate, oven or tunnel furnace) for individual bases. In order to avoid the thermal expansion and contraction of the metal pedestal, the effect of the eutectic is affected by the temperature shock, and the latter is a relatively high yield. The features and spirit of the present invention are more clearly described in the above detailed description of the preferred embodiments, and the scope of the present invention is not limited by the preferred embodiments disclosed herein. On the contrary, the purpose is to cover all kinds of changes and equivalences within the scope of the patent scope of the application. [Simplified Schematic Description] The first to the right diagrams of the conventional LED package are shown in the first to the right. Figure 2a is a side cross-sectional view showing a first embodiment of the package structure of the present invention. Figure 2b is a side cross-sectional view showing a second embodiment of the package structure of the present invention. Figure 2c is a side cross-sectional view of a third embodiment of the package structure of the present invention 12 200840079. [Main component symbol description] 100 Base 102 Base 104 Electrode 106 Insulation 108 Next material 110 Reflector 120 Conductor 130 Translucent filler 150 Diode grain 160 Subsequent 200 Eutectic bonding material 202 Eutectic contact material 13

Claims (1)

200840079 十、申請專利範圍： 1· 一種發光二極體封裝過程的固晶材料，係適用於封裝結 構採用一金屬材質基座者，該固晶材料係設置於一發光 二極體晶粒與該金屬材質基座之間，且係以一共晶製程 完成該發光二極體晶粒之固著於該金屬材質基座上，該 固晶材料係下列材料之一：無錯的Sn、In、InSn、InAg、 BiSn、SnAg、SnSb、SnAgSb、SnAgCu、AuSn、AuGe、 f AuSi ;以及有鉛的 pbAg、BiPb、SnPbCd、SnPbBi、 \ . . SnPbAg、SnPbln、SnPb、SnPbSb、Pbln、PblnAg、Pb o 2 ·如申請專利範圍第i項所述固晶材料’其中該固晶材料 係先塗佈於該金屬材質基座上，再與該發光二極體晶粒 進行共晶製程。 3.如申請專利範圍第1項所述固晶材料，其中該固晶材料 係先塗佈於該發光二極體晶粒與該金屬材質基座之接合 【 面上，再與該金屬材質基庫進行共晶製程。 4· 一種發光二極體封裝過程的固晶方法，係適用於封裝結構 採用一金屬材質基座者，該固晶方法至少包含下列步驟： 在基座的上表面塗佈_適當範圍的共晶材料， 將一發光二極體晶粒設f於該基座的該共晶接著材料 上；以及 提供適當溫度以完成共晶操合。 5. —種發光二極體封裝過程的固晶方法，係適用於封裝結構 14 200840079 採用一金屬材質基座者，該固晶方法至少包含下列步驟： 在一發光二極體晶粒與該基座的接合面塗佈一共晶材 料； 將該發光二極體晶粒設置於該基座上；以及 提供適當溫度以完成共晶接合。 6·如申請專利範圍第4項獲第5項所述之固晶方法，其中 該固晶材料係下列材料之一：無錯的Sn、In、InSn、InAg、 BiSn、SnAg、SnSb、SnAgSb、SnAgCu、AuSn、AuGe、 AuSi ;以及有鉛的 PbAg、BiPb、SnPbCd、SnPbBi、 SnPbAg、SnPbln、SnPb、SnPbSb、Pbln、PblnAg、Pb o 7·如申請專利範圍第4項或第5項所述之固晶方法，進一 步包含下列步驟： 提供一助銲材料。 8·如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由60.0〜75.0%的Bi及40.0〜25.0%的in所組成。 9·如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由40.0〜60.0%的化及6〇.〇〜40.0%的Sn所組成。 10·如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由50.0〜65.0%的Bi及50 0〜35 〇%的811所組成。 11.如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由90.0〜99.0%的比及noq.o%的Ag所組成。 15 200840079 12. 如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由 45.0 〜55.0% 的 Sn、40.0 〜25.0% 鉛（Pb)、及 15.0〜25.0%的Ag所組成。 13. 如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由 75.0〜85.0%的 In、10.0〜20.0%的 Pb、及 1.0〜15.0% 的Ag所組成。 14. 如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由 40.0〜45.0%的 Sn、40.0〜45.0%的 Pb、及 10.0〜15.0% 的Bi所組成。 15. 如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由100%的銦所組成。 16. 如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由 55.0〜70.0%的 Sn、40·0〜25.0%的 Pb、及 1.0〜5.0% 的Ag所組成。 17. 如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由 30.0〜45.0%的 Sn、30.0〜45.0%的 Pb、及 10.0〜35.0%的In所組成。 18. 如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由60.0〜80.0%的Sn、及40.0〜20.0°/〇的Pb所組成。 19. 如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由 45.0〜55.0%的 Bi、30.0〜25.0%的 Pb、20.0〜10.0% 16 200840079 的Sn及10.0〜15.0%的的Sb所組成。 20. 如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由85.0〜99.0%的In及15.0〜1.0%的Ag所組成。 21. 如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由90.0〜99.0%的Sn及10.0〜1.0%的Au所組成。 22. 如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由90.0〜99.0%的Sn、5.0〜1.0%的Ag及1.0〜0.5%的 ( Cu所組成。 23. 如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由90.0〜99.0%的Sn、及10.0〜1.0%的Ag所組成。 24. 如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由90.0〜99.0%的Sn、及10.0〜1.0°/。的Sb所組成。 25. 如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由70.0〜85.0%的Pb、及30.0〜15.0%的In所組成。 、 26.如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由25.0〜15.0%的Sn、及75.0〜85.0%的Au所組成。 27. 如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由由85.0〜95.0%的Pb、10.0〜1.0%的、Sn及5.0〜1.0% 的Ag所組成。 28. 如申請專利範圍第7項所述之固晶方法，其中該助銲材 料係由90.0〜99.0%的Sn、及10.0〜1.0%的Ge所組成。 17 200840079 29. 如申請專利範圍第7 料係由80.0〜99.0%的 30. 如申請專利範圍第7 料係由90.0〜99.0%的 31. 如申請專利範圍第7 料係由90.0〜99.0%的 項所述之固晶方法，其中該助銲材 Au、及20.0〜1.0%的Ge所組成。 項所述之固晶方法，其中該助銲材 Au、及10.0〜1.0%的Si所組成。 項所述之固晶方法，其中該助銲材 Pb、及10.0〜1.0%的Ag所組成。200840079 X. Patent application scope: 1. A solid crystal material for a light-emitting diode package process, which is suitable for a package structure using a metal base, the solid crystal material is disposed on a light-emitting diode die and the The metal substrate is fixed on the metal substrate by a eutectic process, and the die bonding material is one of the following materials: the error-free Sn, In, InSn , InAg, BiSn, SnAg, SnSb, SnAgSb, SnAgCu, AuSn, AuGe, f AuSi; and leaded pbAg, BiPb, SnPbCd, SnPbBi, \ . . SnPbAg, SnPbln, SnPb, SnPbSb, Pbln, PblnAg, Pb o 2 The solid crystal material as described in claim i wherein the solid crystal material is first coated on the metal substrate and then eutectic with the light emitting diode die. 3. The die bonding material according to claim 1, wherein the die bonding material is first applied to the bonding surface of the light emitting diode die and the metal substrate, and then to the metal substrate. The library performs a eutectic process. 4. A die bonding method for a light emitting diode package process, which is suitable for a package structure using a metal substrate, the solid crystal method comprising at least the following steps: coating an appropriate range of eutectic on the upper surface of the pedestal a material, a light emitting diode die is disposed on the eutectic bonding material of the susceptor; and a suitable temperature is provided to complete the eutectic operation. 5. A die bonding method for a light emitting diode package process, which is suitable for a package structure 14 200840079. A metal substrate is used, and the die bonding method comprises at least the following steps: in a light emitting diode die and the base The joint surface of the seat is coated with a eutectic material; the light emitting diode die is disposed on the susceptor; and a suitable temperature is provided to complete the eutectic bonding. 6. The method of solid crystal bonding according to item 5, wherein the solid crystal material is one of the following materials: Sn, In, InSn, InAg, BiSn, SnAg, SnSb, SnAgSb, And SnP, Cu, Cu, Cu The die bonding method further comprises the steps of: providing a fluxing material. 8. The method of solid crystal bonding according to claim 7, wherein the fluxing material is composed of 60.0 to 75.0% of Bi and 40.0 to 25.0% of in. 9. The method of solid crystal bonding according to claim 7, wherein the fluxing material consists of 40.0 to 60.0% of crystallization and 6 〇.4 to 40.0% of Sn. 10. The method of solid crystal bonding according to claim 7, wherein the fluxing material is composed of 50.0 to 65.0% of Bi and 50 to 35% by weight of 811. 11. The die bonding method according to claim 7, wherein the fluxing material is composed of a ratio of 90.0 to 99.0% and noq.o% of Ag. The method of solid-crystal bonding according to claim 7, wherein the fluxing material is composed of 45.0 to 55.0% of Sn, 40.0 to 25.0% of lead (Pb), and 15.0 to 25.0% of Ag. . 13. The method of solid crystal bonding according to claim 7, wherein the fluxing material is composed of 75.0 to 85.0% of In, 10.0 to 20.0% of Pb, and 1.0 to 15.0% of Ag. 14. The method of solid crystal bonding according to claim 7, wherein the fluxing material is composed of 40.0 to 45.0% of Sn, 40.0 to 45.0% of Pb, and 10.0 to 15.0% of Bi. 15. The die bonding method of claim 7, wherein the fluxing material consists of 100% indium. 16. The method of solid crystal bonding according to claim 7, wherein the fluxing material is composed of 55.0 to 70.0% of Sn, 40. 0 to 25.0% of Pb, and 1.0 to 5.0% of Ag. 17. The die bonding method according to claim 7, wherein the fluxing material is composed of 30.0 to 45.0% of Sn, 30.0 to 45.0% of Pb, and 10.0 to 35.0% of In. 18. The method of solid crystal bonding according to claim 7, wherein the fluxing material consists of 60.0 to 80.0% of Sn and 40.0 to 20.0 °/〇 of Pb. 19. The method of solid crystal bonding according to claim 7, wherein the fluxing material is 45.0 to 55.0% Bi, 30.0 to 25.0% Pb, 20.0 to 10.0% 16 200840079 of Sn, and 10.0 to 15.0%. The composition of Sb. 20. The method of solid crystal bonding according to claim 7, wherein the fluxing material consists of 85.0 to 99.0% of In and 15.0 to 1.0% of Ag. 21. The method of solid crystal bonding according to claim 7, wherein the fluxing material consists of 90.0 to 99.0% of Sn and 10.0 to 1.0% of Au. 22. The method of solid crystal bonding according to claim 7, wherein the fluxing material is composed of 90.0 to 99.0% of Sn, 5.0 to 1.0% of Ag, and 1.0 to 0.5% of (Cu). The method of solid crystal bonding according to claim 7, wherein the fluxing material is composed of 90.0 to 99.0% of Sn and 10.0 to 1.0% of Ag. 24. The solid solution according to claim 7 The method of crystallizing, wherein the fluxing material is composed of 90.0 to 99.0% of Sn, and 10.0 to 1.0% of Sb. 25. The method of bonding according to claim 7, wherein the fluxing material The method of solid-crystallizing according to the seventh aspect of the invention, wherein the fluxing material is from 25.0 to 15.0% of Sn, And 75.0 to 85.0% of the composition of Au. 27. The method of solid crystal according to claim 7, wherein the fluxing material is composed of 85.0 to 95.0% of Pb, 10.0 to 1.0%, Sn and 5.0. The composition of the solid solution according to claim 7, wherein the fluxing material is composed of 90.0 to 99.0% of Sn and 10.0 to 1.0% of Ge. 17 200840079 29. As claimed in the patent application, the 7th material is from 80.0 to 99.0% of 30. If the scope of application is 7th, the material is from 90.0 to 99.0%. 31. If the scope of application is 7th, the material is from 90.0 to 99.0. The solid crystal method according to the item, wherein the auxiliary material Au and 20.0 to 1.0% of Ge are used. The solid crystal method according to the item, wherein the auxiliary material Au and 10.0 to 1.0% of Si are used. The solid crystal method according to the item, wherein the flux Pb and 10.0 to 1.0% of Ag are composed. 1818
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2328192A2 (en) 2009-11-27 2011-06-01 Industrial Technology Research Institute Die-bonding method of LED chip and LED manufactured by the same
TWI466253B (en) * 2012-10-08 2014-12-21 Ind Tech Res Inst Dual-phase intermetallic interconnection structure and method of fabricating the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2328192A2 (en) 2009-11-27 2011-06-01 Industrial Technology Research Institute Die-bonding method of LED chip and LED manufactured by the same
US8236687B2 (en) 2009-11-27 2012-08-07 Industrial Technology Research Institute Die-bonding method of LED chip and LED manufactured by the same
TWI466253B (en) * 2012-10-08 2014-12-21 Ind Tech Res Inst Dual-phase intermetallic interconnection structure and method of fabricating the same

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