200828458 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半 種可供複數封裝結構進行堆 堆疊結構。 【先前技術】 導體封裝件及其製法，尤指一 ®之半導體封裝件及其製法與 井在小型化之餘’仍要求性能與處理速度之提 升。&升性能與處理速度之較佳方法，不外乎是增加半導 件中之晶片數量或尺寸，惟供晶片接置之基板上所 心之面積往往無法供複數個晶$水平設置或較大尺寸 之晶片？置放。故而，目前之發展乃著眼於複數個封裝件 上下堆疊之堆疊式多封裝件模組(paekage⑽^ e POP )〇 &， 凊茶閱第1圖，美國專利第5,222,014號揭露一種半 導_裝件之POP堆疊結構，其係提供—上表面設置有複 數堆4：鋅墊（stacked pad)110之球柵陣列⑺GA)基板u，以 在该基板11上接置半導體晶片1〇並形成包覆該半導體晶 片10之封裝體13,以形成下層半導體封裝件1〇1，接著將 一完成封裝之上層半導體封裝件1〇2透過銲球14而接置並 電性連接至該下層半導體封裝件1〇1之基板表面的堆疊銲 塾110上’藉以形成一半導體封裝件之POP堆疊結構。 然’由於前述該上層半導體封裝件與下層半導體封裝 件係藉銲球回銲而電性連接，而該銲球高度H 一般為 〇.5mm，如此將限制下層半導體封裝件之封裝體之高度h 5 110127 200828458 :广i:銲球高度H，即該封裝體之高度h正常大約在 接曰：：，然而封裝體過低之高度會影響到用以 ==銲線的銲線品質’邮 另外，該T層半㈣難件之封裝體雜最近銲塾之 至二：：Γ.25_，以減少形成該封裝體之樹脂溢流 此干蔣給 染’造成堆疊接點之電性不良問題。惟如 ==可供設置該銲墊之空間，使得銲墊數目變小， + 干衣件間電性連接之I/O數目減 i之不對不同尺寸、形狀之封裝體，即須使用相對 :不同拉/、，造成製程成本及複雜性之提高，且該封裝 體之形狀祕制可供後續於下層半導體職件堆疊另 導體封裝件之應用。 相對地’如為增加可供上層與下層半導體封裝件間電 連接之1/0數目，即需儘可能增加該銲塾，亦即必須俾 量限縮下料導體縣件之封裝體尺寸，惟如此即無充; 空間可供設置被動元件以改善封裝件電性品質。 再者，請參閱第2圖，如下層半導體封裝件1〇1之封 装體13尺寸相對過小，料致該下層半導體封裝件⑼、 結構強度不佳’而容易發生結構翹曲（赠卿）問題，造成 後續不易在該下層半導體封裝件1〇1上堆疊上層半導體封 裝件102，甚或導致堆疊上層半導體封裝件1〇2時發生提 供該上、下層半導體封裝件1G2，⑻彼此電㈣合:鋒球 14裂損問題。 110127 6 200828458 層堆疊之半半導體封裝件及其製法可避免下 數量與被動元件4牛因：封褒體之設置而限制堆疊鋒墊 °又置、，可乐堆疊銲墊、結構翹曲，以及針 對不同封裝體形狀、 之製#尺寸須準備不同對應生產模具所產生 之課i 度增加等問題，實已成為目前亟欲解決 【發明内容】 鑒於以上所述習知技術之缺點 於提供-種半導““之主要目的在 知下声本墓 、衣 /、2法與堆疊結構，以避免習 問題褒件因封裝體之設置而限制堆疊銲墊數量 制 纟月之$目的在於提供一種半導體封裝件及其 二=疊：構，以避免習知下層半導體封裝件因封裝體 I °又置而 >可染堆疊銲墊問題。 ，發明之又-目的在於提供—種半導體縣件及其 兵堆$結構’以避免習知下層半導體縣件因封裝體 尺寸過小所導致之結構翹曲問題。 本發明之再—目的在於提供—種何體封裝件及並 製法與堆疊結構，可有歧置㈣元件，以卜 性品質。 衣仟电 、本發明之復一目的在於提供一種半導體封裝件及其 製法與堆疊結構，僅使用單—模具即可完成晶片封裝了俾 可避免習知下層半導體封裝件中針對不同封裝體形狀、尺 寸須準備不同生產模具所產生之製程㈣及複雜度增 110127 7 200828458 加等問題。 為達成上揭及其他目的，本發明之半導體封裝件之製 法係包括：提供一具複數基板之基板模組片，各該基板之 表面設有一晶片接置區及複數堆疊鮮墊；於該基板堆疊銲 ，上接置導電凸塊及於該晶片接置區上接置並電性連接^ 導，晶片’·進行封裝製程，以於基板模組片上形成包覆該 半導體晶片及導電凸塊之封裝體，並使該導電凸塊之端： 外露出該封襄體頂自；以及沿各該基板間進行切割作業， 以形成複數封裝體頂面外露有導電凸塊端部之半導體封裝 、另卜於D亥基板上復可接置並電性連接複數被動元件， 、σ封衣件电性品質。該基板可為薄型球柵陣列 (TFBGA)基板或平面栅格陣列（Land Grid Array ; LGA)基 板。 土 ^半導體封裝件於進行封裝製料，係可先於該基板 ' 上开/成王面包覆該半導體晶片及導電凸塊之封枣 接著進行薄化作業，以移除部分封裝體而使該導電凸 塊端部外露出該封裝體頂面。另外亦可 =封裝製程時，將該接置有半導體晶片及導電凸^ 片置於—封裝模具之模穴中，其中該模穴之頂面 設有—薄膜層’並使該模穴頂面之薄膜層壓抵於 :包覆4ΓΓ接著於該模穴中填充封裝樹脂，藉以形 模具封裝艘;之後即移除該 體。帽層猎以直接使该導電凸塊端部外露出該封裝 110127 8 200828458 透過iy述製法，本發明復揭示一種半導體封裝件，係 包括：基板，該基板表面設有一晶片接置區及複數堆疊銲 塾，半導體晶片，係接置於該晶片接置區且電性連接至該 基板，電凸塊，係接置於該堆疊銲墊上；以及封裝體， 係形成於該基板上且包覆該半導體晶月及導電凸塊，並使 =導電凸塊端部外露出該封裝體頂面。另外，於該基板上 4c 了接置並電性連接複數被動元件，以改善封裝件口 質。 。口 本發明亦揭示一種半導體封裝件堆疊結構，係包括有 一下層半導體封裝件；以及一上層半導體封裝件，係堆疊 並電性連接於該下層半導體封裝件上，其中，該下層半$ 體封裝件係包括表面設有一晶片接置區及複數堆疊銲墊之 基板、接置於該晶片接置區且電性連接至該基板之半導體 晶片、接置於該堆疊鮮墊之導電凸塊、以及形成於該基板 ^以包覆該半導體晶片及導電凸塊之封裝體，該導電凸塊 端^係外路於該封裝體頂φ，以供該上層半導體封褒件藉 由妓數導電元件而接置並電性連接至該下層半導體封裝件 所外露出該封裝體頂面之導電凸塊端部。 因此，本發明之半導體封裝件及其製法與堆疊結構， j供-具複數基板之基板模組片，各該基板之表面設有 曰1曰2接置區及複數堆疊銲墊，以於該基板堆疊銲墊上接 導电凸塊及於该晶片接置區上接置並電性連接半導體晶 2接著進行封裝製程，以於基板模組片上形成包覆該: 晶片及導電凸塊之封裝體，並使該導電凸塊之端部外 9 110127 200828458 露出該封裝體頂面，之後即可沿各該基板間進 .二：形成複數㈣頂面外露有導電凸塊端部之G體 桩=u供其匕半導體封震件得以透過複數 而 接置並電性連接至該半導體封褒件所外露 之導電凸塊端部。 对衣體頂面 如此即可避免f知半導體封裝件堆疊結構中 半導體封裝件中所包覆半導體曰 層 ._ 粒日日片之封裝體高度受限於和 C度所造成產品信賴性不佳、溢流至銲塾而發生污毕: 或為免鮮墊污染而縮限可供設置鮮整之空間，造成所堆二 t導體封裝件間電性連接之"ο數目減少問題，亦或Γ 乓加半導體封裝件間電性連接之工 : 體封裝件之封裝體限_下層+導 件及容易發生翻曲等門題1：；間可供設置被動元 可製得本發明利用單一封裝模具即 費用及複雜度肢封叙件及其堆疊結構，以降低製程 、【實施方式】 式，古由特定的具體實施例說明本發明之實施方 :解t=T人士可由本說明書所揭示之内容輕易地 =~本夯明之其他優點與功效。 請參閱第3A至3F F1，& & 4« β a制— 主祀圖，係為本發明之半導體封裝件及 ^衣法弟一貫施例之示意圖。 31Α 圖所7F，提供—具複數基板31之基板模組片 μ 土板3〗之表面設有一晶片接置區311及複數堆 110127 10 200828458 疊銲塾312。該基板可為薄型球柵陣列（tfbga)基板或平 面栅格陣列（Land Grid Array ; LGA、耸知拉 如㈣圖所示’於該基板塾312上接置 導電凸塊32,以及於該晶片接置區311上接置並電 半導體晶UG，其中該導電凸塊32係例如為銲錫凸塊， 且該+導體W 30係可以打線方式電性連接至該基板 ，另於該基板3U復可充分接置有如電容器、電阻器或 電感器等複數被動元件3 5。 如第3C及3D ®所示’進行封裝製程，首先於該基 模組片31A_h形成全面包覆該半導體晶片3〇、被動元； 35及導電凸塊32之封裝體33。 接著透過如研磨之薄化作業，以移除封裝體33頂部， 以使該導電凸塊32端部與該封裝體33頂面齊平，進而使 该導電凸塊32端部外露出該封裝體33。 如第3E圖所示，、沿各該基板3 j @進行切割作業，以 形成複數封裝體33頂面外露有導電凸塊32端部之薄型球 柵陣列（TFBGA)或平面栅格陣列（Land Gdd Arr吖；lga) 半導體封裝件，其中該封裝體33與基板31侧邊係相 平0 透過前述製法，本發明復揭示一種半導體封裝件，係 包括·基板31，該基板31表面設有一晶片接置區3ιι及 複數堆疊銲墊312;半導體晶片3〇,係接置於該晶片接置 區311且電性連接至該基板31 ;導電凸塊32 ，係接置於 忒堆宜釦墊312上；以及封裝體33，係形成於該基板3 j 11 110127 200828458 上以包覆該半導體晶片3〇及導電凸塊32，並使該導電凸 塊32端部外露出該封裝體33頂面。另外，於該基板3ι 上復可接置並電性連接複數被動元件35，以改善封裝件 性品質。 电 再者，由於本發明之半導體封裝件係在該基板31上 王面形成一包覆半導體晶片3〇及導電凸塊32(惟外露出導 電凸塊端部）之TFBGA或LGA封裝體％，其結構均衡可 有效防止㈣問題產生，亦不致發生如習知技術之堆疊鲜 墊叉封裝樹脂污染及封裝體尺寸限制問題。 篇二實施例 、凊芩閱第4A至4C圖，係為本發明之半導體封裝件製 法第二實施例之示意圖。 如4A圖所示，本實施例之製法主要與前述實施例大 致相同，首先係提供—純數基板41之基板额片ΜΑ , 以於各該基板41上接置並電性連接半導體晶# 4〇、被動 凡件45及導電凸塊42’並將該接置有半導體晶片仙、被 動〜件4」及‘ i凸塊42之基板模組片4ia置於—封裝模 二二6之核八460中，其中該模穴46〇之頂面係預先敷設有 4膜層47，如為聚亞醯胺(p〇lyimide)膠#，並使該敷設 於：穴楊頂面之薄膜層47壓抵於該導電凸塊42端部， 於該模八460中填充封裝樹脂，藉以形成包覆該半導 晶片40、被動元件45及導電凸塊42之封裝體43。 如第4B圖所示，接著移除該模具46及薄膜層47，以 供該導電凸塊42端部直接外露出該封裝體43。 110127 12 200828458 • 如第4C圖所示’沿各該基板w間進行200828458 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a stacking structure for a plurality of packages for a plurality of package structures. [Prior Art] The conductor package and its manufacturing method, especially the semiconductor package of a ® and its manufacturing method and the well-being of the well, still require an increase in performance and processing speed. The preferred method of increasing the performance and processing speed is nothing more than increasing the number or size of the wafers in the semiconductor, but the area of the substrate on the substrate for the wafer is often not available for a plurality of crystals. Large size wafers? Place. Therefore, the current development is a stacked multi-package module (paekage(10)^e POP) 〇&, which is stacked on top of a plurality of packages, and a yellow semi-conductive package is disclosed in U.S. Patent No. 5,222,014. The POP stack structure of the POP stack is provided with a plurality of stack 4: a ball grid array (7) GA substrate 7 of a stacked pad 110, to connect the semiconductor wafer 1 on the substrate 11 and form a cladding The package body 13 of the semiconductor wafer 10 is formed to form the lower semiconductor package 1〇1, and then a completed package upper semiconductor package 1〇2 is connected through the solder ball 14 and electrically connected to the lower semiconductor package 1 The stacked solder fillet 110 on the surface of the substrate of the substrate 1 is formed to form a POP stack structure of a semiconductor package. However, since the upper semiconductor package and the lower semiconductor package are electrically connected by solder ball reflow, the height H of the solder ball is generally 〇5 mm, which will limit the height of the package of the lower semiconductor package. 5 110127 200828458 : Wide i: the height H of the solder ball, that is, the height h of the package is normally about the connection::, however, the height of the package is too low, which affects the quality of the wire used for == wire bonding. The T-layer half (four) difficult piece of the package is recently soldered to the second:: Γ.25_, in order to reduce the resin overflow forming the package, which causes the electrical connection problem of the stacked contacts. However, if == the space of the pad can be set, the number of pads becomes smaller, and the number of I/Os that are electrically connected between the clothes pieces is less than that of different sizes and shapes, that is, the relative: Different pull/, resulting in an increase in process cost and complexity, and the shape of the package is secreted for subsequent application of the lower semiconductor package to another conductor package. Relatively, if the number of 1/0 of the electrical connection between the upper and lower semiconductor packages is increased, the solder fillet needs to be increased as much as possible, that is, the package size of the blank conductor is limited. This is no charge; space can be used to set passive components to improve the electrical quality of the package. Furthermore, referring to FIG. 2, the package 13 of the semiconductor package 1〇1 of the following layer is relatively small in size, so that the underlying semiconductor package (9) has poor structural strength and is prone to structural warpage. Therefore, it is difficult to subsequently stack the upper semiconductor package 102 on the lower semiconductor package 1〇1, or even to cause the upper and lower semiconductor packages 1G2 to be stacked when the upper semiconductor package is stacked, and (8) electrically (four) Ball 14 cracking problem. 110127 6 200828458 Layer-stacked semi-semiconductor package and its manufacturing method can avoid the number of passive components and the passive components 4: the setting of the sealing body limits the stacking of the front pad, the Coke stacking pad, the structure warping, and Different package shapes, and the size of the package must be prepared in accordance with the problem of the increase in the degree of the class produced by the corresponding production molds, which has become the current solution. [Invention] In view of the above-mentioned shortcomings of the prior art, "The main purpose of the guide is to know the sound of the tomb, clothing /, 2 methods and stacking structure to avoid the problem of the problem. The number of stacked pads is limited by the setting of the package. The purpose of the month is to provide a semiconductor package. The device and its two-stack structure are used to avoid the problem that the underlying semiconductor package can be dyed by the package I°. Inventively, the objective is to provide a semiconductor device and its munitions $ structure to avoid the problem of structural warpage caused by the undersized semiconductor package being too small. A further object of the present invention is to provide a package of the body, a method of combining and stacking the structure, and to have a disparate (four) component for quality. A further object of the present invention is to provide a semiconductor package, a method of manufacturing the same, and a stacked structure, which can be completed by using only a single mold, and can avoid the shape of different packages in the conventional underlying semiconductor package. The size must be prepared for the production process of different production molds (4) and the complexity is increased by 110127 7 200828458 plus other issues. In order to achieve the above and other objects, the method for manufacturing a semiconductor package of the present invention includes: providing a substrate module of a plurality of substrates, each of the substrate having a wafer connection region and a plurality of stacked fresh pads; Stacking soldering, connecting the conductive bumps on the upper surface of the wafer mounting region and electrically connecting the wafers, and performing a packaging process to form the semiconductor wafer and the conductive bumps on the substrate module sheet a package body, and the end of the conductive bump: externally exposing the top of the sealing body; and performing a cutting operation between the substrates to form a semiconductor package having a top surface of the plurality of packages exposed with conductive bump ends, and Bu can be connected to the D-Hui substrate and electrically connected to a plurality of passive components, and the electrical quality of the σ-sealing member. The substrate can be a thin ball grid array (TFBGA) substrate or a planar grid array (LGA) substrate. The semiconductor package can be packaged and formed by pre-opening/finishing the semiconductor wafer and the conductive bumps on the substrate and then thinning to remove part of the package. The top end of the conductive bump exposes the top surface of the package. In addition, when the package process is performed, the semiconductor wafer and the conductive bump are placed in a cavity of the package mold, wherein the top surface of the cavity is provided with a film layer and the top surface of the cavity The film is laminated to: a cover 4, and then the encapsulating resin is filled in the cavity, whereby the mold is packaged; then the body is removed. The present invention discloses a semiconductor package comprising a substrate having a wafer connection region and a plurality of stacked layers. The semiconductor package is disclosed in the present invention. a solder bump, a semiconductor wafer, is electrically connected to the wafer connection region and electrically connected to the substrate, and the electrical bump is electrically connected to the stacked pad; and the package is formed on the substrate and coated The semiconductor crystal and the conductive bumps cause the outer end of the conductive bump to be exposed to the top surface of the package. In addition, a plurality of passive components are connected and electrically connected to the substrate 4c to improve the quality of the package. . The present invention also discloses a semiconductor package stack structure including a lower semiconductor package; and an upper semiconductor package stacked and electrically connected to the lower semiconductor package, wherein the lower half package The invention comprises a substrate having a wafer connection region and a plurality of stacked pads on the surface, a semiconductor wafer disposed in the wafer connection region and electrically connected to the substrate, conductive bumps disposed on the stacked fresh pad, and forming The substrate is coated with a package body of the semiconductor wafer and the conductive bump, and the conductive bump end is externally connected to the top φ of the package, so that the upper semiconductor package is connected by the plurality of conductive elements And electrically connecting to the end of the conductive bump of the top surface of the package exposed to the underlying semiconductor package. Therefore, the semiconductor package of the present invention, the manufacturing method and the stacked structure thereof, the substrate module of the plurality of substrates, the surface of each of the substrates is provided with a 接1曰2 connection region and a plurality of stacked pads for Forming a conductive bump on the substrate stacking pad and connecting and electrically connecting the semiconductor crystal 2 to the wafer mounting region, and then performing a packaging process to form a package covering the wafer and the conductive bump on the substrate module sheet And exposing the outer surface of the conductive bump 9 110127 200828458 to the top surface of the package, and then entering between the substrates. 2: forming a plurality of (four) top surface exposed G body piles with conductive bump ends = The semiconductor semiconductor sealing member is connected through the plurality of electrodes and electrically connected to the end of the conductive bump exposed by the semiconductor sealing member. The top surface of the body can avoid the semiconductor layer covered in the semiconductor package in the semiconductor package stack structure. _ The height of the package of the chip is limited by the reliability of the product caused by C degree. , overflowing to the soldering iron and causing the contamination: or to reduce the pollution of the fresh pad to provide a space for fresh space, resulting in a reduction in the number of electrical connections between the two t-conductor packages, or电 Pong plus semiconductor package electrical connection: body package package limit _ lower layer + guide and easy to turn over the door 1 :; can be set to passive elements can be made to use the invention in a single package The mold is the cost and complexity of the limb seal description and its stack structure, in order to reduce the process, the [embodiment], the specific embodiment of the present invention illustrates the implementation of the present invention: the solution t = T can be disclosed by the present specification The content is easily == other advantages and effects of this book. Please refer to the 3A to 3F F1, && 4« β a system - the main diagram, which is a schematic diagram of the semiconductor package of the present invention and the consistent application of the method. 31F, FIG. 7F, providing a substrate module piece having a plurality of substrates 31, a surface of the earth plate 3 is provided with a wafer connection region 311 and a plurality of stacks 110127 10 200828458. The substrate may be a thin ball grid array (tfbga) substrate or a planar grid array (Land Grid Array; LGA, as shown in FIG. 4), the conductive bumps 32 are attached to the substrate 312, and the wafer is mounted on the substrate. A semiconductor chip UG is connected to the connection region 311, wherein the conductive bump 32 is, for example, a solder bump, and the +-conductor W 30 can be electrically connected to the substrate in a wire bonding manner, and the substrate 3U can be reconfigured. Fully connected with a plurality of passive components such as capacitors, resistors or inductors. 3 5. As shown in the 3C and 3D ® 'packaging process, firstly, the base die 31A_h is formed to completely cover the semiconductor wafer. 35 and the package 33 of the conductive bump 32. Then, through the thinning operation such as grinding, the top of the package 33 is removed, so that the end of the conductive bump 32 is flush with the top surface of the package 33, thereby The end portion of the conductive bump 32 is exposed to the package body 33. As shown in FIG. 3E, a cutting operation is performed along each of the substrates 3 j @ to form a top surface of the plurality of package bodies 33 with exposed ends of the conductive bumps 32 Thin Ball Grid Array (TFBGA) or Planar Grid Array (Land Gdd) The semiconductor package, wherein the package 33 is flush with the side of the substrate 31. The semiconductor package includes a substrate 31 having a wafer on the surface of the substrate 31. And a plurality of stacked pads 312; the semiconductor wafer 3 is electrically connected to the wafer connection region 311 and electrically connected to the substrate 31; and the conductive bumps 32 are connected to the stack 312. And a package body 33 formed on the substrate 3 j 11 110127 200828458 to cover the semiconductor wafer 3 and the conductive bump 32, and expose the end of the conductive bump 32 to the top surface of the package 33. The plurality of passive components 35 are electrically connected to the substrate 3 to improve the package quality. Further, since the semiconductor package of the present invention forms a coated semiconductor on the substrate 31 The TFBGA or LGA package % of the wafer 3 turns and the conductive bumps 32 (except only the ends of the conductive bumps are exposed), and the structural balance thereof can effectively prevent the (4) problem from occurring, and does not cause the stacked fresh pad fork encapsulating resin as in the prior art. Pollution and package dimensions The second embodiment of the semiconductor package manufacturing method of the present invention is a schematic view of the second embodiment of the semiconductor package manufacturing method of the present invention. As shown in FIG. 4A, the manufacturing method of the present embodiment is mainly the same as the foregoing embodiment. In the same manner, firstly, the substrate wafer ΜΑ of the pure substrate 41 is provided, so that the semiconductor crystal 41, the passive device 45 and the conductive bump 42 ′ are connected and electrically connected to each of the substrates 41 and the connection is performed. The substrate module piece 4ia of the semiconductor chip, the passive piece 4" and the 'i bump 42" is placed in the core 460 of the package module 22, wherein the top surface of the cavity 46 is pre-applied 4 The film layer 47 is, for example, a polyplyimide gel, and the film layer 47 applied to the top surface of the hole is pressed against the end of the conductive bump 42 and filled in the die 460 The resin is encapsulated to form a package 43 covering the semiconductor wafer 40, the passive component 45, and the conductive bumps 42. As shown in Fig. 4B, the mold 46 and the film layer 47 are then removed, so that the end of the conductive bump 42 directly exposes the package body 43. 110127 12 200828458 • As shown in Figure 4C, 'between each substrate w
，形成複數封裝體43頂面外露有導電凸塊42端=乍=以 或LGA半導體封裝件。 BGAThe top surface of the plurality of packages 43 is formed with a conductive bump 42 end = 乍 = or LGA semiconductor package. BGA
第三實施H 請參閱第5圖，係為本發明之半導體封 例之剖面示意圖。 干弟一貝轭 如圖所示，本實施例之半導體封裝件與前 相同，主要差異在於半導體晶片50除可透過前广^ 電性連接至該基板外，亦可以覆曰 /述打線方式 板51。 』以復日日方式而電性連接至該基 社構Si閱：6圖’係顯示本發明之半導體封裝件堆疊 4之剖面示意圖’主要係將前述之咖 乍為堆疊結構中之下層半導體封裝件，以二I 、’书性連接其它半導體縣件， 堆疊結構。 人丁〒紅玎衣仟 該Λ導^封料堆疊結構係包財：—下層TF驗 二雄封t件6G1;以及—上層半導體封裝件602， ’、且二书性連接於該下層半導體封裝件001上，其中， =下層、半導體，件6G1係包括表㈣有—晶片接置區 及複數堆宜！于塾612之基板61、接置於該晶片接置區 電性連接至該基板61之半導體w接置於該堆 豐在干塾612之導雷jtlm 凸塊62、以及形成於該基板61上以包 =該半導體晶片6〇及導電凸塊62之封裝體63，該導電凸 塊62端部外露出該封裳體幻頂面，以供該上層半導體封 110127 13 200828458 ，裝件602藉由複數如銲球之導電元件64而接置並電性連接 .至該下層半導體封裝件601所外露出該封裝體63頂面之導 電凸塊62端部。 、 、 /因此’本發明之半導體封裝件及其製法與堆疊結構， 係提供-具複數基板之基板模組片，各該基板之表面設有 -晶片接置區及複數堆疊銲塾，以於該基板堆叠銲塾上接 置導電凸塊及於該晶片接置區上接置並電性連接半導體曰 :i體?裝製程，以於基板模組片上形成包覆“ =曰曰片及導電凸塊之封裝體，並使該導電凸塊之端部外 路出該封裝體頂面，之後即可沿各該基板間進行切巧作 ，，以形成複數封裝體頂面外露有導電凸塊端部之咖以 ^ LGA+導體封裝件，以供其它半㈣ 數導電元件而接置並電性連接至該半導趙封裝二= 該封裝體頂面之導電凸塊端部。 半導卩可避免習知半導體封裝件堆疊結構中，因下声 str;封裝件中所包覆半導體晶片之封震體高度受限 =度所造成產品信賴性不佳、溢流至銲墊而發生# 或為免銲墊污染而縮限可供 :所:’ 件間電性連接之1/0數目減少問題 二間電性連接之1/0數目，限縮下層ΐΐ Ί 體尺寸’造成無充足空' 件及容易發生或又置被動兀Third Embodiment H Referring to Figure 5, there is shown a cross-sectional view of a semiconductor package of the present invention. As shown in the figure, the semiconductor package of the present embodiment is the same as before, the main difference is that the semiconductor wafer 50 can be connected to the substrate in addition to being permeable to the substrate, and the wiring pattern can also be covered. 51. </ RTI> </ RTI> is electrically connected to the basic structure of the system. Figure 6 shows a schematic cross-sectional view of the semiconductor package stack 4 of the present invention. The main reason is to use the aforementioned curry as the underlying semiconductor package in the stacked structure. Pieces, with two I, 'books connected to other semiconductor county pieces, stacked structure. The 堆叠 〒 〒 玎 仟 仟 仟 ^ ^ ^ ^ 封 封 封 封 封 封 封 封 封 封 封 封 封 封 封 封 封 封 封 封 封 封 封 封 封 封 封 TF TF TF TF TF TF TF TF TF TF TF TF TF TF TF TF On piece 001, where = lower layer, semiconductor, piece 6G1 system includes table (four) with - wafer connection area and multiple stacks! a substrate 61 disposed on the substrate 612, and a semiconductor w electrically connected to the substrate 61 in the wafer connection region are disposed on the pillared jtlm bump 62 of the stack 612, and formed on the substrate 61 The package body 63 of the semiconductor wafer 6 and the conductive bump 62 is exposed at the end of the conductive bump 62 to expose the upper surface of the semiconductor body 110127 13 200828458 by means of the upper layer semiconductor package 110127 13 200828458 A plurality of conductive elements 64, such as solder balls, are connected and electrically connected. The ends of the conductive bumps 62 on the top surface of the package 63 are exposed to the lower semiconductor package 601. And/or the semiconductor package of the present invention, and the method and the stacked structure thereof, are provided with a substrate module sheet having a plurality of substrates, and the surface of each of the substrates is provided with a wafer connection region and a plurality of stacked solder pads for The substrate stacking pad is connected with a conductive bump and is connected to the wafer receiving area and electrically connected to the semiconductor device: a body mounting process to form a coating on the substrate module sheet. a package of the bumps, and the ends of the conductive bumps are out of the top surface of the package, and then can be cut along the substrates to form a conductive bump on the top surface of the plurality of packages. The end of the coffee is in the LGA+ conductor package for the other half (four) number of conductive elements to be connected and electrically connected to the semiconductor package 2 = the end of the conductive bump on the top surface of the package. Avoiding the conventional semiconductor package stack structure, due to the lower sound str; the height of the sealed body of the semiconductor wafer coated in the package is limited=degree of reliability, and the product is not reliable, overflowing to the solder pad occurs# or Free solder pad contamination and limited limit available:: 1/0 of the electrical connection between parts The number reduction problem is the number of 1/0 of the two electrical connections, and the lower limit ΐΐ Ί body size 'causes no sufficient air' and is easy to occur or passive
或LGA封，二，，同時僅需利用單-之TFBGA 叠結構，：^Γ 本發日狀何㈣料及其堆 牛低製程費用及複雜度。 110127 14 200828458 上述之實施例僅用以例示本發明之原理及其功效，而 非用於限定本發明，因此任何熟習此項技藝之人士均可在 不返背本發明之精神及範轉下，對上述實施例進行修舞與 變化，端視實施型態而定。 【圖式簡單說明】 第1圖係為美國專利 導體封裝件之堆疊結構； 第2圖係為習知半導體封裝件之堆疊結構中下層半 體封裝件發生翹曲之示意圖； —第SAME圖係為本發明之半導體封裝件及其製法第 一貫施例之剖面示意圖； 第4A至4C®係為本發明之半導體封裝件 二實 施例之剖面示意圖； 一貝 第5圖係為本發明之半導裝 示意圖；α及 U件弟二貫施例之剖面 疊結構示意圖 第6圖係為本發明之半導體封裳件堆 【主要元件符號說明】 10 半導體晶片 11 基板 110 堆疊銲墊 13 封裝體 14 鮮球 101 下層半導體封裝件 102 上層半導體封裝件 110127 15 200828458 ，30 半導體晶片 -31 基板 31A 基板模組片 311 晶片接置區 312 堆疊銲墊 32 導電凸塊 33 封裝體 35 被動元件 40 半導體晶片 41 基板 41A 基板模組片 42 導電凸塊 43 封裝體 45 被動元件 46 封裝模具 460 模穴 47 薄膜層 50 半導體晶片 51 基板 60 半導體晶片 61 基板 62 導電凸塊 63 封裝體 64 導電元件 200828458 1 601 下層半導體封裝件 ，602 上層半導體封裝件 611 晶片接置區 612 堆疊銲墊 17 110127Or LGA seal, two, at the same time only need to use the single-TFBGA stack structure, : ^ Γ this day shape (four) material and its heap cattle low process cost and complexity. 110 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The above embodiment is practiced and changed, depending on the implementation type. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a stacked structure of a US patented conductor package; FIG. 2 is a schematic view showing warpage of a lower half package in a stacked structure of a conventional semiconductor package; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 4A to FIG. 4C are cross-sectional views showing a second embodiment of a semiconductor package of the present invention; FIG. 5 is a half of the present invention. FIG. 6 is a schematic diagram of a cross-sectional stack structure of a two-part embodiment of α and U. FIG. 6 is a semiconductor package of the present invention. [Main component symbol description] 10 semiconductor wafer 11 substrate 110 stacked pad 13 package 14 Fresh Ball 101 Lower Semiconductor Package 102 Upper Semiconductor Package 110127 15 200828458 , 30 Semiconductor Wafer - 31 Substrate 31A Substrate Module Sheet 311 Wafer Junction Area 312 Stacking Pad 32 Conductive Bump 33 Package 35 Passive Element 40 Semiconductor Wafer 41 Substrate 41A Substrate module sheet 42 Conductive bump 43 Package body 45 Passive element 46 Package mold 460 Cavity 47 Film layer 50 Semiconductor wafer 51 substrate 60 semiconductor wafer 61 substrate 62 conductive bump 63 package 64 conductive element 200828458 1 601 lower semiconductor package, 602 upper semiconductor package 611 wafer contact region 612 stacked pad 17 110127