TW201327769A - Semiconductor package and manufacturing method thereof - Google Patents

Semiconductor package and manufacturing method thereof Download PDF

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Publication number
TW201327769A
TW201327769A TW100148007A TW100148007A TW201327769A TW 201327769 A TW201327769 A TW 201327769A TW 100148007 A TW100148007 A TW 100148007A TW 100148007 A TW100148007 A TW 100148007A TW 201327769 A TW201327769 A TW 201327769A
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substrate
semiconductor
package
disposed
outer side
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TW100148007A
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Chinese (zh)
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Chi-Sheng Chung
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Advanced Semiconductor Eng
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package comprises a semiconductor element, a second substrate, a second semiconductor chip and a second package body. The semiconductor element comprises a first substrate, a first semiconductor chip and a first package body. The first substrate has a first surface and a second surface opposite to the first surface. The first semiconductor chip is disposed on the first surface of the first substrate. The first package body encapsulates the first semiconductor chip. The second substrate has a recess. The semiconductor element is disposed to the corresponding to the second substrate and corresponds to the recess. The second semiconductor chip is disposed to the second surface of the first substrate. The second package body encapsulates the second semiconductor chip and fills the recess of the second substrate.

Description

半導體封裝件及其製造方法Semiconductor package and method of manufacturing same

本發明是有關於一種半導體封裝件及其製造方法，且特別是有關於一種具有晶片堆疊結構之半導體封裝件及其製造方法。The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package having a wafer stack structure and a method of fabricating the same.

隨著科技發展，半導體封裝件的功能也愈來愈強大。傳統半導體封裝件可包括多個晶片，以提供系統型功能。With the development of technology, the function of semiconductor packages is becoming more and more powerful. Conventional semiconductor packages can include multiple wafers to provide system type functionality.

然而，該些晶片多採用邊靠邊(side by side)方式設置，使半導體封裝件的面積尺寸無法有效縮小。為了維持半導體封裝件的小尺寸，只能設限晶片數量，如此便限制導致半導體封裝件所提供的系統功能。However, the wafers are often disposed in a side by side manner, so that the area size of the semiconductor package cannot be effectively reduced. In order to maintain the small size of the semiconductor package, only the number of wafers can be limited, thus limiting the system functions provided by the semiconductor package.

本發明係有關於一種半導體封裝件及其製造方法，具有多個晶片，可提升半導體封裝件的系統功能。The present invention relates to a semiconductor package and a method of fabricating the same, having a plurality of wafers that enhance the system function of the semiconductor package.

根據本發明之一實施例，提出一種半導體封裝件。半導體封裝件包括一半導體元件、一第二基板及一第二半導體晶片。半導體元件包括一第一基板、一第一半導體晶片及一第一封裝體。第一基板具有相對之一第一面與一第二面。第一半導體晶片設於第一基板之第一面上。第一封裝體包覆第一半導體晶片。第二基板具有一凹部，半導體元件對應凹部設於第二基板上。第二半導體晶片設於第一基板之第二面上。第二封裝體包覆半導體元件及第二半導體晶片且填滿第二基板之凹部。According to an embodiment of the invention, a semiconductor package is proposed. The semiconductor package includes a semiconductor component, a second substrate, and a second semiconductor wafer. The semiconductor component includes a first substrate, a first semiconductor wafer, and a first package. The first substrate has a first side and a second side opposite to each other. The first semiconductor wafer is disposed on the first surface of the first substrate. The first package encases the first semiconductor wafer. The second substrate has a recess, and the semiconductor element corresponding recess is disposed on the second substrate. The second semiconductor wafer is disposed on the second surface of the first substrate. The second package encapsulates the semiconductor component and the second semiconductor wafer and fills the recess of the second substrate.

根據本發明之另一實施例，提出一種半導體封裝件的製造方法。製造方法包括以下步驟。提供一半導體元件，其中半導體元件包括一第一基板、一第一半導體晶片及一第一封裝體，第一基板具有相對之一第一面與一第二面，第一半導體晶片設於第一基板之第一面上，而第一封裝體包覆第一半導體晶片；設置半導體元件至一第二基板上，其中第二基板具有一凹部，半導體元件對應凹部設於第二基板上；設置一第二半導體晶片於第一基板之第二面上；形成一第二封裝體包覆半導體元件及第二半導體晶片且填滿第二基板之凹部。According to another embodiment of the present invention, a method of fabricating a semiconductor package is provided. The manufacturing method includes the following steps. Providing a semiconductor device, wherein the semiconductor device includes a first substrate, a first semiconductor wafer, and a first package, the first substrate has a first surface and a second surface, and the first semiconductor wafer is disposed at the first a first surface of the substrate, the first package covers the first semiconductor wafer; the semiconductor element is disposed on a second substrate, wherein the second substrate has a recess, and the corresponding recess of the semiconductor element is disposed on the second substrate; The second semiconductor wafer is on the second surface of the first substrate; a second package is formed to cover the semiconductor element and the second semiconductor wafer and fill the recess of the second substrate.

根據本發明之另一實施例，提出一種半導體封裝件。半導體封裝件包括一半導體元件、一第二基板、一第二覆晶及一封裝體。半導體元件包括一第一基板及一第一覆晶。第一基板具有相對之一第一面與一第二面且電性連接於第二基板。第一覆晶設於第一基板之第一面上。半導體元件設於第二基板上。第二覆晶設於第一基板之第二面上。封裝體包覆半導體元件及第二覆晶。In accordance with another embodiment of the present invention, a semiconductor package is presented. The semiconductor package includes a semiconductor component, a second substrate, a second flip chip, and a package. The semiconductor component includes a first substrate and a first flip chip. The first substrate has a first surface and a second surface opposite to each other and is electrically connected to the second substrate. The first flip chip is disposed on the first surface of the first substrate. The semiconductor component is disposed on the second substrate. The second flip chip is disposed on the second surface of the first substrate. The package covers the semiconductor element and the second flip chip.

為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式，作詳細說明如下：In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

請參照第1A圖，其繪示依照本發明一實施例之半導體封裝件的剖視圖。半導體封裝件100包括半導體元件120、第二基板110、第二半導體晶片130、第二封裝體140、第二屏蔽層160及至少一銲線190。Referring to FIG. 1A, a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention is shown. The semiconductor package 100 includes a semiconductor device 120, a second substrate 110, a second semiconductor wafer 130, a second package 140, a second shield layer 160, and at least one bonding wire 190.

半導體元件120設於第二基板110上且包括第一基板121、第一半導體晶片122、第一封裝體123、至少一銲線124及第一屏蔽層125。The semiconductor device 120 is disposed on the second substrate 110 and includes a first substrate 121 , a first semiconductor wafer 122 , a first package body 123 , at least one bonding wire 124 , and a first shielding layer 125 .

本實施例中，半導體元件120以第一屏蔽層125設於第二基板110。另一實施例中，當第一屏蔽層125被省略時，半導體元件120以第一封裝體123設於第二基板110上。此外，半導體封裝件100更包括黏合件150，半導體元件120透過黏合件150固定於第二基板110上。In this embodiment, the semiconductor device 120 is disposed on the second substrate 110 with the first shielding layer 125. In another embodiment, when the first shielding layer 125 is omitted, the semiconductor device 120 is disposed on the second substrate 110 with the first package body 123. In addition, the semiconductor package 100 further includes an adhesive member 150. The semiconductor device 120 is fixed to the second substrate 110 through the adhesive member 150.

第一基板121具有相對之第一面121b與第二面121u，其中第一面121b朝向第二基板110。本實施例中，第一基板121例如是中介層(interposer)基板，其可包括至少一導通孔1212，例如是矽通孔(through silicon via,TSV)。矽通孔可藉由於第一基板121(例如是矽基板)開設一開孔且以導電材料填入該開孔而形成。然而，本實施例不限於此，只要是可製作導通孔(不限於矽通孔)的基板，皆屬本實施例之第一基板121的範圍。此外，第一基板121的材質可包括玻璃或封膠體，本實施例不限定第一基板121的材質種類。The first substrate 121 has a first surface 121b and a second surface 121u opposite to each other, wherein the first surface 121b faces the second substrate 110. In this embodiment, the first substrate 121 is, for example, an interposer substrate, which may include at least one via hole 1212, such as a through silicon via (TSV). The through hole may be formed by opening a hole in the first substrate 121 (for example, a germanium substrate) and filling the opening with a conductive material. However, the present embodiment is not limited thereto, and any substrate that can form a via hole (not limited to a via hole) is in the range of the first substrate 121 of the present embodiment. In addition, the material of the first substrate 121 may include glass or a sealant, and the material of the first substrate 121 is not limited in this embodiment.

第一基板121包括至少一接地部1211，其中接地部1211從第一基板121之外側面121s露出。接地部1211例如是導電柱(conductive pillar)或圖案化線路層，本實施例係以導電柱為例說明。The first substrate 121 includes at least one ground portion 1211, wherein the ground portion 1211 is exposed from the outer side surface 121s of the first substrate 121. The grounding portion 1211 is, for example, a conductive pillar or a patterned wiring layer. This embodiment is described by taking a conductive pillar as an example.

本實施例中，接地部1211延伸於第一面121b與第二面121u之間。另一實施例中，接地部1211可從第一面121b延伸至第二面121u。再一實施例中，接地部1211可突出超過第一面121b。此外，雖然圖未繪示，然其中一導通孔1212可透過第一基板121的內部結構(如多層線路層)或外部結構(如走線(trace))電性連接於接地部1211。In this embodiment, the grounding portion 1211 extends between the first surface 121b and the second surface 121u. In another embodiment, the ground portion 1211 can extend from the first surface 121b to the second surface 121u. In still another embodiment, the ground portion 1211 can protrude beyond the first surface 121b. In addition, although not shown, one of the via holes 1212 can be electrically connected to the ground portion 1211 through an internal structure of the first substrate 121 (such as a multilayer wiring layer) or an external structure (such as a trace).

第一半導體晶片122可透過黏合件150設於第一基板121之第一面121b上，其中，黏合件150例如黏膠或黏膜，其材質例如是環氧樹脂或其它合適材料。本實施例中，第一半導體晶片122之主動面朝向第二基板110。第一半導體晶片122可透過銲線124電性連接於第一基板121之導通孔1212。此外，第一半導體晶片122例如是射頻(RF)晶片或其它種類晶片。The first semiconductor wafer 122 is disposed on the first surface 121b of the first substrate 121 through the adhesive member 150. The adhesive member 150 is, for example, an adhesive or a mucus, and the material thereof is, for example, epoxy resin or other suitable material. In this embodiment, the active surface of the first semiconductor wafer 122 faces the second substrate 110. The first semiconductor wafer 122 is electrically connected to the via hole 1212 of the first substrate 121 through the bonding wire 124. Further, the first semiconductor wafer 122 is, for example, a radio frequency (RF) wafer or other type of wafer.

第一封裝體123包覆第一半導體晶片122及銲線124。第一封裝體123可包括酚醛基樹脂(Novolac-based resin)、環氧基樹脂(epoxy-based resin)、矽基樹脂(silicone-based resin)或其他適當之包覆劑。第一封裝體123亦可包括適當之填充劑，例如是粉狀之二氧化矽。可利用數種封裝技術形成第一封裝體123，例如是壓縮成型(compression molding)、注射成型(injection molding)或轉注成型(transfer molding)。一實施例中，第一封裝體123係封膠(molding compound)或預浸材疊層(prepreg lamination)。The first package body 123 covers the first semiconductor wafer 122 and the bonding wires 124. The first package 123 may include a Novolac-based resin, an epoxy-based resin, a silicone-based resin, or other suitable coating agents. The first package 123 may also include a suitable filler such as powdered cerium oxide. The first package body 123 can be formed using several packaging techniques, such as compression molding, injection molding, or transfer molding. In one embodiment, the first package body 123 is a molding compound or a prepreg lamination.

銲線124電性連接第一半導體晶片122與第一基板121，例如是連接第一半導體晶片122與第一基板121之導通孔1212。The bonding wire 124 is electrically connected to the first semiconductor wafer 122 and the first substrate 121 , for example, the via hole 1212 connecting the first semiconductor wafer 122 and the first substrate 121 .

第一屏蔽層125覆蓋第一封裝體123之外側面123s、第一基板121的外側面121s及接地部1211從外側面121s露出的側面。藉由第一屏蔽層125的屏蔽，可避免第一半導體晶片122去電磁干擾外部元件或受到外部元件的電磁干擾。另一實施例中，當沒有電磁干擾問題或電磁干擾影響小時，亦可省略第一屏蔽層125。The first shield layer 125 covers the outer side surface 123s of the first package body 123, the outer side surface 121s of the first substrate 121, and the side surface of the ground portion 1211 exposed from the outer side surface 121s. By shielding of the first shielding layer 125, the first semiconductor wafer 122 can be prevented from electromagnetic interference with external components or electromagnetic interference from external components. In another embodiment, the first shielding layer 125 may also be omitted when there is no electromagnetic interference problem or the electromagnetic interference is small.

第一屏蔽層125的材質可選自於鋁、銅、鉻、錫、金、銀、鎳、不銹鋼及其組合所構成的群組。第一屏蔽層125可以是單層或多層結構。以多層結構為例，第一屏蔽層125係三層結構，其內層係不銹鋼層、中間層係銅層，而外層係不銹鋼層；或者，第一屏蔽層125係雙層結構，其內層係銅層，而其外層係不銹鋼層。The material of the first shielding layer 125 may be selected from the group consisting of aluminum, copper, chromium, tin, gold, silver, nickel, stainless steel, and combinations thereof. The first shield layer 125 may be a single layer or a multilayer structure. Taking the multilayer structure as an example, the first shielding layer 125 is a three-layer structure, the inner layer is a stainless steel layer, the intermediate layer is a copper layer, and the outer layer is a stainless steel layer; or the first shielding layer 125 is a two-layer structure, and the inner layer thereof It is a copper layer and its outer layer is a stainless steel layer.

第二基板110具有凹部110r及相對之第一面110u與第二面110b，凹部110r延伸至第一面110u。上述半導體元件120對應凹部110r設於第二基板110上。The second substrate 110 has a recess 110r and an opposite first surface 110u and a second surface 110b, and the recess 110r extends to the first surface 110u. The semiconductor element 120 is disposed on the second substrate 110 corresponding to the recess 110r.

本實施例中，第二基板110包括至少一第一接墊113、至少一第二接墊170及至少一接地部111，其中接地部111從第二基板110之外側面110s露出。接地部111例如是導電柱或圖案化線路層，本實施例係以導電柱為例說明。In this embodiment, the second substrate 110 includes at least one first pad 113, at least one second pad 170, and at least one ground portion 111, wherein the ground portion 111 is exposed from the outer surface 110s of the second substrate 110. The grounding portion 111 is, for example, a conductive pillar or a patterned wiring layer. This embodiment is described by taking a conductive pillar as an example.

本實施例中，接地部111延伸於第二基板110之第一面110u與第二面110b之間。另一實施例中，接地部111可從第二基板110之第一面110u延伸至第二面110b。再一實施例中，接地部111可突出超過第二基板110之第一面110u。In this embodiment, the grounding portion 111 extends between the first surface 110u and the second surface 110b of the second substrate 110. In another embodiment, the grounding portion 111 can extend from the first surface 110u of the second substrate 110 to the second surface 110b. In still another embodiment, the grounding portion 111 can protrude beyond the first surface 110u of the second substrate 110.

該些第一接墊113之一者係一第一接地接墊113g，而該些第二接地接墊170之一者係一第二接地接墊170g，其中第一接地接墊113g透過第二基板110的內部結構(如多層線路層)或外部結構(如走線(trace))電性連接於接地部111及第二接地接墊170g。One of the first pads 113 is a first ground pad 113g, and one of the second ground pads 170 is a second ground pad 170g, wherein the first ground pad 113g passes through the second The internal structure of the substrate 110 (such as a multilayer wiring layer) or an external structure (such as a trace) is electrically connected to the ground portion 111 and the second ground pad 170g.

第二基板110之該些第二接墊170形成於第二基板110之第二面110b，使半導體封裝件100成為一平面閘格陣列(Land Grid Array,LGA)結構。其中，第二接地接墊170g可連接至一外部電路元件(如電路板)的接地端(未繪示)。另一實施例中，半導體封裝件100更包括至少一銲球，其對應地形成於第二接墊170上，使半導體封裝件100成為一球柵陣列(Ball Grid Array,BGA)結構。The second pads 170 of the second substrate 110 are formed on the second surface 110b of the second substrate 110 to make the semiconductor package 100 a Land Grid Array (LGA) structure. The second ground pad 170g can be connected to a ground end (not shown) of an external circuit component (such as a circuit board). In another embodiment, the semiconductor package 100 further includes at least one solder ball, which is correspondingly formed on the second pad 170, so that the semiconductor package 100 is a Ball Grid Array (BGA) structure.

第二半導體晶片130可透過黏合件150設於第一基板121之第二面121u上。本實施例中，第二半導體晶片130係以主動面朝上(face-up)方位設於第一基板121上，銲線124電性連接第二半導體晶片130與第一基板121。此外，第二半導體晶片130例如是射頻晶片或其它種類晶片。The second semiconductor wafer 130 is disposed on the second surface 121u of the first substrate 121 through the adhesive member 150. In this embodiment, the second semiconductor wafer 130 is disposed on the first substrate 121 in an active face-up orientation, and the bonding wires 124 are electrically connected to the second semiconductor wafer 130 and the first substrate 121. Further, the second semiconductor wafer 130 is, for example, a radio frequency wafer or other kind of wafer.

本實施例中，第一基板121的相對二面皆設置有第二半導體晶片130及第一半導體晶片122(第二半導體晶片130與第一半導體晶片122形同堆疊結構)，使半導體封裝件100可配置的晶片數量增加，以提升半導體封裝件100的系統功能。此外，另一實施例中，多個第一半導體晶片122可配置於第一基板121的第一面121b且/或多個第二半導體晶片130可配置於第一基板121的第二面121u。當多個晶片配置於第一基板121上時，該些晶片可沿第一基板121的延伸方向(邊靠邊)的方式配置或沿第一基板121的厚度方向(上下堆疊)的方式配置。In this embodiment, the second semiconductor wafer 130 and the first semiconductor wafer 122 (the second semiconductor wafer 130 and the first semiconductor wafer 122 are in the same stacked structure) are disposed on opposite sides of the first substrate 121 to make the semiconductor package 100 The number of configurable wafers is increased to enhance the system function of the semiconductor package 100. In addition, in another embodiment, the plurality of first semiconductor wafers 122 may be disposed on the first surface 121 b of the first substrate 121 and/or the plurality of second semiconductor wafers 130 may be disposed on the second surface 121 u of the first substrate 121 . When a plurality of wafers are disposed on the first substrate 121, the wafers may be disposed along the extending direction (edges) of the first substrate 121 or in the thickness direction of the first substrate 121 (up and down stacking).

第二封裝體140包覆半導體元件120、第二半導體晶片130、銲線124及190且填滿第二基板110之凹部110r。此外，第二封裝體140的材質可相似於第一封裝體123，容此不再贅述。The second package body 140 covers the semiconductor element 120, the second semiconductor wafer 130, the bonding wires 124 and 190, and fills the recess 110r of the second substrate 110. In addition, the material of the second package body 140 can be similar to the first package body 123, and details are not described herein again.

由於第二封裝體140之一部分填滿凹部110r，且完整地覆蓋半導體元件120之下表面與凹部110r之底面，可提升半導體元件120與第二基板110的結合性。進一步地說，由於第二基板110的翹曲(例如，在任何加熱製程中，第二基板110因熱變形而翹曲)，使半導體元件120之下表面與第二基板110之上表面110u無法完整地接觸，如此第二封裝體140不易填滿半導體元件120之下表面與第二基板110之上表面110u之間的空隙，因此也無法達到穩固結合半導體元件120與第二基板110的功效。反觀本實施例，藉由凹部110r設計，可明顯改善此一問題。Since one of the second packages 140 partially fills the recess 110r and completely covers the lower surface of the semiconductor element 120 and the bottom surface of the recess 110r, the bonding of the semiconductor element 120 to the second substrate 110 can be improved. Further, due to the warpage of the second substrate 110 (for example, the second substrate 110 is warped due to thermal deformation in any heating process), the lower surface of the semiconductor element 120 and the upper surface 110u of the second substrate 110 cannot be made. In complete contact, the second package body 140 does not easily fill the gap between the lower surface of the semiconductor device 120 and the upper surface 110u of the second substrate 110, and thus the effect of firmly bonding the semiconductor device 120 and the second substrate 110 cannot be achieved. In contrast to the present embodiment, this problem can be significantly improved by the design of the recess 110r.

此外，封裝體140具有外側面140s，封裝體140之外側面140s與第二基板110之外側面110s實質上對齊，例如是共面。另一實施例中，封裝體140之外側面140s與第二基板110之外側面110s相隔一距離，在此情況下，第二屏蔽層160仍可覆蓋接地部111。In addition, the package body 140 has an outer side surface 140s, and the outer side surface 140s of the package body 140 is substantially aligned with the outer side surface 110s of the second substrate 110, for example, coplanar. In another embodiment, the outer side surface 140s of the package body 140 is spaced apart from the outer side surface 110s of the second substrate 110. In this case, the second shielding layer 160 can still cover the ground portion 111.

本實施例中，第二屏蔽層160覆蓋第二封裝體140之外側面140s、第二基板110之外側面110s及接地部111從外側面110s露出之外側面。藉由第二屏蔽層160的屏蔽，可避免第二半導體晶片130電磁干擾外部元件或受到外部元件的電磁干擾。另一實施例中，當沒有電磁干擾或電磁干擾影響小時，可省略第二屏蔽層160。此外，第二屏蔽層160的材質及結構可相似於第一屏蔽層125，容此不再贅述。In this embodiment, the second shielding layer 160 covers the outer surface 140s of the second package 140, the outer surface 110s of the second substrate 110, and the outer surface of the ground portion 111 exposed from the outer surface 110s. By shielding of the second shielding layer 160, the second semiconductor wafer 130 can be prevented from electromagnetically interfering with or being electromagnetically disturbed by external components. In another embodiment, the second shield layer 160 may be omitted when there is no electromagnetic interference or electromagnetic interference. In addition, the material and structure of the second shielding layer 160 may be similar to the first shielding layer 125, and details are not described herein again.

銲線190電性連接於第一基板121與第二基板110。上述半導體元件120之第一屏蔽層125可透過第一基板121、銲線190及第二基板110電性連接於一接地端。本實施例中，銲線190可連接第一基板121之導通孔1212與第二基板110之接地接墊113g，使上述第一屏蔽層125可依序透過第一基板121之接地部1211、導通孔1212、銲線190、第二基板110之接地接墊113g、接地部111及接地接墊170g電性連接於一接地端，此接地端例如是外部電路板的接地。The bonding wire 190 is electrically connected to the first substrate 121 and the second substrate 110. The first shielding layer 125 of the semiconductor device 120 is electrically connected to the ground via the first substrate 121, the bonding wires 190, and the second substrate 110. In this embodiment, the bonding wire 190 can be connected to the via hole 1212 of the first substrate 121 and the ground pad 113g of the second substrate 110, so that the first shielding layer 125 can be sequentially transmitted through the grounding portion 1211 of the first substrate 121. The hole 1212, the bonding wire 190, the grounding pad 113g of the second substrate 110, the grounding portion 111 and the grounding pad 170g are electrically connected to a grounding end, such as a grounding of an external circuit board.

請參照第1B圖，其繪示第1A圖之俯視圖(未繪示第二屏蔽層160及第二封裝體140)。第二基板110包括至少一承載部112，承載部112對應凹部110r之轉角。半導體元件120設於承載部112上，本實施例中，半導體元件120設於四個承載部112上。另一實施例中，第二基板110可省略呈對角配置的二個承載部112，半導體元件120可設於另二個呈對角配置的承載部112上。其它實施例中，承載部112可對應凹部110r之轉角以外的區域。Please refer to FIG. 1B , which illustrates a top view of FIG. 1A (the second shielding layer 160 and the second package 140 are not shown). The second substrate 110 includes at least one carrying portion 112 corresponding to the corner of the recess 110r. The semiconductor device 120 is disposed on the carrying portion 112. In this embodiment, the semiconductor device 120 is disposed on the four carrying portions 112. In another embodiment, the second substrate 110 may omit the two carrying portions 112 disposed diagonally, and the semiconductor element 120 may be disposed on the other two of the carrying portions 112 disposed diagonally. In other embodiments, the carrier portion 112 may correspond to a region other than the corner of the recess 110r.

如第1B圖所示，半導體元件120與凹部110r之四邊的內側壁110w相隔一間距，如此一來，在形成第二封裝體140的製程中，呈流動態的第二封裝體140可經由半導體元件120與凹部110r之內側壁110w之間的空間填入凹部110r。填入凹部110r的第二封裝體140可發揮支撐半導體元件120的作用。As shown in FIG. 1B, the semiconductor device 120 is spaced apart from the inner sidewall 110w of the four sides of the recess 110r. Thus, in the process of forming the second package 140, the second package 140 flowing in a dynamic manner can pass through the semiconductor. A space between the element 120 and the inner side wall 110w of the recess 110r is filled in the recess 110r. The second package body 140 filled in the recess 110r can function to support the semiconductor element 120.

請參照第2圖，其繪示依照本發明另一實施例之半導體封裝件的剖視圖。半導體封裝件200包括第二基板110、半導體元件220、第二覆晶(flip chip)230、封裝體140、黏合件150及屏蔽層160。Referring to FIG. 2, a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention is shown. The semiconductor package 200 includes a second substrate 110 , a semiconductor element 220 , a second flip chip 230 , a package 140 , an adhesive 150 , and a shielding layer 160 .

半導體元件220設於第二基板110上且包括第一基板121及第一覆晶222。本實施例中，半導體元件220以第一覆晶222設於第二基板110，且黏合件150設於第一覆晶222與第二基板110之間，以完整地覆蓋第一覆晶222之下表面與第二基板110之上表面110u，增加第一覆晶222與第二基板110的結合性。The semiconductor device 220 is disposed on the second substrate 110 and includes a first substrate 121 and a first flip chip 222 . In this embodiment, the semiconductor device 220 is disposed on the second substrate 110 with the first flip chip 222, and the adhesive member 150 is disposed between the first flip chip 222 and the second substrate 110 to completely cover the first flip chip 222. The lower surface and the upper surface 110u of the second substrate 110 increase the bonding of the first flip chip 222 and the second substrate 110.

第一基板121具有相對之第一面121b與第二面121u。銲線190電性連接於第一基板121與第二基板110。第二覆晶230可透過第一基板121、銲線190及第二基板110電性連接於一接地端。本實施例中，第二覆晶230可透過第一基板121之導通孔1212、銲線190及第二基板110之第一接地接墊113g、接地部111及第二接地接墊170g電性連接於一接地端(此接地端與第二接地接墊170g電性連接)。The first substrate 121 has a first surface 121b and a second surface 121u opposite to each other. The bonding wire 190 is electrically connected to the first substrate 121 and the second substrate 110. The second flip chip 230 is electrically connected to the ground via the first substrate 121 , the bonding wire 190 , and the second substrate 110 . In this embodiment, the second flip chip 230 is electrically connected to the via hole 1212 of the first substrate 121, the bonding wire 190, the first ground pad 113g of the second substrate 110, the grounding portion 111, and the second ground pad 170g. The grounding end is electrically connected to the second grounding pad 170g.

第一基板121之二導通孔1212之間可透過第一基板121的內部結構(如多層線路層)或外部結構(如走線)電性連接。The two via holes 1212 of the first substrate 121 can be electrically connected through an internal structure of the first substrate 121 (such as a multilayer wiring layer) or an external structure (such as a trace).

第一覆晶222具有相對之主動表面222u與背面222b。本實施例中，第一覆晶222之主動表面222u朝向第一基板121，而第一覆晶222之背面222b朝向第二基板110且透過黏合件150設於第二基板110之第一面110u上。The first flip chip 222 has an opposite active surface 222u and a back surface 222b. In this embodiment, the active surface 222u of the first flip chip 222 faces the first substrate 121, and the back surface 222b of the first flip chip 222 faces the second substrate 110 and is disposed on the first surface 110u of the second substrate 110 through the adhesive 150. on.

第二覆晶230設於第一基板121之第二面121u上。本實施例中，第二覆晶230係以主動面”朝下(face-down)”方位設於第一基板121上。即，第二覆晶230包括至少一凸塊(bump)231，第二覆晶230透過凸塊231可電性連接於第一基板121。The second flip chip 230 is disposed on the second surface 121u of the first substrate 121. In this embodiment, the second flip chip 230 is disposed on the first substrate 121 in an "face-down" orientation of the active surface. That is, the second flip chip 230 includes at least one bump 231 , and the second flip chip 230 is electrically connected to the first substrate 121 through the bump 231 .

請參照第3圖，其繪示依照本發明另一實施例之半導體封裝件的剖視圖。半導體封裝件300包括第二基板110、半導體元件220、第二覆晶230、半導體晶片130、封裝體140及屏蔽層160。Referring to FIG. 3, a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention is shown. The semiconductor package 300 includes a second substrate 110, a semiconductor element 220, a second flip chip 230, a semiconductor wafer 130, a package body 140, and a shield layer 160.

半導體晶片130與第二覆晶230係以堆疊方式配置。例如，半導體晶片130透過黏合件150設於第二覆晶230上。本實施例中，半導體晶片130係以主動面朝上(face-up)方位設於第二覆晶230上，其以銲線124電性連接半導體晶片130與第一基板121。The semiconductor wafer 130 and the second flip chip 230 are arranged in a stacked manner. For example, the semiconductor wafer 130 is disposed on the second flip chip 230 through the adhesive member 150. In this embodiment, the semiconductor wafer 130 is disposed on the second flip chip 230 in an active face-up orientation. The semiconductor wafer 130 and the first substrate 121 are electrically connected by the bonding wires 124.

請參照第4圖，其繪示依照本發明另一實施例之半導體封裝件的剖視圖。半導體封裝件400包括第二基板110、半導體元件220、多個第二覆晶230、封裝體140及屏蔽層160。Referring to FIG. 4, a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention is shown. The semiconductor package 400 includes a second substrate 110, a semiconductor element 220, a plurality of second flip-chips 230, a package body 140, and a shielding layer 160.

本實施例中，多個第二覆晶230係以邊靠邊(side by side)方式設於於第一基板121上。In this embodiment, the plurality of second flip-chips 230 are disposed on the first substrate 121 by side by side.

請參照第5A至5H圖，其繪示第1A圖之半導體封裝建的製造過程圖。Please refer to FIGS. 5A to 5H for a manufacturing process diagram of the semiconductor package of FIG. 1A.

如第5A圖所示，提供至少一半導體元件120。其中，半導體元件120包括第一基板121、第一半導體晶片122、第一封裝體123、至少一銲線124及第一屏蔽層125。第一基板121具有相對之第一面121b與第二面121u，第一半導體晶片122設於第一基板121之第一面121b上，而第一封裝體123包覆第一半導體晶片122。本步驟中，第一半導體晶片122係以主動面朝上方位設於第一基板110上。第一屏蔽層125覆蓋第一封裝體123之外側面123s及接地部1211。As shown in FIG. 5A, at least one semiconductor component 120 is provided. The semiconductor device 120 includes a first substrate 121 , a first semiconductor wafer 122 , a first package body 123 , at least one bonding wire 124 , and a first shielding layer 125 . The first substrate 121 has a first surface 121b and a second surface 121u. The first semiconductor wafer 122 is disposed on the first surface 121b of the first substrate 121, and the first package 123 covers the first semiconductor wafer 122. In this step, the first semiconductor wafer 122 is disposed on the first substrate 110 with the active surface facing upward. The first shielding layer 125 covers the outer surface 123s of the first package body 123 and the ground portion 1211.

本實施例中，可採用材料形成技術形成第一屏蔽層125。上述材料形成技術例如是化學氣相沈積、無電鍍法(electroless plating)、電解電鍍(electrolytic plating)、印刷、旋塗、噴塗、濺鍍(sputtering)或真空沈積法(vacuum deposition)。另一實施例中，亦可省略第一屏蔽層125。In this embodiment, the first shielding layer 125 may be formed by a material forming technique. The above material forming techniques are, for example, chemical vapor deposition, electroless plating, electrolytic plating, printing, spin coating, spray coating, sputtering, or vacuum deposition. In another embodiment, the first shielding layer 125 may also be omitted.

如第5B圖所示，以例如是表面黏貼技術(SMT)，設置半導體元件120於第二基板110上。其中，第二基板110具有至少一凹部110r，半導體元件120對應凹部110r設於第二基板110上。此外，半導體元件120可透過黏合件150設於第二基板110上。As shown in FIG. 5B, the semiconductor element 120 is disposed on the second substrate 110 by, for example, a surface mount technique (SMT). The second substrate 110 has at least one recess 110r, and the semiconductor element 120 is disposed on the second substrate 110 corresponding to the recess 110r. In addition, the semiconductor device 120 can be disposed on the second substrate 110 through the adhesive member 150.

本實施例中，在設置半導體元件120至第二基板110之前，可倒置(Reverse)半導體元件120，使半導體元件120之第一封裝體123朝向第二基板110，然後再將半導體元件120設於第二基板110上，如此一來，半導體元件120以第一封裝體123設於第二基板110上。In this embodiment, before the semiconductor device 120 is disposed to the second substrate 110, the semiconductor device 120 may be reversed such that the first package 123 of the semiconductor device 120 faces the second substrate 110, and then the semiconductor device 120 is disposed on the semiconductor device 120. On the second substrate 110, the semiconductor device 120 is disposed on the second substrate 110 in the first package body 123.

第二基板110包括至少一承載部112，承載部112對應凹部110r之轉角，在設置半導體元件120至第二基板110的過程中，半導體元件120可設於承載部112上。本實施例中，半導體元件120的四個轉角對應地設於第二基板110之四個承載部112上。The second substrate 110 includes at least one carrying portion 112. The carrying portion 112 corresponds to the corner of the recess 110r. During the process of disposing the semiconductor component 120 to the second substrate 110, the semiconductor component 120 can be disposed on the carrying portion 112. In this embodiment, the four corners of the semiconductor element 120 are correspondingly disposed on the four carrying portions 112 of the second substrate 110.

如第5C圖所示，可形成黏合件150於第二基板110上。然後，設置至少一第二半導體晶片130於第一基板121之第二面121u上，第二半導體晶片130透過黏合件150固定於第一基板121。第二半導體晶片130係以主動面朝上方位設於第一基板121上。As shown in FIG. 5C, the adhesive member 150 can be formed on the second substrate 110. Then, at least one second semiconductor wafer 130 is disposed on the second surface 121u of the first substrate 121, and the second semiconductor wafer 130 is fixed to the first substrate 121 through the adhesive 150. The second semiconductor wafer 130 is disposed on the first substrate 121 with the active surface facing upward.

如第5D圖所示，可採用打線技術，以銲線124電性連接第二半導體晶片130與第一基板121之導通孔1212，第二半導體晶片130透過銲線124及第一基板121電性連接於第一半導體晶片122。As shown in FIG. 5D, the bonding wire 124 is electrically connected to the second semiconductor wafer 130 and the via hole 1212 of the first substrate 121. The second semiconductor wafer 130 is electrically connected to the bonding wire 124 and the first substrate 121. Connected to the first semiconductor wafer 122.

如第5E圖所示，可採用打線技術，以銲線190電性連接第一基板121之導通孔1212與第二基板110之接墊113。As shown in FIG. 5E, the bonding wires 12 are electrically connected to the vias 1212 of the first substrate 121 and the pads 113 of the second substrate 110.

如第5F圖所示，採用例如是壓縮成型(compression molding)、注射成型(injection molding)或轉注成型(transfer molding)，形成第二封裝體140包覆半導體元件120、第二半導體晶片130、銲線124及190且填滿第二基板110之凹部110r。As shown in FIG. 5F, the second package 140 is formed to cover the semiconductor element 120, the second semiconductor wafer 130, and the solder by, for example, compression molding, injection molding, or transfer molding. Lines 124 and 190 fill the recess 110r of the second substrate 110.

如第5G圖所示，形成至少一切割狹縫P經過第二封裝體140、第二基板110及接地部111，使第二封裝體140形成外側面140s、第二基板110形成外側面110s及接地部111形成外側面111s，其中接地部111之外側面111s從第二基板110之外側面110s露出。此外，切割狹縫P形成後，第二封裝體140之外側面140s、第二基板110之外側面110s及接地部111之外側面111s實質上對齊，例如是共面。As shown in FIG. 5G, at least one cutting slit P is formed to pass through the second package body 140, the second substrate 110, and the ground portion 111, so that the second package body 140 forms the outer side surface 140s, the second substrate 110 forms the outer side surface 110s, and The ground portion 111 forms an outer side surface 111s in which the outer side surface 111s of the ground portion 111 is exposed from the outer side surface 110s of the second substrate 110. Further, after the slit S is formed, the outer surface 140s of the second package 140, the outer surface 110s of the second substrate 110, and the outer surface 111s of the ground portion 111 are substantially aligned, for example, coplanar.

形成切割狹縫P之前，可設置第5F圖之結構至一具有黏貼層之載板180上。切割狹縫P可經過整個第二封裝體140、第二基板110及部分載板180，以切斷第二封裝體140及第二基板110。本實施例的切割方式係以”全穿切(full-cut)”為例。Before forming the cutting slit P, the structure of the 5F drawing can be placed on a carrier 180 having an adhesive layer. The cutting slit P can pass through the entire second package 140, the second substrate 110, and a portion of the carrier 180 to cut the second package 140 and the second substrate 110. The cutting method of this embodiment is exemplified by "full-cut".

另一實施例中，只要切割狹縫P經過接地部111使其露出外側面111s即可，後續形成之第二屏蔽層160仍可覆蓋接地部111之外側面111s。在此情況下，可選選擇性地切穿第二封裝體140及部分之第二基板110；之後，再執行第二次切割，以切斷第二基板110及/或第二封裝體140。如此的切割方式稱為”半穿切(half-cut)”。In another embodiment, as long as the cutting slit P passes through the grounding portion 111 to expose the outer side surface 111s, the subsequently formed second shielding layer 160 can still cover the outer side surface 111s of the grounding portion 111. In this case, the second package body 140 and a portion of the second substrate 110 are selectively selectively cut; after that, the second cutting is performed to cut the second substrate 110 and/or the second package body 140. Such a cutting method is called "half-cut".

如第5H圖所示，可採用上述材料形成技術，形成第二屏蔽層160覆蓋第二封裝體140之外側面140s、第二基板110之外側面110s及接地部111之外側面111s。至此，形成至少一如第1A圖所示之半導體封裝件100。As shown in FIG. 5H, the second shielding layer 160 may be formed to cover the outer surface 140s of the second package 140, the outer surface 110s of the second substrate 110, and the outer surface 111s of the ground portion 111. Thus far, at least one semiconductor package 100 as shown in FIG. 1A is formed.

請參照第6A至6G圖，其繪示第2圖之半導體封裝件的製造過程圖。Please refer to FIGS. 6A to 6G for a manufacturing process diagram of the semiconductor package of FIG. 2.

如第6A圖所示，提供至少一半導體元件220。其中，半導體元件220包括第一基板121及第一覆晶222。第一基板121具有相對之第一面121b與第二面121u，第一覆晶222設於第一基板121之第一面121b上。As shown in FIG. 6A, at least one semiconductor component 220 is provided. The semiconductor device 220 includes a first substrate 121 and a first flip chip 222. The first substrate 121 has a first surface 121b and a second surface 121u opposite to each other, and the first flip chip 222 is disposed on the first surface 121b of the first substrate 121.

第一覆晶222係以主動面”朝下(face-down)”方位設於第一基板121上。例如，第一覆晶222包括至少一凸塊2221，第一覆晶222透過凸塊1221可電性連接於第一基板121。The first flip chip 222 is disposed on the first substrate 121 in an "face-down" orientation of the active surface. For example, the first flip chip 222 includes at least one bump 2221 , and the first flip chip 222 is electrically connected to the first substrate 121 through the bump 1221.

如第6B圖所示，以例如是表面黏貼技術，設置半導體元件220至第二基板110上。本實施例中，半導體元件220可透過黏合件150設於第二基板110上。As shown in FIG. 6B, the semiconductor element 220 is disposed on the second substrate 110 by, for example, a surface bonding technique. In this embodiment, the semiconductor device 220 is disposed on the second substrate 110 through the adhesive member 150.

在設置半導體元件220至第二基板110之前，可倒置半導體元件220，使第一覆晶222之背面222b朝向第二基板110，然後再將半導體元件220設於第二基板110上。如此一來，第一覆晶222以其背面222b設於第二基板110上。Before the semiconductor device 220 is disposed to the second substrate 110, the semiconductor device 220 may be inverted such that the back surface 222b of the first flip chip 222 faces the second substrate 110, and then the semiconductor device 220 is disposed on the second substrate 110. In this way, the first flip chip 222 is disposed on the second substrate 110 with its back surface 222b.

如第6C圖所示，以例如是表面黏貼技術，設置至少一第二覆晶230於第一基板121之第二面121u上。第二覆晶230包括至少一凸塊231，第二覆晶230以凸塊231電性連接於第一基板121之導通孔1212上。As shown in FIG. 6C, at least one second flip chip 230 is disposed on the second surface 121u of the first substrate 121 by, for example, a surface pasting technique. The second flip chip 230 includes at least one bump 231 , and the second flip chip 230 is electrically connected to the via hole 1212 of the first substrate 121 by the bump 231 .

如第6D圖所示，可採用打線技術，以銲線190電性連接第一基板121之導通孔1212與第二基板110之接墊113。其中一銲線190電性連接導通孔1212與第一接地接墊113g。As shown in FIG. 6D, the wire bonding technique is used to electrically connect the via hole 1212 of the first substrate 121 and the pad 113 of the second substrate 110. One of the bonding wires 190 is electrically connected to the via hole 1212 and the first ground pad 113g.

如第6E圖所示，以例如是壓縮成型、注射成型或轉注成型，形成封裝體140包覆半導體元件220、第二覆晶230及銲線190。As shown in FIG. 6E, the package body 140 is formed to cover the semiconductor element 220, the second flip chip 230, and the bonding wire 190 by, for example, compression molding, injection molding, or transfer molding.

如第6F圖所示，形成至少一切割狹縫P經過封裝體140、第二基板110及接地部111，使第二封裝體140形成外側面140s、第二基板110形成外側面110s及接地部111形成外側面111s，其中接地部111之外側面111s從第二基板110之外側面110s露出。此外，切割狹縫P形成後，封裝體140之外側面140s、第二基板110之外側面110s及接地部111之外側面111s實質上對齊，例如是共面。As shown in FIG. 6F, at least one cutting slit P is formed through the package body 140, the second substrate 110, and the ground portion 111, so that the second package body 140 forms the outer side surface 140s, and the second substrate 110 forms the outer side surface 110s and the ground portion. 111 forms an outer side surface 111s in which the outer side surface 111s of the ground portion 111 is exposed from the outer side surface 110s of the second substrate 110. Further, after the slit S is formed, the outer surface 140s of the package 140, the outer surface 110s of the second substrate 110, and the outer surface 111s of the ground portion 111 are substantially aligned, for example, coplanar.

形成切割狹縫P之前，可設置第6E圖之結構至一具有黏貼層之載板180上。切割狹縫P可經過整個封裝體140、第二基板110及部分之載板180，以切斷封裝體140及第二基板110。Before the cutting slit P is formed, the structure of Fig. 6E can be placed on a carrier 180 having an adhesive layer. The cutting slit P can pass through the entire package 140, the second substrate 110, and a portion of the carrier 180 to cut the package 140 and the second substrate 110.

如第6G圖所示，可採用上述材料形成技術，形成第一屏蔽層125覆蓋封裝體140之外側面140s、第二基板110之外側面110s及接地部111之外側面111s。至此，形成至少一如第2圖所示之半導體封裝件200。As shown in FIG. 6G, the first shielding layer 125 can be formed to cover the outer surface 140s of the package 140, the outer surface 110s of the second substrate 110, and the outer surface 111s of the ground portion 111. Thus far, at least one semiconductor package 200 as shown in FIG. 2 is formed.

另一實施例中，亦可採用上述”半穿切”方式形成半導體封裝件200。In another embodiment, the semiconductor package 200 can also be formed by the above-described "half-cut" method.

綜上所述，雖然本發明已以實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100、200、300、400．．．半導體封裝件100, 200, 300, 400. . . Semiconductor package

110．．．第二基板110. . . Second substrate

110b．．．第二面110b. . . Second side

110r．．．凹部110r. . . Concave

110s、111s、121s、123s、140s．．．外側面110s, 111s, 121s, 123s, 140s. . . Outer side

110u．．．第一面110u. . . First side

110w．．．內側壁110w. . . Inner side wall

111、1211．．．接地部111, 1211. . . Grounding

112．．．承載部112. . . Carrying part

113、170．．．接墊113, 170. . . Pad

113g．．．第一接地接墊113g. . . First grounding pad

120、220．．．半導體元件120, 220. . . Semiconductor component

121．．．第一基板121. . . First substrate

1212．．．導通孔1212. . . Via

121b．．．第一面121b. . . First side

121u．．．第二面121u. . . Second side

122．．．第一半導體晶片122. . . First semiconductor wafer

123．．．第一封裝體123. . . First package

124、190．．．銲線124,190. . . Welding wire

125．．．第一屏蔽層125. . . First shield

130．．．第二半導體晶片130. . . Second semiconductor wafer

140．．．第二封裝體140. . . Second package

150．．．黏合件150. . . Adhesive

160．．．第二屏蔽層160. . . Second shield

170g．．．第二接地接墊170g. . . Second grounding pad

180．．．載板180. . . Carrier board

222．．．第一覆晶222. . . First flip chip

222u．．．主動表面222u. . . Active surface

222b．．．背面222b. . . back

2221、231．．．凸塊2221, 231. . . Bump

230．．．第二覆晶230. . . Second flip chip

P．．．切割狹縫P. . . Cutting slit

第1A圖繪示依照本發明一實施例之半導體封裝件的剖視圖。1A is a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention.

第1B圖繪示第1A圖之第二基板及半導體元件的俯視圖。FIG. 1B is a plan view showing the second substrate and the semiconductor element of FIG. 1A.

第2圖繪示依照本發明另一實施例之半導體封裝件的剖視圖。2 is a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.

第3圖繪示依照本發明另一實施例之半導體封裝件的剖視圖。3 is a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.

第4圖繪示依照本發明另一實施例之半導體封裝件的剖視圖。4 is a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.

第5A至5H圖繪示第1A圖之半導體封裝建的製造過程圖。5A to 5H are views showing a manufacturing process of the semiconductor package of FIG. 1A.

第6A至6G圖繪示第2圖之半導體封裝建的製造過程圖。6A to 6G are diagrams showing a manufacturing process of the semiconductor package of Fig. 2.

100．．．半導體封裝件100. . . Semiconductor package

110．．．第二基板110. . . Second substrate

110b、121u．．．第二面110b, 121u. . . Second side

110r．．．凹部110r. . . Concave

110u、121b．．．第一面110u, 121b. . . First side

110s、121s、123s、140s．．．外側面110s, 121s, 123s, 140s. . . Outer side

111、1211．．．接地部111, 1211. . . Grounding

112．．．承載部112. . . Carrying part

113、170．．．接墊113, 170. . . Pad

113g．．．第一接地接墊113g. . . First grounding pad

120．．．半導體元件120. . . Semiconductor component

121．．．第一基板121. . . First substrate

1212．．．導通孔1212. . . Via

122．．．第一半導體晶片122. . . First semiconductor wafer

123．．．第一封裝體123. . . First package

124、190．．．銲線124,190. . . Welding wire

125．．．第一屏蔽層125. . . First shield

130．．．第二半導體晶片130. . . Second semiconductor wafer

140．．．第二封裝體140. . . Second package

150．．．黏合件150. . . Adhesive

160．．．第二屏蔽層160. . . Second shield

170g．．．第二接地接墊170g. . . Second grounding pad

Claims (15)

一種半導體封裝件，包括：一半導體元件，包括：一第一基板，具有相對之一第一面與一第二面；一第一半導體晶片，設於該第一基板之該第一面上；及一第一封裝體，包覆該第一半導體晶片；一第二基板，具有一凹部，該半導體元件對應該凹部設於該第二基板上；一第二半導體晶片，設於該第一基板之該第二面上；以及一第二封裝體，包覆該半導體元件及該第二半導體晶片且填滿該第二基板之該凹部。A semiconductor package comprising: a semiconductor device, comprising: a first substrate having a first surface and a second surface; a first semiconductor wafer disposed on the first surface of the first substrate; And a first package covering the first semiconductor wafer; a second substrate having a recess, the semiconductor component corresponding to the recess being disposed on the second substrate; and a second semiconductor wafer disposed on the first substrate The second surface; and a second package covering the semiconductor element and the second semiconductor wafer and filling the recess of the second substrate. 如申請專利範圍第1項所述之半導體封裝件，其中該第二基板具有一外側面且包括一接地部，該接地部從該第二基板之該外側面露出，該半導體元件更包括：一第一屏蔽層，覆蓋該第一封裝體之一外側面及露出之該接地部。The semiconductor package of claim 1, wherein the second substrate has an outer surface and includes a ground portion, the ground portion is exposed from the outer side surface of the second substrate, and the semiconductor component further comprises: The first shielding layer covers an outer side surface of the first package body and the exposed ground portion. 如申請專利範圍第1項所述之半導體封裝件，其中該半導體元件以該第一封裝體設於該第二基板。The semiconductor package of claim 1, wherein the semiconductor component is disposed on the second substrate with the first package. 如申請專利範圍第1項所述之半導體封裝件，其中該第二基板包括一承載部，該承載部的位置對應於該凹部之轉角，該半導體元件設於該承載部上。The semiconductor package of claim 1, wherein the second substrate comprises a carrying portion, the position of the carrying portion corresponds to a corner of the recess, and the semiconductor component is disposed on the carrying portion. 如申請專利範圍第1項所述之半導體封裝件，其中該第一基板包括一接地部，該接地部從該第一基板之一外側面露出，該半導體元件更包括：一第一屏蔽層，覆蓋該第一封裝體之一外側面及露出之該接地部。The semiconductor package of claim 1, wherein the first substrate comprises a grounding portion, the grounding portion is exposed from an outer side of the first substrate, and the semiconductor component further comprises: a first shielding layer, Covering an outer side surface of the first package and the exposed ground portion. 如申請專利範圍第5項所述之半導體封裝件，更包括：一銲線，電性連接該第一基板與該第二基板；其中，該第一屏蔽層透過該第一基板、該銲線及該第二基板電性連接於一接地端。The semiconductor package of claim 5, further comprising: a bonding wire electrically connecting the first substrate and the second substrate; wherein the first shielding layer passes through the first substrate, the bonding wire And the second substrate is electrically connected to a ground. 一種半導體封裝件之製造方法，包括：提供一半導體元件，其中該半導體元件包括一第一基板、一第一半導體晶片及一第一封裝體，該第一基板具有相對之一第一面與一第二面，該第一半導體晶片設於該第一基板之該第一面上，而該第一封裝體包覆該第一半導體晶片；設置該半導體元件至一第二基板上，其中該第二基板具有一凹部，該半導體元件對應該凹部設於該第二基板上；設置一第二半導體晶片於該第一基板之該第二面上；以及形成一第二封裝體包覆該半導體元件及該第二半導體晶片且填滿該第二基板之該凹部。A method of fabricating a semiconductor package, comprising: providing a semiconductor device, wherein the semiconductor device comprises a first substrate, a first semiconductor wafer, and a first package, the first substrate having a first side and a first surface a second surface, the first semiconductor wafer is disposed on the first surface of the first substrate, and the first package covers the first semiconductor wafer; the semiconductor component is disposed on a second substrate, wherein the first The second substrate has a recess, the semiconductor component corresponding to the recess is disposed on the second substrate; a second semiconductor wafer is disposed on the second surface of the first substrate; and a second package is formed to encapsulate the semiconductor component And the second semiconductor wafer fills the recess of the second substrate. 如申請專利範圍第7項所述之製造方法，其中於設置該半導體元件至該第二基板上之該步驟前，該製造方法更包括：倒置該半導體元件，使該半導體元件之該第一封裝體朝向該第二基板。The manufacturing method of claim 7, wherein before the step of disposing the semiconductor device onto the second substrate, the manufacturing method further comprises: inverting the semiconductor device to make the first package of the semiconductor device The body faces the second substrate. 如申請專利範圍第8項所述之製造方法，其中於設置該半導體元件至該第二基板上之該步驟中，該第二基板包括一承載部，該承載部的位置對應於該凹部之轉角，該半導體元件設於該承載部上。The manufacturing method of claim 8, wherein in the step of disposing the semiconductor element onto the second substrate, the second substrate comprises a carrying portion, the position of the carrying portion corresponding to a corner of the recess The semiconductor component is disposed on the carrier. 如申請專利範圍第7項所述之製造方法，其中該第二基板包括一接地部，該第二基板之該接地部從該第二基板之一外側面露出，該製造方法更包括：形成一第二屏蔽層覆蓋該第二封裝體之一外側面及露出之該接地部。The manufacturing method of claim 7, wherein the second substrate comprises a grounding portion, the grounding portion of the second substrate is exposed from an outer side surface of the second substrate, and the manufacturing method further comprises: forming a The second shielding layer covers an outer side surface of the second package body and the exposed ground portion. 如申請專利範圍第7項所述之製造方法，其中該第一基板包括一接地部，該第一基板之該接地部從該第一基板之一外側面露出，於設置該半導體元件至該第二基板上之該步驟之前，該製造方法更包括：形成一第一屏蔽層覆蓋該第一封裝體之一外側面及該第一基板之露出之該接地部。The manufacturing method of claim 7, wherein the first substrate comprises a grounding portion, the grounding portion of the first substrate is exposed from an outer side surface of the first substrate, and the semiconductor component is disposed to the first Before the step of the second substrate, the manufacturing method further comprises: forming a first shielding layer covering an outer side surface of the first package body and the exposed ground portion of the first substrate. 一種半導體封裝件，包括：一半導體元件，包括：一第一基板，具有相對之一第一面與一第二面；及一第一覆晶，設於該第一基板之該第一面上；一第二基板，該半導體元件設於該第二基板上且電性連接於該第一基板；一第二覆晶，設於該第一基板之該第二面上；以及一封裝體，包覆該半導體元件及該第二覆晶。A semiconductor package comprising: a semiconductor device, comprising: a first substrate having a first surface and a second surface; and a first flip chip disposed on the first surface of the first substrate a second substrate, the semiconductor device is disposed on the second substrate and electrically connected to the first substrate; a second flip chip is disposed on the second surface of the first substrate; and a package body, The semiconductor element and the second flip chip are coated. 如申請專利範圍第12項所述之半導體封裝件，其中該半導體元件以該第一覆晶設於該第二基板，該半導體封裝件更包括：一黏合件，設於該第一覆晶與該第二基板之間。The semiconductor package of claim 12, wherein the semiconductor device is disposed on the second substrate by the first flip chip, the semiconductor package further comprising: an adhesive member disposed on the first flip chip and Between the second substrates. 如申請專利範圍第12項所述之半導體封裝件，其中該第二基板具有一外側面且包括一接地部，該第二基板之該接地部從該第二基板之該外側面露出，該半導體封裝件更包括：一屏蔽層，覆蓋該封裝體之一外側面及該接地部。The semiconductor package of claim 12, wherein the second substrate has an outer side surface and includes a ground portion, the ground portion of the second substrate is exposed from the outer side surface of the second substrate, the semiconductor The package further includes: a shielding layer covering an outer side surface of the package body and the grounding portion. 如申請專利範圍第12項所述之半導體封裝件，更包括：一銲線，電性連接該第一基板與該第二基板；其中，該第二覆晶透過該第一基板、該銲線及該第二基板電性連接於一接地端。The semiconductor package of claim 12, further comprising: a bonding wire electrically connecting the first substrate and the second substrate; wherein the second flip chip passes through the first substrate, the bonding wire And the second substrate is electrically connected to a ground.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI619177B (en) * 2014-06-04 2018-03-21 英凡薩斯公司 Integrated interposer solutions for 2d and 3d ic packaging
US10103128B2 (en) 2013-10-04 2018-10-16 Mediatek Inc. Semiconductor package incorporating redistribution layer interposer
TWI647796B (en) * 2018-04-09 2019-01-11 矽品精密工業股份有限公司 Electronic package and its manufacturing method
CN114300446A (en) * 2022-03-09 2022-04-08 甬矽电子(宁波)股份有限公司 Chip stacking shielding structure and manufacturing method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10103128B2 (en) 2013-10-04 2018-10-16 Mediatek Inc. Semiconductor package incorporating redistribution layer interposer
TWI619177B (en) * 2014-06-04 2018-03-21 英凡薩斯公司 Integrated interposer solutions for 2d and 3d ic packaging
TWI647796B (en) * 2018-04-09 2019-01-11 矽品精密工業股份有限公司 Electronic package and its manufacturing method
CN114300446A (en) * 2022-03-09 2022-04-08 甬矽电子(宁波)股份有限公司 Chip stacking shielding structure and manufacturing method thereof
CN114300446B (en) * 2022-03-09 2022-07-08 甬矽电子(宁波)股份有限公司 Chip stacking shielding structure and manufacturing method thereof

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