200828338 九、發明說明 【發明所屬之技術領域】 本發明大致關係於記憶體系統。更明確地說，本發明 關係於串聯連接記憶體裝置之記憶體系統，以用於大量儲 存應用。 【先前技術】 • 快閃記憶體爲常用類型之非揮發記憶體，被大量用作 爲消費電子之大量儲存器，這些消費電子係如數位相機及 攜帶式數位音樂播放器。現行可用之快閃記憶體晶片的密 度可以到達32Gbit ( 4GB )，這係適用於通用之USB快 閃驅動器，因爲一快閃晶片的尺寸很小。 第1圖爲已知一排NAND快閃記憶體的一般方塊圖。 熟習於本技藝者可以了解，一快閃記憶體裝置可以具有任 意數量之排。排30係被組織爲k+Ι方塊。每一方塊包含 ® NAND記憶單元串，有多達i + l之快閃記憶單元彼此串聯 連接。因此，字元線WL0至WLi係被連接至記憶單元串 中之每一快閃記憶單元的閘極。一連接至信號s s L (串選 擇線）之串選擇裝置選擇地連接記憶單元串至〜位元線， 而一連接至is號GSL (接地選擇線）之接地選擇裝置選擇 地連接該S己憶單兀串至一電源線，例如v S S。串選擇裝置 及接地選擇裝置係爲η -通訊電晶體。其中有j + 1個位元線 爲排3 0的所有方塊所共用，及每一位元線連接至每一方 塊[〇]至[k]中之一 NAND記憶單元串。每一字元線（WL〇 200828338 至WLi) 、SSL及GSL信號被連接至在該方塊中之每一 NAND記憶單元串中之相同對應電晶體裝置。如同熟習於 本技藝者所知，儲存於快閃記憶單元中之資料與一字元線 被稱爲一頁資料。 連接至排30外之每一位元線係爲一資料暫存器32， 用以儲存予以被規劃入一頁快閃記憶單元中之一頁寫入資 料，或由該快閃記憶單元取出之讀取資料。資料暫存器 32也包含一感應電路，用以感應自一頁快閃記憶單元讀 出之資料。在規劃操作時，資料暫存器執行程式驗證操作 ，以確保資料已經適當地規劃入連接至選擇字元線的快閃 記憶單元。排30的每一記憶單元可以儲存單一位元資料 或多位元之資料。部份快閃記憶裝置將有一組以上之資料 暫存器，以增加通量。 八百萬像素數位相機及具有音樂及影像能力之可攜式 數位娛樂裝置的出現已經對於儲存大量資料有超高之需求 ’這並不能爲單一快閃記憶體裝置所配合。因此，多快閃 S己憶體裝置被組合在一起成爲一記憶體系統，以有效地增 加可用之儲存容量。例如，此等應用可能需要2 0 G B之快 閃儲存密度。 第2圖爲被整合至一主機系統12之先前技術記憶體 系統1 0的方塊圖。快閃記憶體系統1 〇包含一記憶體控制 器1 4，與該主機系統相通訊；及多非揮發記憶體裝置1 6 。主機系統將包含例如微控制器、微處理機或電腦系統之 處理裝置。第2圖之快閃記憶體系統1 〇係被架構以包含 -6 - 200828338 一通道1 8，其中記憶體裝置1 6係並聯連接至該通道1 8。 熟習於本技藝者可以了解，記憶體系統1 0可以具有多於 或少於四個記憶體裝置連接至其上。 通道1 8包含一組命令匯流排，其包含連接至其對應 §己憶體裝置的資料與控制線。每一記憶體裝置係對應於爲 記憶體控制器14所提供之個別晶片選擇信號ce# 1、 CE#2、CE#3及CE#4加以致能/去能。“#，，表示信號係爲 低態有效邏輯位準信號。記憶體控制器1 4係負責經由通 道18發出命令及資料，以根據主機系統12之操作，選擇 記憶體裝置。自記憶體裝置讀出之資料經由通道1 8被傳 回至記憶體控制器14及主機系統12。快閃記憶體系統10 的操作係同步於一時鐘CLK，其係被並聯提供給每一記憶 體裝置1 6。快閃記憶體系統1 〇大致稱爲多投架構，其中 記憶體裝置1 6相對於通道1 8係被並聯連接。 在快閃記憶體系統1 0中，非揮發記憶體裝置i 6可以 彼此相同，並典型被實施爲NAND快閃記憶體裝置。熟習 於本技藝者可以了解，快閃記憶體被組織成排，每一排被 組織成方塊，以促成方塊抹除。多數商用N AND快閃記憶 體裝置被組態以具有兩排記憶體。 有幾項特殊事項將負面影響系統的效能。快閃記憶體 系統1 0的架構加了實體效能限制。以大量延伸於整個系 統之並聯信號，它們所承載之信號的信號完整性將由於串 音、信號偏斜、及同時切換雜訊（S SN )而劣化。在此一 架構中之功率消耗也當在快閃控制器與快閃記憶體裝置間 200828338 之每一信號軌經常作信號的充放電而變成一事件。隨著系 統時鐘頻率的增加’功率消耗將增加。 對於可以並聯連接至通道的記憶體裝置的數量也有實 質之限制，因爲相較於長信號軌的載入，單一記憶體裝置 的驅動能力很小。再者，當記憶體裝置的數量增加時，需 要更多晶片致能信號（CE#)，及時鐘信號CLK將需要被 發送至另外的記憶體裝置。由於密集時鐘分配之時鐘效能 0 事件在本技藝中係爲已知的，這將需要討論。因此，爲了 容納具有大量記憶體裝置的記憶體系統，必須使用一具有 更多通道的控制器，或系統需要以更低頻率加上時鐘。架 構以具有多數通道的控制器及額外之晶片致能信號增加了 記憶體系統之成本。否則，記憶體系統將被限制爲小數量 之記憶體裝置。 因此，吾人想要提供一記憶體系統架構，其能支援任 意數量之記憶體裝置。 【發明內容】 本發明之態樣爲避免或免除前述記憶體系統之至少一 缺點。 在第一態樣中，本案提供有一具有一控制器及一記憶 體裝置的記憶體系統。該控制器包含提供串聯位元流命令 封包的串聯通道輸出璋；及一用以接收一串聯位元流讀取 資料封包的串聯通道輸入埠。該串聯位元流命令封包包含 一操作碼及一裝置位址。該記憶體裝置具有一輸入埠，用 -8- 200828338 以自控制器接收串聯位元流命令封包並且如果裝置位址對 應於記憶體裝置，則用以執行該操作命令。記憶體裝置經 由輸出埠提供串聯位元流命令封包並隨後如果該操作碼對 應於一讀取動作，則經由輸出埠提供串聯位元流讀取資料 封包。 依據本態樣的實施例，其中至少一中介記憶體裝置串 聯連接於該記憶體裝置與該控制器之間。該至少一中介記 憶體裝置具有用以接收及傳送串聯位元流命令封包至記憶 體裝置並隨後提供串聯位元流命令封包給該記憶體裝置並 且如果裝置位址對應於該記憶體裝置及該操作碼對應於一 讀取功能，而隨後提供該串聯位元流讀取資料封包的輸入 璋° 依據其他實施例，互補時鐘信號係被並聯提供給該記 憶體裝置及該至少一中介記憶體裝置’或者互補時鐘信號 係被提供給至少一中介記憶體裝置並爲該至少一中介記憶 體裝置所傳送給該記憶體裝置，並爲該記憶體裝置所傳送 至控制器。 在本態樣的另一實施例中，記憶體系統包含於控制器 與記憶體裝置間之擴充鏈結，用以接收一擴充模組及一跳 線之一者。該至少一中介記憶體裝置係爲一擴充模組的一 部份，其具有耦接機構以電氣耦接至該擴充鏈結。 依據其他實施例，記憶體裝置及至少一中介記憶體裝 置各個包含一本地記億體核心及一串列介面，與一控制邏 輯方塊，用以回應於串聯位元流命令封包’控制該本地記 -9- 200828338 憶體核心。該記憶體裝置本地記憶體核心及至少一中介記 憶體裝置本地記憶體核心可以爲NAND快閃記憶體爲主、 或可以爲DRAM、SRAM、NAND快閃記憶體或NOR快閃 記憶體核心。 在本態樣之另一實施例中，串聯位元流命令封包具有 一模組化結構，其中之串聯位元流命令封包的大小爲可變 的。串聯位元流命令封包可以包含用以提供操作碼及裝置 位址的命令欄，其中該命令欄包含一第一次欄，用以提供 操作碼，及一第二次欄，用以提供裝置位址。串聯位元流 命令封包可以包含一命令欄，用以提供操作及裝置位址， 及一位址欄，用以提供一列位址及一行位址之一的位址欄 。串聯位元流命令封包可以包含一命令欄，用以提供操作 碼及裝置位址、一位址欄，用以提供列位址及行位址之一 、及一資料欄，用以提供寫入資料。 依據先前實施例之一態樣，控制器提供一命令選通並 聯於該串聯位元流命令封包，該命令選通具有一匹配於串 聯位元流命令封包長度的作動位準。再者，控制器並聯於 串聯位元流讀取資料封包提供一資料輸入選通，該資料輸 入選擇具有匹配於該串聯位元流讀取資料封包長度的作動 位準。當裝置位址對應於該記憶體裝置時，該記憶體裝置 回應於該命令選通的作動位準，閂鎖該串聯位元流命令封 包，及該記憶體裝置輸出埠係回應於該資料輸入選通的作 動位準而被致能。命令選通及資料輸入選通爲非重疊信號 ，並爲至少一資料閂鎖時鐘緣所分開。另外，該命令選擇 -10- 200828338 也爲鄰近命令選通所分開至少一資料閂鎖時鐘緣，該資料 輸入選通係爲鄰近資料輸入選通所分開至少一資料μ鎖時 鐘緣。 在第一態樣中’提供有一具有一串聯位元之命令封包 給具有串聯連接記憶體裝置的記憶體系統。該命令封包包 含一命令欄，用以選擇串聯連接記憶體裝置的一記憶體裝 置，以執行一特定記憶體操作。 • 在第二態樣的實施例中，命令攔包含一第一次欄，用 以提供選擇記憶體裝置的裝置位址，及一第二次欄，用以 提供對應於該特定記憶體操作之操作碼。該命令封包更包 含一位址欄在該命令欄後，用以當該操作碼對應於一讀取 或寫入操作時，提供列位址與行位址之一，該位址欄具有 對應於列位址或行位址之位元長度。一資料欄在該位址欄 之後，用以當操作碼對應於寫入操作時，提供寫入資料以 儲存於記憶體裝置中，該資料欄具有對應於寫入資料的位 Φ 元長度。 在第二態樣中’提供有在記憶體系統中之選定記憶體 裝置中，執行同時發生操作的方法，該記憶體系統具有串 聯連接之記億體裝置。該方法包含：接收第一命令；回應 於該第一命令，在該選定記憶體裝置中之第一記憶體排內 執行核心操作；在該第一記憶體排中執行核心操作的同時 ’接收一^第二命令；及回應於該弟一命令’在該選定記憶 體裝置中之第二記憶體排內執行核心操作。 依據本態樣之實施例’該方法更包含：接收一第三命 -11 - 200828338 令，用以由第一記憶體排及第二記憶體排之一要求資訊， 及回應於該第三命令，輸出包含所得資訊的讀取資料封包 。該所得資訊包含狀態暫存器資料及讀取資料之一。 在本態樣之另一實施例中，該第一命令、第二命令、 第三命令係爲命令封包，包含一連串之位元，其係被邏輯 地架構以包含一強制命令欄，用以提供一操作碼及一裝置 位址；一選用位址欄，在該命令欄後，用以當操作碼對應 於一讀取或寫入操作時，提供列及行位址之一；及一選用 資料欄在該位址欄後，用以當操作碼對應於寫入操作時， 提供寫入資料。 在本實施例之一態樣中，第一命令選通係與第一命令 並聯接收，該第一命令選通具有對應於第一命令長度的作 動持續時間，及第二命令選通係並聯於第二命令接收，該 第二命令選通具有對應於第二命令長度的作動持續時間。 第一命令選通與第二命令選通係分開至少一資料閂鎖時鐘 緣。再者，一資料輸入選通係被接收，以當資料輸入選通 係在作動位準的同時，致能讀取資料封包的輸出，使得第 二命令選通與資料輸入選通係分開至少一資料閂鎖時鐘緣 〇 在另一實施例中，該方法包含在接收該第一命令前， 供電該選定記憶體裝置。該供電步驟包含：在電源轉移前 ，主張（assert ) —控制信號，以維持該選定記憶體裝置 於預設狀態；當該控制信號被主張的同時，將該選定記憶 體裝置的電源位準由第一電壓位準轉移至第二電壓位準； -12- 200828338 等待一預定持續時間，以允許電源位準穩定；及解除（ de-assert)該控制信號，以將該選定記憶體裝置由該預設 狀態釋放，藉以防止在該選定記憶體裝置的不小心規劃或 抹除操作。第二電壓位準可以爲用以穩定電路操作之最小 電壓位準或電源之最大操作電壓位準。第一電壓位準可以 對應於電源之低電力模式操作電壓位準，或是沒有電源。 在另一實施例中，維持該記憶體裝置於該預設狀態中 包含設定該記憶體裝置中之裝置暫存器至預設値，其中該 裝置暫存器包含命令暫存器。該方法之另一步驟包含在啓 始該記憶體裝置由預設狀態釋放時，執行裝置啓始化。該 執行裝置啓始化的步驟包含產生用於該記憶體裝置的裝置 位址及裝置識別碼資訊。 在另一實施例中，供電步驟包含在第一時間主張一控 制信號，以在電源轉移前，維持該記憶體裝置於一預設狀 態；當該控制信號被主張的同時，將該記憶體裝置的電源 位準由第一位準轉移至第二位準；等待預定持續時間，以 允許電源位準穩定；及在第三後續時間，解除該控制信號 ，以將記憶體裝置自預設狀態釋放，藉以防止在該記憶體 裝置的不小心規劃或抹除操作。 在第四態樣中，設有一記憶體系統，其包含多數記憶 體裝置及一控制器，用以控制這些裝置。該控制器具有輸 出埠，用以提供位元流命令封包給該多數記憶體裝置的第 一裝置，該位元流命令封包包含一操作碼及一裝置位址。 各個記憶體裝置自控制器與前一記憶體裝置之一，接收位 -13- 200828338 元流命令封包，並且，如果裝置位址對應的話，則執行操 作碼，各個記憶體裝置提供位元流命令封包給下一記憶體 裝置與該控制器之一者，如果該操作碼對應於一讀取功能 ，則一位元流讀取資料封包被由多數記憶體裝置的最後一 個記憶體裝置提供給該控制器。 依據本態樣的實施例，多數記憶體裝置係被串聯連接 ，第一及最後記憶體係被連接至該控制器，該控制器送出 一位元流資料封包給多數記憶體裝置的第一裝置。來自控 制器之該位元流資料封包及位元流讀取資料封包包含一串 聯位元流或包含並聯位元流。多數記憶體裝置爲相同類型 或不同類型之記憶體裝置的混合。 依據另一實施例，該記億體系統能在接收第一命令前 ，執行選定記憶體裝置的供電功能。該記憶體系統可以執 行功能有：主張一控制信號，以在電力轉移前，維持該選 定記憶體裝置於預設狀態；在主張該控制信號的同時，將 該選定記憶體裝置的電力位準由第一電壓位準轉移至第二 電壓位準；等待一預定持續時間，以允許電力位準穩定； 及解除該控制信號，以將該選定記憶體裝置自該預設狀態 釋放，藉以防止選定記憶體裝置的不小心規劃或抹除操作 。該記憶體系統也可以有功能爲：在第一時間主張一控制 信號，以在電力轉移前，維持記憶體裝置於預設狀態；當 該控制信號被主張的同時，將該記憶體裝置的電力位準由 第一位準轉移至第二位準；等待一預定持續時間，以允許 電力位準穩定；在第三後續時間，解除該控制信號，以將 -14- 200828338 該記憶體裝置由預設狀態釋放，藉以防止記憶體裝置的不 小心規劃或抹除操作。 本發明之態樣與特性將在熟習於本技藝者配合附圖看 過以下本發明之特定實施例後加以了解。 【實施方式】 以下本發明實施例之詳細說明中，參考形成爲本發明 一部份之附圖，其中顯示本發明可以實施之特定實施例。 這些實施例係足夠詳細地描述，以使得熟習於本技藝者可 以實施本發明，可以了解的是，也可以利用其他實施例， 完成邏輯、電性及其他方塊的改變，而不會脫離本發明之 範圍。因此，以下之詳細說明並不作爲限制用，本發明之 範圍係由隨附之申請專利範圍加以界定。 本案描述具有串聯連接記憶體裝置的記憶體系統架構 。記憶體系統係可縮放以包含任意數量之記憶體裝置，而 沒有效能上之劣化或複雜之再設計。每一記憶體裝置具有 一串聯輸入/輸出介面，用於其他記憶體裝置與記憶體控 制器間之通訊。該記憶體控制器在至少一位元流中發出命 令，其中該位元流跟隨有一模組化命令協定。該命令包含 一操作碼，具有選用之位址資訊及裝置位址，使得只有被 定址之記憶體裝置作用該命令。分開之資料輸出選通與命 令輸入選通信號分別並聯提供有各個輸出資料流及輸入命 令資料流，用以指明資料的類型與資料的長度。模組化命 令協定係用以在每一記憶體裝置中執行同時發生之操作， -15- 200828338 以進一步改良效能。 第3A圖爲依據一實施例之串聯記憶體系統之槪念結 構的方塊圖。在第3A圖中，串聯記億體系統1〇0包含具 有至少一串聯通道輸出埠Sout及一串聯通道輸入璋sin 之記憶體控制器102，及串聯連接之記憶體裝置1〇4、106 、1 08、1 1 0、1 1 2、11 4及1 1 6。在一實施例中，記憶體裝 置可以爲快閃記憶體裝置。或者，記憶體裝置也可以爲 DRAM' SRAM或任意類型之記憶體裝置，只要其具有一 串聯輸入/輸出介面，與一特定命令結構相容即可，該結 構係用以執行命令或傳送命令及資料至下一記憶體裝置。 此記憶體裝置架構與一特定命令結構的其他細節將如後述 Ο .現行實施例包含七個記憶體裝置，但其他實施例則可 以少到只有一記憶體裝置，或多到任意數量之記憶體裝寘 。因此，如果記憶體裝置104爲串聯記憶體系統100之第 一裝置，因爲其連接至Sout，則記憶體裝置116爲第N 個或最後裝置，因爲其連接Sin，其中N爲大於0之整數 。記憶體裝置106至116然後中介串聯連接至第一與最後 記憶體裝置間之串聯連接之記憶體裝置。每一記憶體裝置 可以在系統供電啓始化時，假設一特有識別號碼，或裝置 位址（DA )，使得它們可個別被定址。同一受讓人之美 國專利申請案 1 1/622,828 ; 1 1/750,649 ; 1 1 /692,452 ; 11/692,446; 11/692,326 及 11/771,023 描述 了一種產生記 憶體系統之串聯連接記憶體裝置的裝置位址的方法。 -16- 200828338 因爲一記憶體裝置的資料輸入被連接至前一記憶體裝 置的資料輸出，所以記憶體裝置104至116係被認爲是串 聯連接，因而’形成一串聯連接架構，除了在鏈中之第一 及最後記憶體裝置以外。 記憶體控制器102的通道包含任意資料寬的資料通道 ’以承載命令、資料及位址資訊；及一控制通道，以承載 控制信號資料。通道架構的其他細節將如後所示。第3 A 圖之實施例包含一通道，其中一通道包含一 S out及對應 Sin璋。然而’記憶體控制器1〇2可以包含任意數量之通 道’用以收納分開之記憶體裝置鏈。 在一般操作中，記憶體控制器i 〇2經由其Sout埠發 出一命令，其包含一操作碼（op碼）、一裝置位址、位 址資訊’用以讀取或規劃；及用以規劃的資料。該命令係 發出爲串聯位元流封包，其中該封包可以邏輯地再細分爲 預定大小之區段，例如一位元組。一位元流係爲在時間上 所提供之位元順序或連續。該命令係爲第一記憶體裝置 1 04所接收’將裝置位址與其指定位址作比較。如果位址 匹配’則記憶體裝置丨〇4執行該命令。否則，該命令被傳 送經其輸出璋而到下一記憶體裝置1 〇6，其中重覆了相同 之程序°最後’被稱爲選定記憶體裝置的具有相同裝置位 址的記憶體裝置將執行爲該命令所指定的操作。如果該命 令爲讀取資料’則選定記憶體裝置將經由其輸出埠輸出讀 取資料’其係串聯地傳送至中介記憶體裝置，直到其到達 g己憶體控制命1 0 2的S i η ί阜爲止。 -17- 200828338 因爲命令及資料被提供於串聯位元流中，所以，一時 鐘係爲每一記憶體裝置所使用，以對入/出串聯位元加時 鐘信號及用以同步化內部記憶體裝置之操作。此時鐘係爲 在該串聯記憶體系統1 〇〇中之記憶體控制器及所有記憶體 裝置所使用。對於串聯記憶體系統100有兩個可能之時鐘 架構，並將以第4及5圖之實施例加以顯示。 第3B圖爲包含一類型之憶體裝置，例如NAND快閃 記憶體裝置之第3A圖之記憶體系統之方塊圖。每一 NAND快閃記憶體裝置可以彼此相同或彼此不同，例如在 儲存密度上之不同。第3C圖爲包含各種類型記憶體裝置 之記憶體系統的方塊圖。這些記憶體裝置可以包含NAND 快閃記憶體裝置、NOR快閃記憶體裝置、動態隨機存取 記憶體（DRAM )裝置、靜態隨機存取記憶體（81^1^) 裝置及磁阻隨機存取記憶體（MRAM )裝置。當然，於此 未提及之記憶體裝置也可以實施於記憶體系統中。此一具 有混合類型之記憶體裝置的架構係揭示於申請於2006年 十二月6日之美國臨時專利申請第60/8 68，773號案中。 第4圖爲一使用並聯時鐘設計的串聯記憶體系統的方 塊圖。串聯記憶體系統200包含一記憶體控制器202及四 個記憶體裝置204、206、208及210。記憶體控制器202 並聯提供幾個信號給記憶體裝置。這些包含晶片致能信號 CE#、重置信號RST#、及互補時鐘CK#及CK。在使用 CE#的一例子中，當CE#爲低邏輯位準時，裝置被致能。 一旦記憶體裝置開始規劃或抹除操作時，CE#被解除，或 -18- 200828338 驅動至高邏輯位準。另外，在低邏輯位準之CE#也可以啓 動內部時鐘信號，及在高邏輯位準之CE#則可以去能內部 時鐘信號。在使用RST#的例子中，當RST#爲低邏輯位準 時，記憶體裝置被設定至重置模式。在重置模式中，電力 被允許穩定化及裝置藉由啓始所有有限狀態機器及重置任 一架構及狀態暫存器至其預設狀態，而準備操作。 記憶體控制器202的通道包含：一資料通道，其係由 輸出璋Qn及輸入埠Dn所構成；及一控制通道，其係由 一命令選通輸入CSI、一命令選通輸出CSO(CSI的回音 )、資料選通輸入DSI、及一資料選通輸出DSO(DSI的 回音）。取決於想要的架構而定，輸出璋Qn及輸入璋Dn 可以是寬度1位元，或寬度η位元，其中η爲非零的整數 。例如，如果η爲1，則一位元組資料在時鐘的八資料閂 鎖緣後被接收。一資料閂鎖時鐘緣可以例如爲一上升時鐘 緣。如果η爲2，則一位元組資料係在時鐘的四閂鎖緣後 被接收。如果η爲4，則一位元組資料係在時鐘的兩閂鎖 緣後被接收。記憶體裝置可以靜態地架構或動態地架構任 意寬度之Qn及Dn。因此，在η大於1的架構中，記憶體 控制器在並聯位元流中提供資料。CSI係用以閂鎖出現在 輸入埠Dn的命令資料，並具有對應於所接收命令資料長 度的脈寬。更明確地說，該命令資料將具有爲若干時鐘循 環所量測的持續時間，及CSI信號的脈寬將具有對應持續 時間。DSI係用以致能輸出埠Qn緩衝器以輸出資料，並 具有對應於被要求之讀取資料長度的脈寬。DSI及CSI信 -19- 200828338 號之其他細節將如後所討論。 在第4圖所示之實施例中，每一記憶體裝置具有相同 串列輸入/輸出介面，其包含RST#、CE#、CK#及CK輸 入埠，用以自記憶體控制器202接收相同名稱信號。串聯 輸入/輸出介面包含資料輸入埠Dn、資料輸出埠、 CSI、DSI、CSO及DSO埠。如第4圖所示，用於每一記 憶體裝置的Dn、CSI、DSI輸入埠係分別連接至前一記憶 體裝置的Qn、CSO及DSO輸出埠。因此，記憶體裝置係 被彼此串聯連接，因爲每一記憶體裝置將命令及讀取資料 傳送至鏈中之下一記憶體裝置。 在第4圖之實施例的實際實施中，每一記憶體裝置係 被定位在印刷電路板上，使得在輸入及輸出埠間之距離及 信號軌最小化。或者，四個記憶體裝置可以實施在系統於 封裝（SIP )模組中，這進一步最小化軌長度。記憶體控 制器202及記憶體裝置204至210係被串聯連接以形成一 環形拓樸，表示最後記憶體裝置2 1 0提供輸出回到記憶體 控制器202。因此，熟習於本技藝者可以了解到，於記憶 體裝置2 1 0與記憶體控制器202間之距離容易最小化。 在第4圖之串聯記憶體系統200中之記憶體裝置的效 能顯著優於第1圖之先前技術系統中之記憶體裝置的效能 。例如，假定使用66MHz時鐘及串聯記憶體系統200包 含四個記憶體裝置，第4圖之串聯連接之記憶體裝置之一 的每一接腳資料率將約1 3 3Mbps。相反地，假定每一記憶 體裝置的讀取循環時間（tRC)及寫入循環時間（tWC) -20 - 200828338 係被額定爲約25ns時，第1圖之具有四記憶體裝置的多 投記憶體裝置每接腳資料率將約40MbPs。再者，串聯記 憶體系統200的功率消耗將相對於第1圖之先前技藝減少 。串聯記憶體系統200的效能及功率消耗優點主要是由於 沒有必須爲每一記憶體裝置所驅動的信號軌1 8。 第4圖之串聯記憶體系統200之顯著優點爲系統的可 縮放性。換句話說，四個以上之記憶體裝置也可以包含在 連接至記憶體控制器2〇2之記憶體鏈中’而不會有效能上 之劣化。相反地，因爲需要增加通道1 8的信號軌長度， 以容納這些額外之裝置，所以，第1圖之先前技術系統將 具有實際上之限制，其當愈來愈多記憶體裝置加入時，送 回的愈少。額外之接腳載入信號係爲該加入之裝置所貢獻 。如前所述，時鐘頻率必須減少，以確保當驅動一長通道 1 8時的資料傳輸完整性，這降低了效能。在第4圖之實 施例中，時鐘的分佈將被設計以容納大量之記憶體裝置， 並可以包含重覆器及平衡樹，以維持所有記憶體裝置的時 鐘完整性。熟習於本技藝者可了解，有若干方式以提供一 平衡時鐘信號。 雖然第4圖之串聯記憶體系統提供優於先前技術記憶 體系統之效能，但也可以藉由第5圖之另一串聯記憶體系 統實施例，來取得其他效能改良。除了並聯時鐘分佈設計 外，第5圖之串聯記憶體系統300係類似於第4圖之實施 例，另使用一電源同步時鐘設計。串聯記憶體系統300包 含一記憶體控制器3 02及四記憶體裝置3 04、3 06、3 0 8及 -21 - 200828338 3 10。記憶體控制器302包含時鐘輸出璋CKO#及CKO， 用以提供互補時鐘信號，及時鐘輸入璋CK#及CK，用以 接收來自系統之最後記憶體裝置的互補時鐘信號。記憶體 裝置係與第4圖所示者相同，除了它們現具有時鐘輸入埠 CK#及CK、及時鐘輸出埠CKO#及CKO外，其中爲一記 憶體裝置在CK#及CK璋所接收之時鐘係經由其CKO#及 CKO埠被提供給下一裝置。最後記憶體裝置3 10提供時 鐘信號回到記憶體控制器302。 第5圖之實施例的主要優點爲沒有複雜之時鐘分佈設 計及在記憶體裝置間之最小時鐘互連。因此’最小時鐘頻 率可以增加至166MHz，造成每一接腳最小之333Mbps資 料率。如同第4圖之實施例，第5圖之實施例可以被縮放 以包含任意量之記憶體裝置。例如，第五記憶體裝置可以 加至第5圖之實施例中，並簡單地連接記憶體裝置3 1 0的 輸出璋至第五記憶體裝置的對應輸入埠，並連接第五記憶 體裝置的輸出璋至記憶體控制器302。熟習於本技藝者可 以了解，記憶體控制器3 02可以包含簡單之相鎖迴路（ PLL)以維持時鐘頻率。 串聯記憶體系統200及3 00的架構可以靜態地固定若 千特定量之記憶體裝置。不同架構可以藉由簡單地調整在 串聯鏈中之記憶體裝置的數量，而設定用以提供不同記憶 體系統容量。在另一實施例中，具有不同容量之記憶體裝 置可以混合在該串聯鏈中’以對整個記憶體系統容量提供 更多彈性。在部份應用中’可以藉由對串聯鏈中加入或移 -22- 200828338 除模組，而將記憶體系統容量作動態調整，其中一模組可 以爲單一記憶體裝置、SIP記憶體、或具有記憶體裝置及 /或SIP記憶體裝置的PCB。 第6圖爲一方塊圖，顯示動態可調串聯記憶體系統實 施例。可調串聯記憶體系統400包含··一記憶體控制器 4〇2 ;固定記憶體裝置404、406、408及410 ;擴充鏈結 4 12 ' 414、416、418 及 420 ;及擴充模組 422、424 及 426。固定記憶體裝置404、406、408及410係被彼此串 聯連接至中介擴充鏈結，並至記憶體控制器402。每一擴 充鏈結係爲公或母耦接機構，用.以可釋放地接收及固持一 模組，其具有對應之母或公耦接機構。每一模組包含至少 一記憶體裝置，串聯地連接至擴充鏈結的終端。在所示例 子中，擴充模組422及426各個包含四個彼此串聯於模組 耦接機構的輸入連接器與輸出連接器間之記憶體裝置。模 組424包含兩記憶體裝置，串聯連接於其模組耦接機構的 輸入連接器與輸出連接器之間。因此，藉由將該模組*** 擴充鏈結，另外之串聯連接記憶體裝置可以動態地***於 固定記憶體裝置之間。例如擴充鏈結41 4及420的未使用 擴充鏈結將具有適當架構的跳線428及430連接至其上， 用以維持該鏈的連續串聯電氣連接。 可調串聯記憶體系統400可以包含任意數量之固定記 憶體裝置及擴充鏈結，及該記憶體模組可以被架構以包含 任意數量之串聯連接之記憶體裝置。因此，藉由簡單地將 新模組加入或以較大容量模組來替換現行模組，可調串聯 -23- 200828338 記憶體系統400具有全記憶體容量上完全之可擴充性，而 不會衝撃整體效能。並不必要改變記憶體控制器，因爲相 同通道係被散佈有另外之串聯連接記憶體裝置，及熟習於 本技藝者將了解，如何連接並聯控制信號，如CE#、 RST#及電源供給至所***之模組。在模組被***後，或 模組移除後，記憶體系統400再啓動，使得記憶體控制器 可以自動設定用於系統之記憶體裝置中之裝置的ID。 % 示於第3A至3C及4至6圖中之串聯記憶體系統使 用記憶體裝置，例如快閃記憶體裝置，具有相容之串聯輸 入/輸出介面。具有串聯輸入/輸出介面之快閃記憶體裝 置例係描述於共同受讓人之申請於2005年十二月30曰之 美國專利申請第1 1/324,023號案中。因此，示於第3A至 3C及4至6圖中之實施例的記憶體裝置可以使用在該些 專利申請案之快閃記憶體裝置。然而，描述於這些專利申 請案中之串聯輸入/輸出介面係爲可以使用之串聯介面的 • 例子。任意之可以促成在記憶體裝置間之串聯操作的串聯 輸入/輸出介面也可以使用，只要其架構以接受一預定命 令結構即可。 依據另一實施例，串聯輸入/輸出介面可以以任意類 型記憶體裝置加以使用。更明確地說，其他記憶體類型也 可以適用以串聯輸入/輸出介面一起操作。第7圖爲一般 記憶體裝置的槪念組織方塊圖，其具有適用於第3 A至3 C 與4至6圖之串聯記憶體系統的本地核心及串聯輸入/輸 出介面。記憶體裝置500包含一本地記憶體核心，其包含 -24- 200828338 記憶體陣列排502及504，及本地控制與I/O電路5 06， 用以存取記憶體陣列排502及504。熟習於本技藝者可以 了解，記憶體陣列可以組織爲單一記憶排或兩個以上之記 憶排。本地記憶體核心可以爲DRAM、SRAM、NAND快 閃、或NOR快閃記憶體爲主。當然，任何新出的記憶體 及其對應控制電路均可以使用。因此，取決於本地記憶體 核心的類型，電路方塊506可以包含錯誤檢測邏輯、高壓 產生器、更新邏輯及任何其他電路方塊，以執行有關記憶 體類型所需之操作。 典型地，記憶體裝置使用命令解碼器，用以回應於藉 由主張內部控制信號所接收之命令，而啓始相關電路。它 們將包含已知I/O電路，用以接收及閂鎖資料、命令及位 址。依據本實施例，現行I/O電路係被以串聯電路及控制 邏輯方塊508替換。在本例子中，串聯介面與控制邏輯方 塊 508 接收 RST#、CE#、CK#、CK、CSI、DSI 及 Dn 輸 入，並提供Qn、CSO、DSO、CKO、及CKO#輸出，這些 配合於第5圖所示之記憶體裝置的輸入及輸出璋。 串聯介面與控制邏輯方塊508負責各種如於美國專利 第1 1/3 24，023號案所述之功能。串聯介面與控制邏輯方 塊5 08的功能爲設定一裝置識別號、傳送資料至下一串聯 連接記憶體裝置、及解碼所接收之命令，用以執行本地操 作。此電路可以包含一命令解碼器’其回應於相關於本地 命令的串聯接收命令，替換該本地命令解碼器，該本地命 令解碼器係架構以主張本地命令解碼器將主張的相同控制 -25- 200828338 信號。當記憶體裝置串聯連接時，命令組可以擴充以執行 爲記憶體控制器所用之特性。例如，狀態暫存器資訊可以 被要求以評估記憶體裝置的狀態。 因此，第3A至3C與4至6圖之串聯記憶體系統可 以包含記憶體裝置類型之混合，每一類型有所不同，這對 於較大系統係有利的。例如，高速之DRAM記憶體可以 用以快取操作，而非揮發之快閃記憶體可以用於大量資料 儲存。不管所使用之記憶體裝置的類型爲何，各個記憶體 裝置係可個別定址以作動一命令，因爲串聯介面與控制邏 輯方塊506係架構以依據預定協定接收命令。 依據另一實施例，這些命令包含命令封包’其係具有 一模組化命令結構，其係用以控制串聯記憶體系統之個別 記憶體裝置。在提議之命令結構中，特定命令可以在不同 時間發出給一記憶體裝置成爲個別命令封包。一命令封包 可以啓始第一記憶體排的特定操作，及當核心操作被執行 時，一次後續命令封包可以然後被接收以回應於該第一命 令封包，啓始第二記憶體排的另一操作。其他命令封包也 可以被接收以類似於交錯方式，完成第一記憶體排及第二 記憶體排的操作。這稱爲在記憶體裝置中之執行同時發生 之操作。在討論同時發生之操作前，將解釋模組化命令協 定。模組化命令協定的細節係在申請於2007年三月2曰 之美國專利申請第60/892,705號名爲“記憶體系統中之模 組化命令結構與其用途”中作描述。 命令封包600具有如第8圖所示之結構，並包含三欄 -26- 200828338 位，其中兩個爲取決於由記憶體控制器發出之特定命令加 以選用。第一欄位爲強制欄’其係爲命令欄602。第一選 用欄爲一位址欄604’及第二選用欄爲資料欄606。 該命令欄602包含兩次欄，第一爲裝置位址（DA) 欄608及第二爲oP-碼（〇P碼）欄610。裝置位址欄608 的長度可以是任意數量之位元，並用以定址在系統中之每 一記憶體裝置。例如’長度1位元組之裝置位址欄608可 以足夠定址256個記憶體裝置。一位址可以保留同時定址 所有記憶體裝置，用以廣播一操作。在另一實施例中，裝 置位址欄608可以包含一裝置類型欄，以指明有關op-碼 欄6 1 0有關之記憶體裝置的類型。例如，裝置類型欄可以 指定DRAM、SRAM或快閃記憶體。op-碼欄610的長度 可以任意數量位元，以代表用於任意數記憶體裝置的命令 ，並可以包含排位址。例如，快閃記憶體命令組將具有與 DRAM命令組不同之命令，因此，如果記憶體系統包含兩 類型之記憶體裝置，則op-碼欄將被架構以容許來自兩命 令組的所有可能命令。取決於爲該op-碼所指定之操作類 型，位址欄604係用以提供一記憶體陣列的列位址（列 Addr)或行位址（行Addr)。資料欄606將包含任意量 之予以寫入或規劃入記憶體裝置的位元資料因此，該命令 封包600將在大小上有所變化，因爲對於一特定操作，可 能不需要寫入資料，及對於一特定操作，可能不需要位址 及寫入資料。 第9圖出可以用以操作具有第7圖所示之架構的快閃 -27- 200828338 記憶體裝置的例示命令封包’以用於前述之串聯記憶體系 統中。第9圖中之位元組位置對應於爲記憶體裝置所依序 接收的順序。命令欄602佔用第一及第二位元組位置，其 包含裝置位址（DA )作爲第一位元組資訊，及對應於該 操作之op-碼作爲第二位元組資訊。位址欄604可以包含 三位元組之列位址（RA )，佔用第三至第五位元組位置 ，但用於其他命令則可以縮短，以包含兩位元組行位址（ CA )，只佔用第三及第四位元組位置。對於具有兩位元 組行位址之命令，資料欄606將佔用第五位元位置至第 2 1 1 6位元位置，如果資料有該長度的話。資料可以佔用 更少或更多位元組位置。 由記憶體控制器所發出之任何命令封包600將爲系統 中之各個記憶體裝置所串聯接收，只有具有裝置位址包含 命令欄602的DA次欄608的記憶體裝置被作動該〇1>_碼 次欄6 1 0。否則，命令封包係傳送經該記憶體裝置並至該 鏈中之下一記憶體裝置。因爲op-碼爲特定於一特定操作 ，所以，記憶體裝置，即記憶體裝置500之串聯介面與控 制邏輯方塊508將控制命令封包的閂鎖位址及/或資料資 訊所需之電路。例如，如果一頁讀取命令封包爲指定記憶 體裝置所接收’則指定記憶體裝置將解碼該op-碼並控制 適當電路，以閂鎖以下的三個位元組列位址。 歹！J於第9圖之例示命令封包係有關於快閃記憶體操作 。具有不同操作之任意類型記憶體裝置的一組命令封包可 以架構以遵循所述之命令結構。 -28- 200828338 如前所述之命令封包可以較佳地用於執行記憶體裝置 ，例如第7圖之記憶體裝置500中之同時發生操作。如果 記憶體裝置500被架構以獨立存取任一排，則可以在該記 憶體裝置內，實質執行同時發生之操作。獨立存取表示不 同記憶體排的核心操作可以彼此獨立地操作。此一記憶體 裝置例係描述於前述美國專利申請第 n/324,023號案中 。核心操作表示一邏輯或功能操作，其不會被中斷，因爲 核心操作的完成可以取決於在狀態機或其他邏輯控制下所 執行之特定事件的順序。 同時發生操作將增加系統的效能，因爲記憶體控制器 在送出用於第二操作的命令封包前，不需要等待，直到該 記憶體裝置完全完成第一操作爲止。在傳統NAND快閃記 憶裝置中，記憶體裝置將不接受另一命令，或反應於不同 記憶體排的接收命令，直到核心操作完成現行記憶體排爲 止。因此，該記憶體裝置在接受另一命令前，將串聯執行 幾個操作。在本實施例的同時發生操作中，一命令封包將 啓始一記憶體排中之操作，及在核心操作被執行用於第一 記憶體排的同時，——後續命令封包將立即啓始相同記憶體 裝置中之第二記憶體排的另一操作。因此，兩操作將幾個 同時爲兩記憶體排所執行。 第1 0圖爲一流程圖，顯示例如記憶體裝置500之記 憶體裝置中，執行同時發生操作的方法，該記憶體裝置係 被架構以獨立地存取其記憶體排。在步驟700開始，第_ 命令爲記憶體控制器所發出並爲記憶體裝置所接收。第_ -29- 200828338 r 命令可以是前述之在第9圖所示之任一命令封包。一旦整 個封包（命令欄、位址欄及資料欄）被接收，則核心操作 將在步驟702開始記憶體裝置的第一記憶體排。幾乎與第 一記憶體排核心操作開始同時，一第二命令係爲§3憶體控 制器所發出並爲記憶體裝置所接收，如步驟704所示。 在步驟706，第二記憶體排的核心操作係回應於第二 命令加以執行。最後，屬於第一命令的所資訊將在步驟 # 708提出。所得資訊可以包含狀態資訊或讀取資料，其係 回應於一補充讀取命令封包加以提供。狀態資訊提供一例 如規劃或抹除操作之特定類型操作的成功或失敗的指示， 並由相關於該記憶體排的狀態暫存器回應於由記憶體控制 器所出之補充“讀取狀態”命令封包加以讀取。讀取資料係 回應於一補充“叢發（burst)讀取”命令封包加以提供。參 考第1圖，讀取操作的核心操作將包含自該記憶體排的一 方塊輸出一頁資料至資料暫存器方塊32。爲了自資料暫 ® 存器方塊32讀出資料，執行一叢發讀取操作。在步驟 7 1 〇，將提供屬於第二命令之所得資訊。來自兩記憶體排 的所資訊最後送回記憶體控制器。第1 〇圖之實施例例示 兩記憶體排的同時發生操作，但該方法可應用於該記憶體 裝置的兩或更多記憶體排的同時發生操作。 第1 1至1 5圖爲序向圖，顯示於美國專利申請第 1 1 /3 24,023號中所述之快閃記憶體裝置所執行之可同時發 生的操作。第1 1至1 5圖顯示用於第4或5圖之一記憶體 裝置在時間上之CSI、Dn、DSI及Qn的信號軌跡。所示 -30- 200828338 的順序係想要顯示於信號間之相對時序，而不是限制至特 定時序値。應注意的是，命令選通輸入CSI係爲記憶體控 制器所產生並作爲該記憶體控制器所組合及出之命令長度 的指示符。例如，如果被發出之命令封包長度爲兩位元組 ，則對應CSI具有對應於命令的第一位元之一作動緣（在 此例爲上升緣），及對應於命令封包最後位元的不作動緣 。CSI信號控制記憶體裝置命令暫存器，以閂鎖該命令資 料。資料選通輸入信號DSI也爲記憶體控制器所產生，並 作爲記憶體控制器所提供之資料長度的指示符。例如，如 果爲記憶體控制器所要求之讀取資料長度爲八位元組，則 爲記憶體控制器所產生之對應DSI將具有對應於讀取資料 的第一位元的作動緣，及對應於讀取資料的最後位元之不 作動緣。當已知發出命令位元長度及所要求之讀取資料位 元長度時，CSI及DSI係爲記憶體控制器所產生。 第11圖爲一時序圖，顯示兩不同排的記憶體裝置的 同時發生讀取操作。當CSI在高邏輯位準時，一用於排0 之頁讀取命令封包800係爲記憶體裝置所閂鎖。如第9圖 所示，頁讀取命令包含兩位元組命令及三位元組列位址。 排〇之記憶體裝置將在CSI落在低邏輯位準後，在時間 t〇，開始執行被指定列位址的讀取操作。例如，一快閃記 憶體裝置的讀取操作將包含字元線的作動，例如在第1圖 之WLi，並感應BL0至BLj的位元線資料。最後，所感 應資料被閂鎖或儲存於資料暫存器方塊3 2。在一實施例 中，一頁讀取命令封包800被經由其Qn輸出埠傳送至下 -31 - 200828338 一記憶體裝置。在另一實施例中，頁讀取命令封包800係 被禁止傳送至其他記憶體裝置。例如，提供在Qn輸出的 頁讀取命令封包800可以在被閂鎖至命令暫存器時被設定 爲零値。這將保存電力，因爲並不需要信號線的軌至軌信 號切換。 當CSI在高邏輯位準時，用於排1之頁讀取命令封包 802係爲記憶體裝置所閂鎖。在CSI落入低邏輯位準後， φ 排1之記憶體裝置將開始執行用於指定列位址之讀取操作 。在特定數量之時鐘循環後，資料係在時間t2準備由排〇 讀出。爲了由排〇讀出資料，記憶體控制器發出一叢發讀 取命令封包804，當CSI在高邏輯位準時，其係被接收與 閂鎖。如第9圖所示，叢發讀取命令封包將包含資料所讀 取之行位址。在對應於命令封包804之CSI落在低邏輯位 準後，DSI將上升至高邏輯位準，以致能Qn輸出璋緩衝 器，藉以提供用於排〇之輸出資料係爲讀取資料封包806 φ 。在使用第1圖之例子中，在Qn輸出緩衝器上之資料輸 出可以對應於自資料暫存器方塊32讀出之資料，由在叢 發讀取命令封包804中所指定之行位址開始，並在DSI落 在低邏輯位準時結束。當輸出排〇之輸出資料的最後位元 時，用於排1之資料將在時間t3被準備讀出。在DSI落 在低邏輯位準時，用於排1之叢發讀取命令封包808爲記 憶體裝置所接收與閂鎖。在用於叢發讀取命令封包808之 CSI的下降緣後，DSI係被再次驅動至高邏輯位準，一預 定持續時間，以在Qn輸出埠上，輸出來自排1的讀取資 -32 - 200828338 料作爲讀取資料封包8 1 0。 因爲在to及t2間之排0的核心操作與在tl及t3間 之排1之核心操作係實質同時發生並彼此重疊’所以’兩 讀取操作的總核心操作時間爲時間t0及t3之間。在先前 技藝中，兩核心操作依順序執行，這表示回應於第二頁讀 取命令封包排1之核心操作開始，該第二頁讀取命令封包 係在t2之排0的核心操作完成後被接收。如前所示之執 行同時發生操作的效能優點係爲熟習於本技藝者所知。 第12圖爲一時序圖，其中顯示兩不同排之記憶體裝 置的同時發生操作。由此點注意，在記憶體裝置之Dn輸 入埠所接收之命令封包係被傳送至其Qn輸出璋’其係在 第1 1至1 5圖之Qn信號軌所示。爲了規劃一記億體排， 規劃資料係根據一特定行位址被載入至記憶體裝置的資料 暫存器，然後規劃入特定列。在第12圖中，用於排〇之 叢發資料載入命令封包820係與規劃資料一起接收，其後 立即有一頁規劃命令封包822。當CSI在高邏輯位準時， 命令封包820及822均被閂鎖。在頁規劃封包822被閂鎖 並爲記憶體裝置所解碼後，用以規劃資料至排〇之核心操 作開始於時間t0。現在，用於排1之叢發資料載入命令封 包824係與規劃資料一起接收，隨後立即有一頁規劃命令 封包826。在頁規劃封包826被閂鎖並爲記憶體裝置所解 碼後，用於對排1規劃資料之核心操作開始於時間tl。 如果想要話，記憶體控制器也可以藉由發出一讀取狀 態命令封包828要求記憶體裝置的狀態。這將存取記憶體 -33- 200828338 裝置的狀態暫存器，當DSI於高邏輯位準時，記憶體裝置 之資料將被輸出於Qn輸出埠上作爲讀取資料封包83 0。 熟習於本技藝者可了解，當執行內部操作時，狀態暫存器 記憶體裝置所內部更新。在本例子中，讀取資料封包830 將指示對排〇的規劃已經完成。一後續發出之讀取狀態命 令封包832將造成讀取資料封包834提供狀態暫存器的値 ，這可以對排1之規劃已經完成。再次，因爲排0至排1 φ 之核心規劃操作實質同時發生並重疊，因而，相較於續兩 排的依序規劃時，可以節省很多之時間。 第1 3圖爲一時序圖，顯示記憶體裝置的兩不同排之 同時發生讀取與規劃操作。用於排〇之頁讀取命令封包 840係爲記憶體裝置所閂鎖，其後跟有一用於排1之叢發 資料載入開始令封包842，其後再跟隨有用於排i之頁規 劃命令封包844。在時間t0，用以讀取資料的核心操作由 排〇開始，而在時間11中，用以規劃資料的核心操作由 Φ 排1開始。因爲排〇之頁讀取操作的核心操作被首先啓始 ，所以當用以規劃排1資料的核心操作正進行時，資料將 會在時間12完備。因此，一叢發讀取命令封包8 4 6被接 收，及DSI被主張以輸出在讀取資料封包848，輸出自排 0讀取之資料。在DSI被解除以結束自排〇讀出之資料輸 出後，可以發出一讀取狀態命令封包850，以檢查排1的 規劃狀。因爲排1應已在時間t3完成規劃操作，所以 再次主張D S I並且讀取資料封包8 5 2被提供在Qn輸出璋 ，對排1表示規劃操作的通過或失敗狀態。 -34- 200828338 第1 4圖爲一序向圖，顯示記憶體裝置的兩不同排的 同時發生方塊抹除。用於排〇之方塊抹除位址輸入命封包 860係爲記憶體裝置所閂鎖，並爲用於排0之抹除命令封 包8 62所跟隨。在閂鎖抹除命令封包862後，在時間t0， 用於排〇的核心操作開始。現在用於排1之方塊抹除位址 輸入命令封包864係爲記憶體裝置所閂鎖，其跟隨有用於 排1之抹除命令封包866。在閂鎖抹除命令封包866後， 用於排1之核心操作再次於時間tl開始。方塊抹除位址 輸入命令與抹除命令的結構係如第9圖所示。如果用於排 〇之抹除操作應在時間t2完成及排1之抹除操作應在時間 t3完成，則分開之讀取狀態命令封包868及870可以被發 出並爲記憶體裝置所閂鎖。對應之讀取資料封包872及 874係被提供在記憶體裝置的Qn輸出璋上，每個提供狀 態暫存器之値。 在第11至14圖之時序圖中，已經顯示不同組合之同 時發生操作。描述於前述實施例之模組化命令封包結構的 優點爲不同命令封包可以在不同時間發出。如前所示’一 叢發資料載入命令封包係爲一頁規劃命令封包所跟隨。然 而，這並不是完全必然的，及如果想要的話，頁規劃命令 封包可以隨後發出。當命令封包係配合命令選通信號CSI 及資料選通信號DSI的組合一起使用時，更實現進一步優 點，即爲能懸置記憶體裝置操作之能力。如前所述，csi 選通信號係爲記憶體控制器所提供’用以表示在Dn輸入 埠上之命令資料係予以爲命令暫存器所閂鎖’並可以具有 -35- 200828338 對應於被發出之命令封包長度的持續時間。因爲用以規劃 一記憶體排的輸入資料及自一記憶體排讀出之輸出資料可 以長度上超出1 000位元組，所以，熟習於本技藝者可以 了解到，用以輸入或輸出此數量之資料時，需要相當長的 時間。依據本實施例，CSI及DSI選通信號可以在規劃資 料被載入或讀取資料被輸出時被預先解除，並在隨後時間 回復。 φ 第1 5圖爲一序向圖，顯示兩不同排之記憶體裝置的 同時發生規劃及讀取操作，及懸置與回復操作。用於排1 之叢發資料載入開始命令封包880係被閂鎖，及在命令封 包之資料欄中之資料酬載係爲記憶體裝置所閂鎖。在時間 t〇，當記憶體控制器解除CSI時，載入記憶體裝置的資料 係被懸置。在本例子中，只有2 5 6位元組的資料被記憶體 裝置所閂鎖，其係爲記憶體控制器所追蹤。用於排0之頁 讀取命令封包882係被閂鎖，及用於排0之核心操作於時 # 間tl開始。當接收到用於排1之叢發資料載入命令封包 時，命令封包880之懸置資料載入操作在時間t2回復。 在命令封包884之資料欄中之資料酬載包含未被閂鎖的保 留之1856位元組資料。隨後的是，用於排1之頁規劃命 令封包886，及用於排1之規劃資料的核心操作在時間t3 開始。最後，用於排〇之核心操作將在時間t4完成，及 用於排〇之叢發讀取命令封包888係爲記憶體控制器所發 出並爲記憶體裝置所閂鎖。當DSI爲高邏輯位準時，讀取 資料然後輸出爲資料讀取封包890。 -36- 200828338 然而，因爲予以輸出大量資料，所以主機系統可以想 要對排1確認規劃完成，因爲控制器將知道規劃操作應於 預定時間內完成，例如時間t6。在發送讀取狀態要求前， 不同於等待所有予以輸出之讀取資料，讀取資料的輸出可 以藉由解除DSI，懸置在時間t5。一旦資料輸出操作被懸 置，一讀取狀態命令封包892係爲記憶體控制器所發出並 爲記憶體裝置所閂鎖。然後，提供有包含有狀態暫存器値 的對應讀取資料封包894。在DSI於讀取資料封包894的 末端解除時，可以回復叢發讀取。這係藉由令記憶體控制 器發出用於排〇之叢發讀取命令封包896加以完成，這將 包含在時間t5懸置讀取前，予以輸出之下一位元的位址 。在時間t7，剩餘1600位元組係由Qn輸出埠所輸出， 作爲讀取資料封包8 9 8。 第1 5圖之懸置操作例顯示用以執行同時發生操作之 模組化命令結構的優點，各個操作可以被懸置及回復’以 最大化核心利用率及通道的利用。 第1 1至15圖之例示序向與操作取決於CSI及DSI選 通信號，以提供有關命令封包或讀取資料封包的資訊。因 爲命令封包在大小上爲可變，所以，沒有信頭資訊用以表 示命令封包的位元長度，CSI選通信號作動爲用於命令封 包的一信頭，該命令封包係並聯於資料命令封包加以提供 。用於命令封包的長度的CSI信號爲作動的，並爲記憶體 裝置所用以閂鎖出現在Dn輸入埠的命令封包資料至適當 的暫存器。DSI信號在期待讀取資料封包的長度時爲作動 -37- 200828338 的，這係爲記憶體控制器所知，並與讀取資料封包並聯行 進。因而，作動DSI信號作動爲讀取資料封包的信頭。因 此，命令封包與讀取資料封包的長度對應於其個別CSI及 DSI選通信號的長度。 因爲讀取貧料封包及命令封包丫了經連接在鄰接記憶體 裝置的Dn及Qn埠間之相同信號線，所以，具有資料的 CSI選通的出現指定資料爲命令資料封包，而具有資料的 DSI選通的出現指定資料爲讀取資料。因此，選通信號指 出行經記憶體系統的資料類型。記憶體控制器將追蹤其發 出之DSI選通，使得其可以匹配所接收之讀取資料封包與 期待之資料類型。例如，讀取資料封包可以包含狀態暫存 器資訊或自記憶體陣列讀出之資料。 針對CSI及DSI信號的功能相關性，最小分開時間係 被***於任一類型之後續選通信號間。這係用以確保每一 命令封包及讀取資料封包爲可區分與定義，及確保適當類 型之資料係爲記憶體控制器的記憶體裝置所閂鎖。使用分 開有四種可能狀態。有CSI-至- CSI分開（tccs ) 、CSI- 至-DSI 分開（tCDS ) 、DSI-至- CSI 分開（tDCS )及 DSI- 至-DSI 分開（tDDS)。 CSI-至-CSI分開（tccs)爲至相同或不同裝置之連續 命令封包間之時鐘週期（tCK )中之最小分開時間。此分 開時間允許前一命令予以由該記憶體裝置清除，藉由清除 該命令暫存器及重置任一命令邏輯，例如在準備新命令時 。DSI-至-DSI分開（tDDS )爲至相同裝置之連續讀取資料 -38- 200828338 封包間之準備時鐘週期（tCK)中之最小分開時間。此分 開時間允許輸出緩衝器電路在準備予以輸出下一資料時重 置。DSI-至-CSI分開（tDCS )爲對相同或不同裝置之讀取 資料封包與後續命令封包間之時鐘週期（t c κ )中之最小 分開時間。CSI-至-DSI分開（tCDS)爲相同裝置之命令封 包與讀取資料封包間之時鐘週期中之最小分開時間。這兩 分開時間確保適當資料類型爲記憶體裝置所閂鎖，因爲兩 種可能連續出現在記憶體裝置的Dn輸入埠內。因爲記憶 體控制器發出CSI及081信號與知道命令封包或資料位元 長度，所以，這確保命令封包與資料封包本身係爲相同的 最小時間所分開作爲選通信號。 這些分開時間的例子係在第1 1至1 4圖中被標示出， 應注意最小分開時間可以爲時鐘的一資料閂鎖，取決於被 使用之資料率架構，其可以爲一時鐘週期的分數。例如， 在資料被閂鎖於時鐘的上升緣的單一資料率架構（SDR ) 中，最小分開時間將爲一時鐘循環或週期。在資料被閂鎖 於鐘的上升緣及下降緣的雙倍資料率架構（DDR)中，最 小分開時間將爲一時鐘週期的〇. 5。第1 1至1 5圖爲單一 記憶體裝置中之同時發生操作例，並未清楚顯示CSI-至 -DSI分開或DSI-至-CSI分開的相關性。第16圖爲一序向 圖，顯示CSI-至-DSI或DSI-至-CSI分開的相關性。 第1 6圖爲一例示狀況，其中第一記憶體裝置自其Qn 輸出埠輸出其讀取資料及第二串聯連接記憶體裝置在讀取 資料由第一記憶體裝置輸出後接收一命令封包。在此例子 -39 - 200828338 中所表示之該兩記憶體裝置可以例如對應於第4及5圖所 示者。用於 DSI一 1、CSI—1、DS01、CSO —1 及 Qn—1 埠之 信號軌跡係被顯示用於第一記憶體裝置，而附接之“ _1，，表 示第一記憶體裝置的埠。用於DSI —2、CSI —2及Dn —2埠 之信號軌跡係被顯示用於第二記憶體裝置，而附接之“_2，， 表示第二記憶體裝置的埠。假設第一記憶體裝置已經事先 接收一或多數命令封包，用以由其中讀取之資料。結果， DS_1接收選通信號900，用以輸出資料至Qn_：i埠上作爲 讀取資料封包902。讀取資料封包902被標示爲“Qn_l讀 取資料”。因爲讀取資料及選通信號被由第一記憶體裝置 串聯地傳送至第二記憶體裝置，所以 DSO_l傳送自 DSI_1埠接收的選通信號至第二記憶體裝置的DSI_2埠。 同樣地，讀取資料封包902係自第一記憶體裝置的Qn_i 璋傳送至第二記憶體裝置的DN_2埠。 記憶體控制器發出一定址至被標示爲“Dn_2 CMD資 料”的第二記憶體裝置命令封包904，其後有一隨附CSI 選通信號906。選通信號906經由CSI_1被傳送經第一記 憶體裝置及命令封包被經由該第一記憶體裝置（未示於第 16圖）的Dn輸入埠傳送並經由Qn_l輸出埠傳出。第一 記憶體裝置將忽略命令封包904，因爲其係針對第二記憶 體裝置。第一記憶體裝置然後由其CS〇_l埠傳送選通信 號906至第二記憶體裝置的CS_2璋，並經由其Qn_l輸 出璋傳送命令封包904至第二記億體裝置的Dn_2輸入埠 。因爲在選通信號900之下降緣與選通信號906之上升緣 -40- 200828338 間有最小分開tCDS，及在讀取資料封包902之最後位元與 命令封包904之第一位元間有最小分開，所以，第二記憶 體裝置將可靠地閂鎖命令封包904於適當之暫存器中。另 一方面，如果命令封包904及其對應選通信號90 6被發出 沒有任何分開tCDS，則第二記憶體裝置可以閂鎖讀取資料 封包9 02的讀取資料位元成爲命令封包904的一部份。因 此，最小分開確保沒有資料類型的混合。 在前所描述之記憶體系統中之記憶體裝置，特別是非 揮發記憶體裝置具有的優點爲當沒有電力供給至記憶體裝 置時，其能保持所儲存之資料。然而，於全功率操作與完 全沒有電力或省電位準間之轉移可能危及所儲存資料的完 整性。 第1 7 A圖顯示本發明實施例可以應用之快閃記憶體 裝置。參考第17A圖，一快閃記憶體1010包含：例如控 制電路1 0 1 2之邏輯電路，用以控制快閃電路的各種操作 ;及一位址暫存器l〇12a，用以儲存位址資訊；一資料暫 存器1012b，用以儲存規劃資料資訊；一命令暫存器 1012c，用以儲存命令資料資訊；高壓電路，用以產生所 需之規劃及抹除電壓；及核心記憶體電路，用以存取記憶 體陣列1014。該控制電路1012包含一命令解碼器及邏輯 ，用以執行內部快閃操作，例如讀取，規劃及抹除功能。 熟習於本技藝者可以了解，這些操作係可以回應於儲存於 命令暫存器1012c中之命令資料加以執行，有時配合儲存 於個別位址暫存器1012a及資料暫存器1012b之位址資料 -41 - 200828338 及規劃資料，這係取決於予以執行之操作而定。命令資料 、位址資料及規劃資料係爲一記憶體控制器所發出並爲快 閃記憶體1 〇 1 2所閂鎖入對應暫存器中。快閃記憶體1 0 1 0 之所示電路方塊功能係爲本技藝所知。熟習於本技藝將了 解，示於第1圖中之快閃記憶體1 0 1 0代表很多可能架構 中之一可能快閃記憶體架構。 對於快閃記憶體1 0 1 0之適當操作，暫存器儲存位址 、資料及命令資訊必須可靠。一儲存於暫存器中之不當値 造成裝置故障。例如，變化之電壓可能使得暫存器隨機改 變儲存於命令暫存器10 12c中之資訊的狀態，可能造成對 應於接收規劃或抹除命令之位元圖案。在此例子中，一虛 僞規劃操作將使得在資料暫存器1012b中之隨機資料予以 規劃至記憶體陣列1014之位址暫存器1012a中之隨機位 址。如果資料存在於此位址，則對應於該位址之記憶體單 元將受到規劃電壓，及其臨限電壓將改變。一虛僞抹除操 作可能造成在記憶體陣列1 0 1 4中之存在資料的抹除。因 爲記憶體控制器不知爲快閃記憶體1010所執行之虛僞操 作，所以遺失之資料不可回復。 快閃記憶體1 〇 1 0之暫存器典型被以具有兩穩態之正 反器電路構成。D型正反器爲本技藝中已知，如第17圖 所示。D型正反器1 0 5 0具有D輸入’用以接收輸入資料 D_IN，其係被內部閂鎖在時鐘信號CLK之作動緣，例如 CLK之上升緣。當閂鎖時，Q-輸出將提供對應於D_IN邏 輯狀態的D_OUT，而互補Qb輸出將提供對應於D_IN邏 -42 - 200828338 輯狀態反相的D —OUTb。一重置輸入清除閂鎖’而信號 RESET係在作動位準，例如Vss或地端。每一正反器電路 儲存一位元資料，及命令暫存器l〇12c將包含多數正反器 電路。如同爲熟習於本技藝所知，正反器電路可以包含一 對交叉連接之反相電路。 第18圖顯示在典型快閃記憶體1010中之供電與斷電 操作時之電壓源vcc、低態有效邏輯位準重置信號RST# 、及低態有效邏輯位準晶片致能信號CE#。在一典型供電 操作中，在導通時間t0N，電源電壓Vcc由低GND或Vss 電壓位準轉移至高Vcc電壓位準。Vcc電壓位準上升及在 時間tST到達穩定電壓位準VST，在此時，快閃記憶體 1010可以操作。最後，在時間tv，Vcc電壓位準到達最大 値Vcc位準。該裝置重置及致能信號RST#及CE#分別由 一相關記憶體控制器接收，並在時間t0N同時被驅動至不 作動之高邏輯位準，但跟隨Vcc的上升電壓。一旦RST# 解除，或在不作動之高位準，則裝置爲“準備”狀態，並可 操作以自該記憶體控制器接收命令。或者，在裝置於重置 狀態的同時，控制器藉由將其驅動至不動高邏輯位準而在 時間t0N解除CE#信號。因爲Vcc上升至最小電壓位準， 所以，CE#將跟隨VCC升壓。在時間tCEOff，CE#信號可以 被主張以允許裝置進入正常執行狀態。此時間tCEOif發生 在RST#信號已解除或驅動至不作動高邏輯狀態後（即在 時間tv後），經過至少tCE#的時間間距後發生。一旦裝 置進入正常執行狀態，啓始操作可以以裝置位準及系統位 -43- 200828338 準執行。然而，在vcc轉移時間，即由時間t〇N轉移至時 間tv間，或至少到時間tST，至暫存器的控制信號不能被 精確地控制。這可能造成虛僞資訊被儲存在快閃記憶體 1010之各種暫存器中，而造成不當規劃或抹除資料，造 成快閃記憶體1 〇 1 0中之資料完整性之損失。 由於在電力轉移時，發生之不自願規劃/抹除操作， 所造成之資料完整性之損失，在本世代的快閃記憶體裝置 中加劇，本世代記憶體裝置需要速度、尺寸減縮、及想要 低功率消耗，這需要快閃裝置經常地操作於較低之Vcc電 壓位準。較低之vcc位準放大了有關虛僞資訊被儲存於快 閃裝置之各暫存器中之問題，因而，不利地影響資料可靠 度。 本案描述在非揮發記憶體裝置之電力轉移時，例如供 電操作或斷電操作時之資料保護方法。在主張任何電力轉 移前，一重置信號被主張，以去能記憶體裝置的功能。在 裝置電壓期待穩定時，重置信號被維持一預設時間。在此 時間，所有內部暫存器，例如裝置之命令暫存器係被設定 至預設値，藉以防止由於裝置所執行之虛僞/抹除命令所 造成之資料損失。 第1 9圖爲依據本發明實施例之非揮發記憶體裝置中 之供電及斷電操作中，電壓源Vcc、低態有效邏輯位準重 置信號RST#、及低態有效邏輯位準晶片致能信號CE#。 如前所述，在時間，Vcc電壓由低GND或Vss電壓位 準轉移至高VCC電壓位準。或者，Vcc電壓位準可以由低 - 44- 200828338 功率位準轉移至vcc電壓位準。在時間上，Vcc電壓位準 上升及在時間tST超出一快閃記憶體1 〇 1 〇可以操作之穩 定電壓位準VST。最後，在時間tv時’ Vcc電壓位準到達 最大vcc位準。然而，爲了防止裝置由於虛僞資訊被閂鎖 入命令暫存器而故障，一例如有關於該非揮發記憶體裝置 的記憶體控制器之控制器保有RST#信號在低態有效邏輯 位準，以去能裝置的所有功能一等待時間週期，其至少爲 Vcc電壓位準到達穩定VST電壓位準所花用之時間（時間 t0N至tST)。如第19圖所示之實施例中，RST#信號係被 保持在低態有效邏輯位準一延長時間週期tRST (由時間 t〇N至tST)加上在Vcc位準到達穩定電壓位準VST後的至 少一時間間距U。當RST#信號係在低態有效邏輯位準時 ，所有裝置的內部暫存器將因此保持在一預設或重置狀態 〇 最後，控制器將在時間間距tRST後解除RST#，如第 19圖所示。在此時，電力將穩定及裝置元件可以準備或 啓始操作。或者，當裝置在重置狀態中，在時間t0N，控 制器藉由將其驅動至不作動之高邏輯狀態，而解除CE#信 號。因爲VCC爲上升至其最大電壓位準，所以CE#將跟隨 VCC上升。CE#信號在時間tCEOff被主張，以允許裝置進 入一正常執行狀態。時間tCEOff在至少t2的時間間距後發 生，在RST#信號被解除後，或驅動至不作動之高邏輯位 準後。一旦裝置進入正常執行狀態，啓始操作可以被執行 於裝置位準或系統位準。在功率轉換操作時，令裝置保持 -45 - 200828338 於一重置狀態一預定量的時間，防止了虛僞資訊被儲存或 閂鎖至裝置的各暫存器上。該裝置因此被保護對抗不當及 不小心之規劃或抹除資料，確保在功率轉換時的資料完整 〇 一類似程序確保資料保護可以在斷電操作時加以跟隨 ，藉由當vcc被關閉及驅動至低GND或Vss電壓位準時 ，在預定時間，在t0FF前，主張1^丁#，或驅動1187#至低 態有效邏輯位準。 一流程圖，顯示在非揮發記憶體裝置中，依據本發明 實施例，在功率轉換時之資料保護的方法係如第20圖所 示。控制非揮發記憶體裝置，例如快閃記憶體裝置的記憶 體控制器在任一功率轉換（步驟1100)前，保持RST#爲 低，以使裝置在一重置狀態。在此時，裝置的內部暫存器 被設定至一預設或重置狀態。控制器然後允許電力轉換（ 步驟1102)並等待預設時間，等待裝置的內部電壓穩定 (步驟1104)。等待時間週期對應於第19圖所示之tRST ，並至少爲Vcc電壓位準到達穩定VST電壓位準所花的時 間（時間t0N至tST )加上在Vcc位準到達一穩定電壓位 準V S T後的至少一時間間距t 1。時間間距t 1可以根據例如 操作電壓及處理技術之裝置特徵加以決定。例如，RST# 保持爲低之總時間週期’即t r s τ可以爲1 〇微秒或更大。 在此裝置的時間週期各種元件穩定及時鐘變成可操作並變 成頻率及相位穩定。 在經過時間週期tRST後，當裝置期待在“備用”狀態時 -46- 200828338 ，控制器主張RST#高信號（步驟1106)。如參考第19 圖所’在時間t0N控制器主張CE#信號，同時，裝置在重 置狀態，並在RST#被解除，以將記憶體裝置由重置狀況 釋放。CE#信號在時間tCEOff解除，以允許裝置進入一正 常執行狀態。時間tCEOff係在t2的至少一時間間距後，在 RST#信號已經主張後。一旦裝置進入正常執行狀態，啓 始操作可以執行於裝置位準或系統位準（步驟Η 08 )。 類似於時間U，時間間距t2可以根據裝置特徵加以決定 ’並將由一記憶體系統至另一記憶體系統地改變。例如， t2可以是100微秒或更大。 第2 1圖描述在功率轉移時，裝置所涉及之步驟，以 確保依據本發明實施例之資料保護。在任何電力轉移前， 該非揮發記憶體裝置自一控制該裝置的記憶體控制器接收 —RST#低信號（步驟1200 )。裝置然後自該控制器接收 電力，以作動該裝置元件（步驟1202 )。此接收之電力 可以由 V S S電壓或由一低功率模式電壓位準增加至全 VCC操作電壓位準。因爲RST#信號很低，所以，裝置係 被放置在重置狀態。在此時，裝置的內部暫存器及任一有 限狀態機係被設定並維持在一預設或重置狀態（步驟 1204 )。在主張RST#爲高前，控制器然後等待預定時間 週期’等待裝置的內部電壓穩定。在經過時間週期tRST後 ’當裝置被期待有一“準備”狀態時，控制器主張一 RST# 高信號。裝置接收RST#高信號並放置裝置於“準備，，狀態 (步驟1 206 )。在時間tCEOff時，控制器主張CE#信號， -47 - 200828338 以允許裝置進入正常執行狀態。如前所述，——旦裝置進入 正常執行狀態，則啓始操作可以以裝置位準執行（步驟 1 208 ) 〇 在第4圖之記憶體系統200中之電力轉換中，討論資 料保護的方法。供電時，記憶體控制器202將保持重置（ RST# )爲低，以保持所有記憶體裝置204、206、208及 210在重置，同時，電力穩定及裝置準備操作。在Vcc穩 定後，RST#將爲控制器202所保持爲低一最小時間tl ( 例如20微秒），如第19圖所示。在RST#被保持爲低時 ，在記憶體中之所有有限狀態機被啓始，及任何架構及狀 態暫存器均被重置至其預設或重置狀態。在RST#被解除 至一高邏輯位準，時鐘變成操作性並變成頻率及變成頻率 及相位穩定。如前參考第19圖所示，在時間t0N，控制器 202解除CE#信號，同時，裝置係在重置狀態及主長CE# 及RST#已經解除。CE#信號在時間^⑼^被主張以允許裝 置進入正常執行狀態。時間tCEOff係在t2的時間間距後經 過，在RST#信號被主張後。一旦裝置進入正常執行狀態 ，啓始操作可以執行於裝置位準及系統位準。啓始化操作 例子包含裝置位址及識別碼產生，及在串聯連接中之每一 裝置的指定。各種裝置位址及識別碼產生之方法係描述於 共同申請之美國專利申請案第1 1/622,828; 1 1/750,649; 11/692,452; 11/692,446; 11/692,326;及 11/771，023 案 中。 藉由確保裝置在重置狀態一預定時間量，在功率轉移 -48- 200828338 操作時，防止虛僞資訊被儲存或閂鎖在裝置的各暫存器中 。該裝置因此被保護對抗資料的不當規劃或抹除，確保資 料在電力轉移時之完整性。 在前述說明中，爲了解釋目的，各種細節係加以描述 ，以提供對本發明之實施例有完全之了解。然而，爲熟習 於本技藝者可以了解這些特定細節在實施本發明時並不需 要。例如，已知電結構及電路係被以方塊圖顯示，以不會 阻礙本發明。例如，有關於本發明竇施例所述之特殊細節 係被提供實施爲軟體常式、硬體電路、韌體、或其組合。 本發明之實施例可以以儲存於機器可讀媒體（稱爲電 腦可讀取媒體、處理器可讀取媒體、或具有電腦可讀取程 式核心實施例）電腦可用媒體中之軟體加以表示。機器可 讀媒體可以爲任意適當實媒體，包含磁、光或電性儲存媒 體包含有碟片、光碟（CD-ROM )、記憶裝置（揮發或非 揮發），或類似儲存媒體。機器可讀取媒體可以包含各種 組之指令、碼序向、架構資訊、或其他資料，當其被執行 時，使得一處理機執行依據本發明實施例之方法的步驟。 熟習於本技藝者可以了解，其他指令或操作以執行所述之 本發明也可以儲存在機器可讀取媒體中。由機器可讀媒體 執行之軟體可以與電路互動，以執行想要工作。 本發明之上述實施例係只作例示。各種改變、修正及 變化可以爲熟習於本技藝者，在不脫離本發明範圍下完成 ，本發明範圍係由隨附申請專利範圍所界定。 -49 - 200828338 【圖式簡單說明】 第1圖先前技術之NAND快閃記憶體核心之示意圖； 第2圖爲先前技術之快閃記憶體系統之方塊圖； 第3A圖爲串列記憶體系統之一般方塊圖； 第3B圖爲由NAND快閃記憶體裝置構成之串聯記憶 體系統之方塊圖； 第3 C圖爲由不同記憶體裝置混合所構之串聯記憶體 系統之方塊圖； 第4圖爲第3A圖之串聯記憶體系統架構有並聯時鐘 設計之方塊圖； 第5圖爲第3A圖之串聯記憶體系統架構有源同步時 鐘設計之方塊圖； 第6圖爲動態可調串聯記憶體系統之方塊圖； 第7圖爲具有一本地核心與串聯輸入/輸出介面適用 於第3A至3C及4至6圖之串聯記憶體系統的記憶體裝 置的方塊圖； 第8圖爲模組化命令封包結構示意圖； 第9圖爲用以操作第7圖之快閃記憶體裝置例示模組 化命令封包的表列； 第10圖爲在一記憶體裝置內執行同時發生操作方法 的流程圖， 第11圖爲用於兩不同排之記憶體裝置的同時發生讀 取操作的時序圖； 第12圖爲用於兩不同排之記憶體裝置的同時發生規 -50- 200828338 劃操作的時序圖； 第13圖爲用於兩不同排之記憶體裝置的同時發生讀 取及規劃操作的時序圖； 第1 4圖爲用於兩不同排之記憶體裝置的同時發生方 塊抹除之時序圖； 第1 5圖爲具有懸置及回復操作之不同排記憶體裝置 的同時發生規劃及讀取操作的時序圖·， φ 第1 6圖爲兩串聯連接記憶體裝置操作的時序圖； 第1 7 A圖爲本發明實施例可應用之快閃記憶體裝置 的方塊圖； 第17B圖爲正反器之示意圖； 第18圖爲在第17A圖之快閃記憶體裝置供電及斷電 操作時之各種控制信號的時序圖； 第19圖爲在一非揮發記憶體裝置之供電及斷電操作 時之各控制信號的時序圖； # 第20圖爲在非揮發記憶體裝置中之電力轉換時，資 料保護方法之流程圖；及 第21圖爲依據本發明另一實施例之非揮發記憶體裝 置電力轉換時，資料保護方法之流程圖。 【主要元件符號說明】 30 :排 32 :資料暫存器 1 〇 :快閃記憶體系統 -51 - 200828338 1 2 :主機系統 1 4 :記憶體控制器 1 6 :非揮發記憶體裝置 1 8 :通道 100 :串聯記憶體系統 102 :記憶體控制器 104 :記憶體裝置 0 106 :記憶體裝置 108 :記憶體裝置 1 1 〇 :記憶體裝置 1 1 2 :記億體裝置 1 1 4 :記憶體裝置 1 1 6 :記憶體裝置 200 :串聯記憶系統 202 :記憶體控制器 # 204 :記憶體裝置 206 :記憶體裝置 208 :記憶體裝置 2 1 0 :記憶體裝置 3 0 0 :串聯記憶系統 3 02 :記億體控制器 3 04 :記憶體裝置 3 06 :記憶體裝置 3 08 :記億體裝置 -52- 200828338 3 1 0 :記憶體裝置 400 :可調串聯記憶系統 402 :記憶體控制器 404 :記憶體裝置 406 :記憶體裝置 408 :記憶體裝置 4 1 0 :記憶體裝置 φ 4 1 2 :擴充鏈結 4 1 4 ·擴充鍵結 4 1 6 :擴充鏈結 4 1 8 :擴充鏈結 420 :擴充鏈結 422 :擴充模組 424 :擴充模組 426 :擴充模組 • 428 :跳線 4 3 0 :跳線 500 :記億體裝置 502 :記憶體陣列排 5〇4 :記憶體陣列排 5 06 :本地控制及I/O電路 5 0 8:串聯介面及控制邏輯方塊 6 0 0 :命令封包 6 0 2 :命令封包 -53- 200828338 604 :位址欄 606 :資料欄 608 :裝置位址欄 610 : Op-碼欄 800 :頁讀取命令封包 8 02 :頁讀取命令封包 8 04 :叢發讀取命令封包 φ 806 :讀取資料封包 808:叢發讀取命令封包 8 1 0 :讀取資料封包 8 2 0 :命令封包 822 ：命令封包 8 24 :叢發資料載入命令封包 826:頁讀取命令封包 828 :讀取狀態命令封包 Φ 830 :讀取資料封包 8 3 2 :讀取狀態命令封包 834 :讀取資料封包 840:頁讀取命令封包 8 42 :叢發資料載入命令封包 844 :頁讀取命令封包 846 :叢發讀取命令封包 848 :讀取資料封包 8 5 0 :叢發資料狀態命令封包 -54- 200828338 852 :讀取資料封包 860 :方塊抹除位址輸入命令封包 862 :抹除命令封包 864:方塊抹除位址輸入命令封包 866:抹除命令封包 8 6 8 :讀取狀態命令封包 870 :讀取狀態命令封包 φ 872 :讀取資料封包 8 74 :讀取資料封包 8 80 :叢發資料載入開始命令封包 8 82 :頁讀取命令封包 8 8 4 :叢發資料載入命令封包 8 8 6 :頁讀取命令封包 8 8 8 :叢發讀取命令封包 890 :資料讀取封包 # 892 :讀取狀態命令封包 894 :讀取資料封包 8 9 6 :叢發讀取命令封包 898 :讀取資料封包 900 :選通信號 902 :讀取資料封包 904 :命令封包 906 :選通信號 1 〇 1 〇 :快閃記憶體 -55- 200828338 1 0 1 2 :控制電路 1012a :位址暫存器 1012b :資料暫存器 1012c :命令暫存器 1 〇 1 4 :記憶體陣列 1 05 0 : D型正反器200828338 IX. Description of the Invention [Technical Field to Which the Invention Is Ascribed] The present invention is generally related to a memory system. More specifically, the present invention relates to a memory system in which memory devices are connected in series for use in mass storage applications. [Prior Art] • Flash memory is a commonly used type of non-volatile memory that is used in large quantities as a large storage device for consumer electronics such as digital cameras and portable digital music players. The currently available flash memory chips can reach 32 Gbit (4 GB), which is suitable for general purpose USB flash drives because of the small size of a flash chip. Figure 1 is a general block diagram of a known row of NAND flash memory. It will be appreciated by those skilled in the art that a flash memory device can have any number of rows. Row 30 is organized as k+Ι squares. Each block contains a ® NAND memory cell string with up to i + l flash memory cells connected in series with each other. Therefore, the word lines WL0 to WLi are connected to the gates of each of the flash memory cells in the memory cell string. A string selection device connected to the signal ss L (string selection line) selectively connects the memory cell string to the -bit line, and a ground selection device connected to the is number GSL (ground selection line) selectively connects the S-recall Single string to a power cord, such as v SS. The string selection device and the ground selection device are η-communication transistors. There are j + 1 bit lines shared by all the blocks of row 3 0, and each bit line is connected to one of the NAND memory cell strings of each block [〇] to [k]. Each word line (WL 〇 200828338 to WLi), SSL and GSL signals are connected to the same corresponding transistor device in each NAND memory cell string in the block. As is known to those skilled in the art, the data and a line of characters stored in the flash memory unit are referred to as a page of data. Each bit line connected to the row 30 is a data buffer 32 for storing data to be written into one page of the flash memory unit, or taken out by the flash memory unit. Read the data. The data buffer 32 also includes a sensing circuit for sensing data read from a page of flash memory cells. During the planning operation, the data register performs program verification operations to ensure that the data has been properly programmed into the flash memory unit connected to the selected word line. Each memory cell of row 30 can store a single bit of data or a plurality of bits of data. Some flash memory devices will have more than one set of data registers to increase throughput. The advent of eight-megapixel digital cameras and portable digital entertainment devices with music and imaging capabilities has created a high demand for storing large amounts of data. This is not compatible with a single flash memory device. Therefore, multiple flash S-resonance devices are combined to form a memory system to effectively increase the available storage capacity. For example, such applications may require a flash storage density of 20 G B. 2 is a block diagram of a prior art memory system 10 integrated into a host system 12. The flash memory system 1 includes a memory controller 14 for communicating with the host system, and a plurality of non-volatile memory devices 16 . The host system will contain processing devices such as microcontrollers, microprocessors or computer systems. The flash memory system 1 of Fig. 2 is constructed to include -6 - 200828338, a channel 18, in which a memory device 16 is connected in parallel to the channel 18. As will be appreciated by those skilled in the art, the memory system 10 can have more or less than four memory devices connected thereto. Channel 18 contains a set of command buses that contain data and control lines that are connected to their corresponding § memory devices. Each memory device is enabled/disabled corresponding to the individual wafer select signals ce#1, CE#2, CE#3, and CE#4 provided for the memory controller 14. "#," indicates that the signal is a low active logic level signal. The memory controller 14 is responsible for issuing commands and data via the channel 18 to select a memory device according to the operation of the host system 12. Reading from the memory device The outgoing data is passed back to the memory controller 14 and the host system 12 via channel 18. The operation of the flash memory system 10 is synchronized to a clock CLK, which is provided in parallel to each memory device 16. The flash memory system 1 is generally referred to as a multi-drop architecture in which the memory devices 16 are connected in parallel with respect to the channel 18. In the flash memory system 10, the non-volatile memory devices i 6 can be identical to each other. And typically implemented as a NAND flash memory device. Those skilled in the art will appreciate that flash memory is organized into rows, and each row is organized into squares to facilitate block erase. Most commercial N AND flashes The memory device is configured to have two rows of memory. There are several special issues that will negatively impact the performance of the system. The architecture of the flash memory system 10 adds physical performance limitations. Parallel signals, the signal integrity of the signals they carry will be degraded by crosstalk, signal skew, and simultaneous switching noise (S SN ). The power consumption in this architecture is also in the flash controller. Each signal track of the flash memory device 200828338 is often charged and discharged as a signal. As the system clock frequency increases, the power consumption will increase. The number of memory devices that can be connected in parallel to the channel is also substantial. The limitation is that the driving ability of a single memory device is small compared to the loading of a long signal track. Furthermore, when the number of memory devices increases, more wafer enable signals (CE#) and clocks are required. The signal CLK will need to be sent to another memory device. Since clocking 0 events for dense clock distribution are known in the art, this will need to be discussed. Therefore, in order to accommodate a memory system with a large number of memory devices Must use a controller with more channels, or the system needs to add a clock with a lower frequency. The architecture has a controller with a majority of channels and the amount The wafer enable signal increases the cost of the memory system. Otherwise, the memory system will be limited to a small number of memory devices. Therefore, we want to provide a memory system architecture that can support any number of memory devices. SUMMARY OF THE INVENTION [0009] Aspects of the present invention are to avoid or eliminate at least one of the disadvantages of the foregoing memory system. In a first aspect, the present invention provides a memory system having a controller and a memory device. a serial channel output port comprising a serial bit stream command packet; and a serial channel input port for receiving a serial bit stream read data packet. The serial bit stream command packet includes an opcode and a device address The memory device has an input port for receiving a serial bit stream command packet from the controller with -8-200828338 and for executing the operation command if the device address corresponds to the memory device. The memory device provides a serial bit stream command packet via the output port and then if the opcode corresponds to a read action, the serial bit stream is read via the output port to read the data packet. According to an embodiment of the present aspect, at least one intermediate memory device is connected in series between the memory device and the controller. The at least one intermediate memory device has means for receiving and transmitting a serial bit stream command packet to the memory device and then providing a serial bit stream command packet to the memory device and if the device address corresponds to the memory device and the The opcode corresponds to a read function, and then the input of the serial bit stream read data packet is provided. According to other embodiments, the complementary clock signal is provided in parallel to the memory device and the at least one intervening memory device. 'Or a complementary clock signal is provided to at least one interposable memory device and transmitted to the memory device for the at least one interposable memory device and transmitted to the controller for the memory device. In another embodiment of the present aspect, the memory system includes an extended link between the controller and the memory device for receiving an expansion module and one of the jumpers. The at least one interposable memory device is part of an expansion module having a coupling mechanism for electrically coupling to the expansion link. According to other embodiments, the memory device and the at least one intermediate memory device each include a local core and a serial interface, and a control logic block for controlling the local record in response to the serial bit stream command packet -9- 200828338 The core of memory. The memory device local memory core and the at least one intermediate memory device local memory core may be NAND flash memory or may be DRAM, SRAM, NAND flash memory or NOR flash memory core. In another embodiment of this aspect, the serial bit stream command packet has a modular structure in which the size of the serial bit stream command packet is variable. The serial bit stream command packet may include a command bar for providing an opcode and a device address, wherein the command bar includes a first column for providing an opcode and a second column for providing a device bit. site. The serial bit stream command packet may include a command bar for providing operation and device addresses, and an address bar for providing a column address and an address field for one of the addresses. The serial bit stream command packet may include a command bar for providing an opcode and a device address, an address field for providing one of a column address and a row address, and a data field for providing writing data. In accordance with one aspect of the previous embodiment, the controller provides a command strobe in conjunction with the serial bit stream command packet, the command strobe having an actuation level that matches the length of the serial bit stream command packet. Furthermore, the controller is coupled in parallel with the serial bit stream read data packet to provide a data input strobe, the data input selection having an actuation level that matches the length of the serial data stream read data packet. When the device address corresponds to the memory device, the memory device latches the serial bit stream command packet in response to the command strobe actuation level, and the memory device output system responds to the data input The actuating level of the strobe is enabled. The command strobe and data input strobes are non-overlapping signals and are separated by at least one data latch clock edge. In addition, the command selection -10- 200828338 also separates at least one data latch clock edge for the adjacent command strobe, and the data input strobe is a clock edge for separating at least one data μ lock for the adjacent data input strobe. In the first aspect, a command packet having a series of bits is provided to a memory system having a serially connected memory device. The command packet includes a command bar for selecting a memory device connected in series to the memory device to perform a particular memory operation. In a second aspect, the command bar includes a first column for providing a device address for selecting a memory device, and a second column for providing operation corresponding to the particular memory. Opcode. The command packet further includes an address bar after the command bar for providing one of a column address and a row address when the opcode corresponds to a read or write operation, the address bar having a corresponding The length of the bit of the column address or row address. A data field is located after the address field for providing write data for storage in the memory device when the operation code corresponds to the write operation, the data field having a bit length corresponding to the written data. In the second aspect, there is provided a method of performing a simultaneous operation in a selected memory device in a memory system having a serially connected device. The method includes: receiving a first command; performing a core operation in a first memory bank in the selected memory device in response to the first command; receiving a core operation while performing a core operation in the first memory bank ^ a second command; and in response to the brother one command 'performing a core operation in the second memory bank in the selected memory device. According to the embodiment of the present aspect, the method further includes: receiving a third life command - a command from the first memory bank and the second memory bank, and responding to the third command, Output a read data packet containing the resulting information. The resulting information includes one of the status register data and the read data. In another embodiment of the present aspect, the first command, the second command, and the third command are command packets, and include a series of bits that are logically configured to include a mandatory command bar for providing a An operation code and a device address; a selection address bar, after the command bar, is used to provide one of a column and a row address when the operation code corresponds to a read or write operation; and an optional data field After the address bar, it is used to provide write data when the operation code corresponds to a write operation. In an aspect of the embodiment, the first command gating system is received in parallel with the first command, the first command gating has an actuation duration corresponding to the first command length, and the second command gating system is connected in parallel The second command is received, the second command strobe having an actuation duration corresponding to the second command length. The first command strobe is separated from the second command strobe by at least one data latch clock edge. Furthermore, a data input strobe is received to enable reading of the output of the data packet while the data input strobe is at the active level, so that the second command strobe is separated from the data input strobe by at least one Data Latch Clock In another embodiment, the method includes powering the selected memory device prior to receiving the first command. The step of supplying power includes: asserting a control signal to maintain the selected memory device in a preset state before the power transfer; and when the control signal is asserted, the power level of the selected memory device is The first voltage level is transferred to the second voltage level; -12- 200828338 waiting for a predetermined duration to allow the power supply level to stabilize; and de-asserting the control signal to cause the selected memory device to be The preset state is released to prevent inadvertent planning or erasing operations on the selected memory device. The second voltage level can be the minimum voltage level used to stabilize the circuit operation or the maximum operating voltage level of the power supply. The first voltage level may correspond to a low power mode operating voltage level of the power supply or no power source. In another embodiment, maintaining the memory device in the preset state includes setting a device register in the memory device to a preset port, wherein the device register includes a command register. Another step of the method includes performing device initiation upon initiation of release of the memory device from a preset state. The step of initiating the execution of the apparatus includes generating device address and device identification code information for the memory device. In another embodiment, the powering step includes asserting a control signal at a first time to maintain the memory device in a predetermined state before the power transfer; and when the control signal is asserted, the memory device The power level is transferred from the first level to the second level; waiting for a predetermined duration to allow the power level to be stable; and at the third subsequent time, releasing the control signal to release the memory device from the preset state In order to prevent inadvertent planning or erasing operations on the memory device. In the fourth aspect, a memory system is provided which includes a plurality of memory devices and a controller for controlling the devices. The controller has an output port for providing a bit stream command packet to the first device of the plurality of memory devices, the bit stream command packet including an opcode and a device address. Each memory device receives a bit-13-200828338 meta-stream command packet from one of the controller and the previous memory device, and if the device address corresponds, executes the opcode, and each memory device provides a bit stream command. The packet is sent to the next memory device and one of the controllers. If the opcode corresponds to a read function, the one-bit stream read data packet is provided by the last memory device of the majority of the memory devices. Controller. In accordance with an embodiment of the present invention, a plurality of memory devices are connected in series, and a first and last memory system is coupled to the controller, the controller sending a bit stream data packet to the first device of the plurality of memory devices. The bit stream data packet and the bit stream read data packet from the controller comprise a serial bit stream or a parallel bit stream. Most memory devices are a mixture of the same type or different types of memory devices. According to another embodiment, the system can perform the powering function of the selected memory device prior to receiving the first command. The memory system can perform a function of: claiming a control signal to maintain the selected memory device in a preset state before power transfer; and asserting the power level of the selected memory device while asserting the control signal The first voltage level is transferred to the second voltage level; waiting for a predetermined duration to allow the power level to stabilize; and releasing the control signal to release the selected memory device from the preset state, thereby preventing the selected memory Inadvertent planning or erasing of the device. The memory system may also have the function of: asserting a control signal at a first time to maintain the memory device in a preset state before the power transfer; and when the control signal is asserted, the power of the memory device The level is shifted from the first level to the second level; waiting for a predetermined duration to allow the power level to stabilize; at the third subsequent time, the control signal is released to pre-set the memory device from -14 to 200828338 The state is released to prevent inadvertent planning or erasing of the memory device. The aspects and features of the present invention will become apparent from the <RTIgt; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following detailed description of the embodiments of the invention, reference to the claims The embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It can be appreciated that other embodiments can be utilized to carry out changes in the logic, electrical and other blocks without departing from the invention. The scope. Therefore, the following detailed description is not to be taken as limiting, and the scope of the invention is defined by the scope of the appended claims. This case describes a memory system architecture with a serially connected memory device. The memory system is scalable to include any number of memory devices without performance degradation or complex redesign. Each memory device has a serial input/output interface for communication between other memory devices and the memory controller. The memory controller issues a command in at least one of the metastreams, wherein the bitstream follows a modular command protocol. The command includes an opcode with optional address information and device address so that only the addressed memory device acts on the command. Separate data output strobes and command input strobe signals are respectively provided in parallel to provide respective output data streams and input command data streams for indicating the type of data and the length of the data. The modular command protocol is used to perform simultaneous operations in each memory device, -15-200828338 to further improve performance. Figure 3A is a block diagram of a commemorative structure of a series memory system in accordance with an embodiment. In FIG. 3A, the serial register system includes a memory controller 102 having at least one serial channel output 埠Sout and a serial channel input 璋sin, and a memory device 1〇4, 106 connected in series, 1 08, 1 1 0, 1 1 2, 11 4 and 1 1 6 In one embodiment, the memory device can be a flash memory device. Alternatively, the memory device can also be a DRAM 'SRAM or any type of memory device as long as it has a serial input/output interface that is compatible with a particular command structure for executing commands or transmitting commands and Data to the next memory device. Other details of this memory device architecture and a particular command structure will be described later. The current embodiment includes seven memory devices, but other embodiments may have as few as one memory device, or as many as any number of memory devices. Thus, if memory device 104 is the first device in series memory system 100, since it is connected to Sout, memory device 116 is the Nth or last device because it is connected to Sin, where N is an integer greater than zero. The memory devices 106-116 then intervene in series with the memory devices connected in series between the first and last memory devices. Each memory device can assume a unique identification number, or device address (DA), when the system power is initiated, so that they can be individually addressed. U.S. Patent Application Serial No. 1 1/622,828, 1 1/750, 649, 1 1/692,452, 11/692,446, 11/692,326, and 11/771,023, the entire disclosure of each of each of each of each of each of each of each of The method of the address. -16- 200828338 Since the data input of a memory device is connected to the data output of the previous memory device, the memory devices 104 to 116 are considered to be connected in series, thus forming a series connection architecture, except in the chain Outside of the first and last memory devices. The channel of the memory controller 102 includes any data wide data channel ' to carry command, data and address information; and a control channel for carrying control signal data. Additional details of the channel architecture will be shown later. The embodiment of Figure 3A includes a channel, wherein one channel includes a S out and a corresponding Sin 璋. However, the 'memory controller 1 〇 2 may contain any number of channels' for housing separate memory device chains. In normal operation, the memory controller i 〇 2 sends a command via its Sout, which contains an opcode (op code), a device address, address information 'for reading or planning; and for planning data of. The command is issued as a serial bit stream packet, where the packet can be logically subdivided into segments of a predetermined size, such as a one-tuple. A meta-flow is the order or continuation of the bits provided in time. The command is received by the first memory device 104 to compare the device address with its designated address. If the address matches ', then the memory device 丨〇 4 executes the command. Otherwise, the command is transmitted through its output to the next memory device 1 〇6, where the same procedure is repeated. Finally, the memory device with the same device address, called the selected memory device, will execute. The action specified for the command. If the command is to read the data 'the selected memory device will output the read data via its output '', the series is transmitted to the intermediate memory device in series until it reaches the S i η of the g-recall control 1 0 2阜阜. -17- 200828338 Because commands and data are provided in the serial bit stream, a clock is used for each memory device to add clock signals to the in/out series bits and to synchronize internal memory. Operation of the device. This clock is used by the memory controller and all memory devices in the series memory system. There are two possible clock architectures for the series memory system 100 and will be shown in the embodiments of Figures 4 and 5. Figure 3B is a block diagram of a memory system including a type of memory device, such as Figure 3A of a NAND flash memory device. Each NAND flash memory device can be identical to each other or different from each other, e.g., in storage density. Figure 3C is a block diagram of a memory system including various types of memory devices. These memory devices may include NAND flash memory devices, NOR flash memory devices, dynamic random access memory (DRAM) devices, static random access memory (81^1^) devices, and magnetoresistive random access. Memory (MRAM) device. Of course, memory devices not mentioned herein can also be implemented in a memory system. The architecture of a hybrid type of memory device is disclosed in U.S. Provisional Patent Application Serial No. 60/8,68,773, filed on Dec. 6, 2006. Figure 4 is a block diagram of a series memory system designed using a parallel clock. The serial memory system 200 includes a memory controller 202 and four memory devices 204, 206, 208, and 210. The memory controller 202 provides several signals in parallel to the memory device. These include the wafer enable signal CE#, the reset signal RST#, and the complementary clocks CK# and CK. In an example using CE#, when CE# is at a low logic level, the device is enabled. Once the memory device begins planning or erasing operations, CE# is released, or -18-200828338 drives to a high logic level. In addition, the internal clock signal can be started at CE# with low logic level, and the internal clock signal can be removed at CE# with high logic level. In the example using RST#, when RST# is a low logic level, the memory device is set to the reset mode. In the reset mode, power is allowed to stabilize and the device is ready to operate by initiating all finite state machines and resetting any of the architecture and status registers to their default state. The channel of the memory controller 202 includes: a data channel, which is composed of an output 璋Qn and an input 埠Dn; and a control channel, which is a command strobe input CSI and a command strobe output CSO (CSI Echo), data strobe input DSI, and a data strobe output DSO (DSI echo). Depending on the desired architecture, the output 璋Qn and the input 璋Dn may be a width of 1 bit, or a width of η bits, where η is a non-zero integer. For example, if η is 1, then a tuple data is received after the eight data latch edges of the clock. A data latch clock edge can be, for example, a rising clock edge. If η is 2, one tuple data is received after the four latch edges of the clock. If η is 4, then a tuple data is received after the two latch edges of the clock. The memory device can statically architect or dynamically structure Qn and Dn of any width. Thus, in an architecture where η is greater than 1, the memory controller provides data in the parallel bit stream. The CSI is used to latch the command data appearing at the input 埠Dn and has a pulse width corresponding to the length of the received command data. More specifically, the command data will have a duration measured for several clock cycles, and the pulse width of the CSI signal will have a corresponding duration. The DSI is used to enable the output of the 埠Qn buffer to output data with a pulse width corresponding to the length of the requested read data. Additional details of DSI and CSI Letter -19- 200828338 will be discussed later. In the embodiment shown in FIG. 4, each memory device has the same serial input/output interface including RST#, CE#, CK#, and CK input ports for receiving the same from the memory controller 202. Name signal. The serial input/output interface contains data input 埠Dn, data output 埠, CSI, DSI, CSO, and DSO埠. As shown in Fig. 4, the Dn, CSI, and DSI input ports for each memory device are connected to the Qn, CSO, and DSO outputs of the previous memory device, respectively. Therefore, the memory devices are connected in series with each other because each memory device transfers commands and read data to a lower memory device in the chain. In a practical implementation of the embodiment of Figure 4, each memory device is positioned on a printed circuit board such that the distance between the input and output turns and the signal track are minimized. Alternatively, four memory devices can be implemented in a system-in-package (SIP) module, which further minimizes track length. The memory controller 202 and the memory devices 204 through 210 are connected in series to form a ring topology, indicating that the last memory device 210 provides an output back to the memory controller 202. Therefore, those skilled in the art will appreciate that the distance between the memory device 210 and the memory controller 202 is easily minimized. The memory device in the serial memory system 200 of Figure 4 is significantly more efficient than the memory device of the prior art system of Figure 1. For example, assume that a 66 MHz clock and series memory system 200 are used to include four memory devices, and that one of the serially connected memory devices of Figure 4 will have a data rate of about 13 3 Mbps. Conversely, assuming that each memory device's read cycle time (tRC) and write cycle time (tWC) -20 - 200828338 are rated at approximately 25 ns, Figure 1 has a multi-injection memory with four memory devices. The body device will have a data rate of about 40 MbPs per pin. Moreover, the power consumption of the serial memory system 200 will be reduced relative to the prior art of Figure 1. The performance and power consumption advantages of the series memory system 200 are primarily due to the lack of signal rails 18 that must be driven for each memory device. A significant advantage of the series memory system 200 of Figure 4 is the scalability of the system. In other words, more than four memory devices can also be included in the memory chain connected to the memory controller 2' without any degradation in performance. Conversely, because of the need to increase the signal track length of channel 18 to accommodate these additional devices, the prior art system of Figure 1 will have practical limitations as more and more memory devices are added when they are added. The less you return. Additional pin loading signals are contributed by the added device. As mentioned earlier, the clock frequency must be reduced to ensure data transmission integrity when driving a long channel of 18, which reduces performance. In the embodiment of Figure 4, the clock distribution will be designed to accommodate a large number of memory devices and may include repeaters and balance trees to maintain the clock integrity of all memory devices. As will be appreciated by those skilled in the art, there are several ways to provide a balanced clock signal. While the series memory system of Figure 4 provides superior performance over prior art memory systems, other performance improvements can be achieved by another series memory system embodiment of Figure 5. In addition to the parallel clock distribution design, the series memory system 300 of Figure 5 is similar to the embodiment of Figure 4, and uses a power synchronous clock design. The serial memory system 300 includes a memory controller 032 and four memory devices 3 04, 3 06, 3 0 8 and -21 - 200828338 3 10. The memory controller 302 includes clock outputs 璋CKO# and CKO for providing complementary clock signals, and clock inputs 璋CK# and CK for receiving complementary clock signals from the last memory device of the system. The memory devices are the same as those shown in Figure 4, except that they now have clock inputs 埠CK# and CK, and clock outputs 埠CKO# and CKO, where a memory device is received at CK# and CK璋. The clock is provided to the next device via its CKO# and CKO埠. Finally, the memory device 3 10 provides a clock signal back to the memory controller 302. The main advantage of the embodiment of Figure 5 is that there is no complicated clock distribution design and minimal clock interconnection between memory devices. Therefore, the minimum clock frequency can be increased to 166MHz, resulting in a minimum 333Mbps feed rate per pin. As with the embodiment of Figure 4, the embodiment of Figure 5 can be scaled to include any amount of memory device. For example, the fifth memory device can be added to the embodiment of FIG. 5 and simply connected to the output port of the memory device 3 10 to the corresponding input port of the fifth memory device and connected to the fifth memory device. The output is buffered to the memory controller 302. As will be appreciated by those skilled in the art, the memory controller 302 can include a simple phase lock loop (PLL) to maintain the clock frequency. The architecture of the series memory system 200 and 300 can statically fix a thousand specific amounts of memory devices. Different architectures can be set to provide different memory system capacities by simply adjusting the number of memory devices in the series chain. In another embodiment, memory devices having different capacities can be mixed in the series chain to provide more flexibility to the overall memory system capacity. In some applications, the capacity of the memory system can be dynamically adjusted by adding or removing -22-200828338 modules in the series chain. One module can be a single memory device, SIP memory, or A PCB with a memory device and/or a SIP memory device. Figure 6 is a block diagram showing an embodiment of a dynamically adjustable series memory system. The adjustable series memory system 400 includes a memory controller 4〇2; fixed memory devices 404, 406, 408, and 410; extended links 4 12 ' 414, 416, 418, and 420; and an expansion module 422 , 424 and 426. The fixed memory devices 404, 406, 408, and 410 are connected in series to the intermediate extension link and to the memory controller 402. Each expansion link is a male or female coupling mechanism. Releasably receiving and holding a module having a corresponding female or male coupling mechanism. Each module includes at least one memory device connected in series to the terminal of the extended link. In the illustrated example, the expansion modules 422 and 426 each include four memory devices in series with the input connector and the output connector of the module coupling mechanism. The module 424 includes two memory devices connected in series between the input connector and the output connector of the module coupling mechanism. Thus, by inserting the module into the extended link, another series connected memory device can be dynamically inserted between the fixed memory devices. For example, the unused extension links of the extension links 41 4 and 420 are connected to jumpers 428 and 430 having appropriate architectures to maintain a continuous series electrical connection of the chain. The adjustable series memory system 400 can include any number of fixed memory devices and extension links, and the memory module can be constructed to include any number of serially connected memory devices. Therefore, by simply adding a new module or replacing the current module with a larger capacity module, the adjustable serial -23-200828338 memory system 400 has full scalability in full memory capacity without Rushing overall performance. It is not necessary to change the memory controller because the same channel is interspersed with another series connected memory device, and those skilled in the art will understand how to connect parallel control signals, such as CE#, RST#, and power supply to the station. Insert the module. After the module is inserted, or after the module is removed, the memory system 400 is restarted so that the memory controller can automatically set the ID of the device used in the memory device of the system. The series memory system shown in Figures 3A through 3C and 4 through 6 uses a memory device, such as a flash memory device, with a compatible serial input/output interface. An example of a flash memory device having a series of input/output interfaces is described in co-pending application Serial No. 1 1/324,023, filed on December 30, 2005. Accordingly, the memory devices of the embodiments shown in Figures 3A through 3C and 4 through 6 can be used in the flash memory devices of these patent applications. However, the serial input/output interface described in these patent applications is an example of a serial interface that can be used. Any of the serial input/output interfaces that can cause serial operation between memory devices can also be used as long as it is structured to accept a predetermined command structure. According to another embodiment, the serial input/output interface can be used with any type of memory device. More specifically, other memory types can also be used to operate together with a serial input/output interface. Figure 7 is a block diagram of a memory structure of a general memory device having local core and serial input/output interfaces for the series memory system of Figures 3A through 3C and 4 through 6. The memory device 500 includes a local memory core including -24-200828338 memory array rows 502 and 504, and local control and I/O circuitry 506 for accessing memory array rows 502 and 504. Those skilled in the art will appreciate that memory arrays can be organized into a single memory bank or more than two memory banks. The local memory core can be dominated by DRAM, SRAM, NAND flash, or NOR flash memory. Of course, any new memory and its corresponding control circuit can be used. Thus, depending on the type of local memory core, circuit block 506 can include error detection logic, high voltage generators, update logic, and any other circuit blocks to perform the operations required for the memory type. Typically, the memory device uses a command decoder to initiate the associated circuitry in response to a command received by the assertion of the internal control signal. They will contain known I/O circuitry to receive and latch data, commands and addresses. In accordance with this embodiment, the current I/O circuitry is replaced with a series circuit and control logic block 508. In this example, the serial interface and control logic block 508 receives the RST#, CE#, CK#, CK, CSI, DSI, and Dn inputs and provides Qn, CSO, DSO, CKO, and CKO# outputs. Figure 5 shows the input and output of the memory device. The tandem interface and control logic block 508 is responsible for various functions as described in U.S. Patent No. 1 1/3 24,023. The function of the serial interface and control logic block 508 is to set a device identification number, transfer data to the next serially connected memory device, and decode the received command for performing local operations. The circuit can include a command decoder that replaces the local command decoder in response to a serial receive command associated with a local command, the local command decoder architecture asserting the same control that the local command decoder would claim -25 - 200828338 signal. When the memory devices are connected in series, the command group can be expanded to perform the characteristics used for the memory controller. For example, status register information can be requested to evaluate the status of the memory device. Thus, the series memory system of Figures 3A through 3C and 4 through 6 can include a mixture of memory device types, each of which is different, which is advantageous for larger systems. For example, high-speed DRAM memory can be used for cache operations, while non-volatile flash memory can be used for large amounts of data storage. Regardless of the type of memory device used, each memory device can be individually addressed to actuate a command because the serial interface and control logic block 506 are architectures to receive commands in accordance with predetermined protocols. In accordance with another embodiment, the commands include a command packet' having a modular command structure for controlling individual memory devices of the serial memory system. In the proposed command structure, specific commands can be issued to a memory device at different times as individual command packets. A command packet can initiate a particular operation of the first bank of memory, and when the core operation is performed, a subsequent command packet can then be received in response to the first command packet, initiating another of the second memory bank operating. Other command packets may also be received in an interleaved manner to complete the operations of the first memory bank and the second memory bank. This is referred to as the simultaneous operation of the execution in the memory device. The modular command agreement will be explained before discussing the simultaneous operation. The details of the modular command protocol are described in U.S. Patent Application Serial No. 60/892,705, filed on March 2, 2007, entitled " Command packet 600 has the structure shown in Figure 8 and contains three columns -26-200828338 bits, two of which are selected depending on the particular command issued by the memory controller. The first field is the mandatory column' which is the command bar 602. The first selection column is a address bar 604' and the second selection column is a data column 606. The command bar 602 contains two columns, the first is the device address (DA) column 608 and the second is the oP-code (〇P code) column 610. The device address field 608 can be any number of bits and is used to address each memory device in the system. For example, a device address field 608 of length 1 byte can be sufficient to address 256 memory devices. An address can be reserved while simultaneously addressing all memory devices for broadcasting an operation. In another embodiment, the device address field 608 can include a device type field to indicate the type of memory device associated with the op-code field 61. For example, the device type field can specify DRAM, SRAM, or flash memory. The length of the op-code field 610 can be any number of bits to represent commands for any number of memory devices and can include row addresses. For example, a flash memory command group will have a different command than a DRAM command group, so if the memory system contains two types of memory devices, the op-code bar will be structured to allow all possible commands from both command groups. . The address field 604 is used to provide a column address (column Addr) or row address (row Addr) of a memory array, depending on the type of operation specified for the op-code. The data field 606 will contain any amount of bit data to be written or planned into the memory device. Therefore, the command packet 600 will vary in size because it may not be necessary to write data for a particular operation, and A specific operation may not require an address and write data. Figure 9 illustrates an exemplary command packet </ RTI> that can be used to operate the flash -27-200828338 memory device having the architecture shown in Figure 7 for use in the aforementioned series memory system. The bit position in Fig. 9 corresponds to the order in which the memory device is sequentially received. The command bar 602 occupies the first and second byte locations, and includes the device address (DA) as the first byte information, and the op-code corresponding to the operation as the second byte information. The address bar 604 can contain a three-byte column address (RA) that occupies the third to fifth byte locations, but can be shortened for other commands to include a two-tuple row address (CA). Only occupy the third and fourth tuple locations. For a command with a two-tuple row address, the data field 606 will occupy the fifth bit position to the 2 1 16 bit position if the data has the length. Data can occupy fewer or more byte locations. Any command packet 600 issued by the memory controller will be received in series for each memory device in the system, and only the memory device having the DA column 608 with the device address containing the command bar 602 is activated. Code column 6 1 0. Otherwise, the command packet is transmitted through the memory device and to the next memory device in the chain. Because the op-code is specific to a particular operation, the memory device, i.e., the serial interface and control logic block 508 of the memory device 500, will control the latch address of the command packet and/or the circuitry required for data communication. For example, if a page read command packet is received by a specified memory device, then the designated memory device will decode the op-code and control the appropriate circuitry to latch the following three byte array addresses. bad! The example command packet in Figure 9 is related to flash memory operation. A set of command packets of any type of memory device having different operations can be architected to follow the command structure described. -28- 200828338 The command packet as previously described may preferably be used to perform simultaneous operation of a memory device, such as memory device 500 of FIG. If the memory device 500 is architected to independently access any of the banks, then concurrent operations can be performed substantially within the memory device. Independent access means that the core operations of different memory banks can operate independently of each other. An example of such a memory device is described in the aforementioned U.S. Patent Application Serial No. n/324,023. A core operation represents a logical or functional operation that is not interrupted because the completion of core operations may depend on the order of specific events performed under state machine or other logical control. Simultaneous operation will increase the performance of the system because the memory controller does not need to wait until the memory device completes the first operation before sending the command packet for the second operation. In a conventional NAND flash memory device, the memory device will not accept another command or respond to a receive command of a different bank of memory until the core operation completes the current memory bank. Therefore, the memory device will perform several operations in series before accepting another command. In the simultaneous operation of this embodiment, a command packet will initiate the operation in a memory bank, and while the core operation is performed for the first memory bank, the subsequent command packet will immediately start the same. Another operation of the second memory bank in the memory device. Therefore, the two operations will be performed simultaneously for two memory banks. Fig. 10 is a flow chart showing, for example, a method of performing simultaneous operations in a memory device of a memory device 500, the memory device being structured to independently access its memory bank. Beginning at step 700, the _th command is issued by the memory controller and received by the memory device. The _-29-200828338 r command may be any of the command packets shown in FIG. 9 described above. Once the entire packet (command bar, address bar, and data field) is received, the core operation begins at step 702 with the first memory bank of the memory device. At the same time as the first memory bank core operation begins, a second command is issued by the §3 memory controller and received by the memory device, as shown in step 704. At step 706, the core operating of the second bank of memory is executed in response to the second command. Finally, the information pertaining to the first command will be presented at step #708. The resulting information may contain status information or read data, which is provided in response to a supplemental read command packet. The status information provides an indication of success or failure of a particular type of operation, such as a planning or erasing operation, and responds to a supplemental "read status" by the memory controller from a status register associated with the memory bank. The command packet is read. The read data is provided in response to a supplemental "burst read" command packet. Referring to Figure 1, the core operation of the read operation will include outputting a page of data from a block of the memory bank to data register block 32. In order to read data from the data buffer block 32, a burst read operation is performed. In step 7 1 , the resulting information pertaining to the second command will be provided. The information from the two memory banks is finally sent back to the memory controller. The embodiment of Figure 1 illustrates the simultaneous operation of two banks of memory, but the method can be applied to the simultaneous operation of two or more banks of memory of the memory device. Figures 1 through 1 5 are a sequence diagram showing the simultaneous operation performed by the flash memory device described in U.S. Patent Application Serial No. 1 1/32,023. Figures 11 through 15 show signal traces for CSI, Dn, DSI, and Qn in time for a memory device of Figure 4 or 5. The order shown in -30-200828338 is intended to show the relative timing between signals, rather than being limited to a specific timing. It should be noted that the command strobe input CSI is an indicator generated by the memory controller and used as the command length combined and output by the memory controller. For example, if the length of the issued command packet is two-tuple, the corresponding CSI has one of the first bits corresponding to the command (in this case, a rising edge), and corresponds to the last bit of the command packet. Acting. The CSI signal controls the memory device command register to latch the command data. The data strobe input signal DSI is also generated by the memory controller and serves as an indicator of the length of the data provided by the memory controller. For example, if the length of the read data required for the memory controller is octet, the corresponding DSI generated for the memory controller will have an operating edge corresponding to the first bit of the read data, and corresponding The last bit of the read data is not used. CSI and DSI are generated by the memory controller when it is known to issue the command bit length and the required read data bit length. Figure 11 is a timing diagram showing simultaneous reading operations of two different banks of memory devices. When the CSI is at a high logic level, a page read command packet 800 for row 0 is latched by the memory device. As shown in Figure 9, the page read command contains a two-tuple command and a three-byte column address. The memory device will start reading the specified column address at time t〇 after the CSI falls to the low logic level. For example, a read operation of a flash memory device will include the operation of the word line, such as WLi in Figure 1, and sense the bit line data of BL0 through BLj. Finally, the sensed data is latched or stored in the data register block 32. In one embodiment, a page read command packet 800 is transmitted via its Qn output port to a memory device of the lower -31 - 200828338. In another embodiment, page read command packet 800 is inhibited from being transferred to other memory devices. For example, the page read command packet 800 provided at Qn output can be set to zero when latched to the command register. This will save power because there is no need for rail-to-rail signal switching of the signal lines. When the CSI is at a high logic level, the page read command packet 802 for row 1 is latched by the memory device. After the CSI falls into the low logic level, the memory device of row φ will begin to perform the read operation for the specified column address. After a certain number of clock cycles, the data is ready to be read by the drain at time t2. In order to read the data from the drain, the memory controller issues a burst read command packet 804 which is received and latched when the CSI is at a high logic level. As shown in Figure 9, the burst read command packet will contain the row address from which the data was read. After the CSI corresponding to the command packet 804 falls to a low logic level, the DSI will rise to a high logic level to enable the Qn output buffer to provide an output data for the read data packet 806 φ . In the example using Figure 1, the data output on the Qn output buffer can correspond to the data read from the data register block 32, starting with the row address specified in the burst read command packet 804. And ends when DSI falls to a low logic level. When the last bit of the output data of the drain is output, the data for row 1 will be ready to be read at time t3. When the DSI falls to a low logic level, the burst read command packet 808 for row 1 is received and latched by the memory device. After the falling edge of the CSI for the burst read command packet 808, the DSI is again driven to the high logic level for a predetermined duration to output the read resource from row 1 on the Qn output port. 200828338 is expected to be a read data packet 8 1 0. Because the core operation of row 0 between to and t2 and the core operation of row 1 between t1 and t3 occur substantially simultaneously and overlap each other 'so' the total core operation time of the two read operations is between time t0 and t3 . In the prior art, the two core operations are performed sequentially, which means that in response to the core operation of the second page read command packet row 1, the second page read command packet is after the core operation of row 0 of t2 is completed. receive. The performance advantages of performing simultaneous operations as previously shown are known to those skilled in the art. Figure 12 is a timing diagram showing the simultaneous operation of two different banks of memory devices. It is noted that the command packet received at the Dn input port of the memory device is transferred to its Qn output 璋' which is shown in the Qn signal track of Figures 1 through 15. In order to plan a billion-body row, the planning data is loaded into the data register of the memory device according to a specific row address, and then planned into a specific column. In Fig. 12, the burst data load command packet 820 for draining is received with the planning material, and immediately there is a page planning command packet 822. When the CSI is at a high logic level, the command packets 820 and 822 are both latched. After the page plan packet 822 is latched and decoded for the memory device, the core operations for planning the data to the drain are started at time t0. Now, the burst data load command package 824 for row 1 is received with the planning material, and immediately there is a page planning command packet 826. After the page plan packet 826 is latched and decoded for the memory device, the core operations for planning the data for row 1 begin at time t1. If desired, the memory controller can also request the status of the memory device by issuing a read status command packet 828. This will access the status register of the memory -33-200828338 device. When DSI is at the high logic level, the data of the memory device will be output on the Qn output port as the read data packet 83 0 . Those skilled in the art will appreciate that the status register memory device is internally updated when internal operations are performed. In this example, reading the data packet 830 will indicate that the planning for the drain has been completed. A subsequent read status command packet 832 will cause the read data packet 834 to provide a status register, which may have completed the planning of row 1. Again, because the core planning operations of row 0 to row 1 φ occur and overlap at the same time, a lot of time can be saved compared to the sequential planning of the two rows. Figure 13 is a timing diagram showing the simultaneous reading and planning operations of two different banks of the memory device. The page read command packet 840 for draining is latched by the memory device, followed by a burst data loading start packet 842 for row 1, followed by a page plan for row Command packet 844. At time t0, the core operation for reading the data begins with the drain, while at time 11, the core operation for planning the data begins with Φ row 1. Since the core operation of the page read operation is started first, the data will be completed at time 12 when the core operation for planning the data is being performed. Therefore, a burst read command packet 864 is received, and the DSI is asserted to output the read data packet 848, which outputs the data read from the row 0. After the DSI is released to end the data output from the readout, a read status command packet 850 can be issued to check the plan of the row 1. Since row 1 should have completed the planning operation at time t3, DES is again asserted and the read data packet 852 is provided at the Qn output 璋, which indicates the pass or fail state of the planning operation. -34- 200828338 Figure 14 is a sequence diagram showing the simultaneous erasure of two different rows of memory devices. The block erase address input packet for the drain is 860 for the memory device and is followed by the erase command packet 8 62 for row 0. After the latch erase command packet 862, at time t0, the core operation for draining begins. Block erase address for row 1 The input command packet 864 is latched by the memory device followed by an erase command packet 866 for row 1. After the latch erase command packet 866, the core operation for row 1 begins again at time t1. Block Erase Address The structure of the input command and erase command is shown in Figure 9. If the erase operation for the drain should be completed at time t2 and the erase operation of row 1 should be completed at time t3, the separate read status command packets 868 and 870 can be issued and latched for the memory device. Corresponding read data packets 872 and 874 are provided on the Qn output port of the memory device, each providing a state register. In the timing diagrams of Figures 11 through 14, it has been shown that different combinations occur simultaneously. An advantage of the modular command packet structure described in the previous embodiment is that different command packets can be sent at different times. As shown previously, the 'one burst data load command packet is followed by a one-page plan command packet. However, this is not entirely necessary, and if desired, the page plan command packet can be sent later. When the command packet is used in combination with the combination of the command strobe signal CSI and the data strobe signal DSI, a further advantage is achieved, that is, the ability to suspend the operation of the memory device. As mentioned earlier, the csi strobe signal is provided by the memory controller to indicate that the command data on the Dn input port is latched for the command register and may have -35- 200828338 corresponding to the The duration of the commanded packet length issued. Since the input data for planning a memory bank and the output data read from a memory bank can exceed 1 000 bytes in length, it is familiar to those skilled in the art to input or output this quantity. It takes a long time to get the information. According to this embodiment, the CSI and DSI strobe signals can be pre-released when the planning data is loaded or the read data is output, and replies at a later time. φ Figure 15 is a sequence diagram showing simultaneous planning and reading operations, and suspension and recovery operations for two different banks of memory devices. The burst data loading start command packet 880 for row 1 is latched, and the data payload in the data column of the command packet is latched by the memory device. At time t〇, when the memory controller releases CSI, the data loaded into the memory device is suspended. In this example, only 256 bytes of data are latched by the memory device, which is tracked by the memory controller. For page 0, the read command packet 882 is latched, and the core operation for row 0 begins at time #tl. When the burst data load command packet for row 1 is received, the suspended data load operation of command packet 880 is replied at time t2. The data payload in the data column of the command packet 884 contains 1856 bytes of data that are not latched. Subsequently, the core operation command packet 886 for row 1 and the core operations for the planning data for row 1 begin at time t3. Finally, the core operation for draining is completed at time t4, and the burst read command packet 888 for draining is issued by the memory controller and latched for the memory device. When the DSI is at a high logic level, the data is read and then output as a data read packet 890. -36- 200828338 However, because a large amount of data is output, the host system may want to confirm the completion of the plan for the row 1, because the controller will know that the planning operation should be completed within a predetermined time, for example, time t6. Before sending the read status request, unlike waiting for all read data to be output, the output of the read data can be suspended at time t5 by releasing the DSI. Once the data output operation is suspended, a read status command packet 892 is issued by the memory controller and latched for the memory device. Then, a corresponding read data packet 894 containing a state register 値 is provided. When the DSI is released at the end of the read data packet 894, the burst read can be resumed. This is done by having the memory controller issue a burst read command packet 896 for the drain, which will include the address of the next bit before the suspend read at time t5. At time t7, the remaining 1600 bytes are output by the Qn output port as a read data packet 889. The suspension operation example of Figure 15 shows the advantages of a modular command structure for performing simultaneous operations, each of which can be suspended and replied to maximize core utilization and channel utilization. The exemplary sequence and operation of Figures 11 through 15 depends on the CSI and DSI strobe signals to provide information about the command packet or the read data packet. Because the command packet is variable in size, no header information is used to indicate the bit length of the command packet, and the CSI strobe signal is actuated as a header for the command packet, and the command packet is connected in parallel with the data command packet. Provide it. The CSI signal used to command the length of the packet is active and is used by the memory device to latch the command packet data present at the Dn input to the appropriate register. The DSI signal is activated when the length of the data packet is expected to be read -37-200828338, which is known to the memory controller and is paralleled with the read data packet. Therefore, the actuating DSI signal is actuated as a header for reading the data packet. Therefore, the length of the command packet and the read data packet correspond to the length of its individual CSI and DSI strobe signals. Because the reading of the poor material package and the command packet is the same signal line connected between Dn and Qn of the adjacent memory device, the specified data of the CSI strobe with the data is the command data packet, and the data has The designated data for the presence of DSI strobes is read data. Therefore, the strobe signal indicates the type of data that travels through the memory system. The memory controller will track its issued DSI strobe so that it can match the received data packet and the type of data expected. For example, the read data packet can contain status register information or data read from the memory array. For the functional correlation of CSI and DSI signals, the minimum separation time is inserted between any type of subsequent strobe signals. This is used to ensure that each command packet and read data packet are distinguishable and defined, and that the appropriate type of data is latched by the memory device of the memory controller. There are four possible states for using split. There are CSI-to-CSI separation (tccs), CSI-to-DSI separation (tCDS), DSI-to-CSI separation (tDCS), and DSI-to-DSI separation (tDDS). The CSI-to-CSI split (tccs) is the minimum split time in the clock cycle (tCK) between consecutive command packets to the same or different devices. This split time allows the previous command to be cleared by the memory device by clearing the command register and resetting any command logic, such as when preparing a new command. DSI-to-DSI separation (tDDS) is the continuous reading of the same device -38- 200828338 The minimum separation time in the preparation clock cycle (tCK) between packets. This split time allows the output buffer circuit to be reset when it is ready to output the next data. DSI-to-CSI separation (tDCS) is the minimum separation time of the clock period (t c κ ) between the read data packet and the subsequent command packet for the same or different devices. CSI-to-DSI separation (tCDS) is the minimum separation time between the command packet and the read data packet of the same device. These two separate times ensure that the appropriate data type is latched by the memory device, as both may appear continuously within the Dn input port of the memory device. Since the memory controller issues CSI and 081 signals and knows the length of the command packet or data bit, this ensures that the command packet and the data packet are separated by the same minimum time as a strobe signal. Examples of these separate times are indicated in Figures 1 through 14 and it should be noted that the minimum split time can be a data latch for the clock, which can be a fraction of a clock cycle, depending on the data rate architecture used. . For example, in a single data rate architecture (SDR) where data is latched on the rising edge of the clock, the minimum separation time will be one clock cycle or period. In the double data rate architecture (DDR) where the data is latched on the rising and falling edges of the clock, the minimum separation time will be one clock cycle. 5. Figures 11 to 15 are examples of simultaneous operation in a single memory device, and the correlation of CSI-to-DSI separation or DSI-to-CSI separation is not clearly shown. Figure 16 is a sequence diagram showing the correlation of CSI-to-DSI or DSI-to-CSI. Figure 16 is an exemplary situation in which the first memory device outputs its read data from its Qn output and the second serially connected memory device receives a command packet after the read data is output by the first memory device. The two memory devices shown in this example -39 - 200828338 may, for example, correspond to those shown in Figures 4 and 5. The signal traces for DSI-1, CSI-1, DS01, CSO-1, and Qn-1 are displayed for the first memory device, and the attached "_1" indicates the 第一 of the first memory device. The signal traces for DSI-2, CSI-2, and Dn-2 are displayed for the second memory device, and the attached "_2," represents the second memory device. It is assumed that the first memory device has previously received one or more command packets for reading from it. As a result, DS_1 receives the strobe signal 900 for outputting the data to Qn_:i for reading the data packet 902. The read data packet 902 is labeled "Qn_l read data". Since the read data and the strobe signal are transmitted in series from the first memory device to the second memory device, DSO_1 transmits the strobe signal received from DSI_1埠 to DSI_2埠 of the second memory device. Similarly, the read data packet 902 is transmitted from Qn_i of the first memory device to DN_2 of the second memory device. The memory controller issues a location to the second memory device command packet 904, labeled "Dn_2 CMD Data", followed by a CSI strobe signal 906. The strobe signal 906 is transmitted via CSI_1 via the first memory device and the command packet is transmitted via the Dn input port of the first memory device (not shown in Figure 16) and transmitted via the Qn_1 output 埠. The first memory device will ignore the command packet 904 because it is for the second memory device. The first memory device then transmits the selected communication number 906 to CS_2璋 of the second memory device by its CS〇_1埠, and transmits the command packet 904 to the Dn_2 input of the second device via its Qn_1 output. Because there is a minimum separation tCDS between the falling edge of the strobe signal 900 and the rising edge of the strobe signal 906-40-200828338, and a minimum between the last bit of the read data packet 902 and the first bit of the command packet 904 Separate, so the second memory device will reliably latch the command packet 904 in the appropriate register. On the other hand, if the command packet 904 and its corresponding strobe signal 90 6 are sent without any separate tCDS, the second memory device can latch the read data bit of the read data packet 902 to become one of the command packets 904. Part. Therefore, the minimum separation ensures that there is no mix of data types. The memory device, particularly the non-volatile memory device, in the previously described memory system has the advantage that it retains the stored data when no power is supplied to the memory device. However, the transfer of full power operation with no power or potential savings may jeopardize the integrity of the stored data. Fig. 17A shows a flash memory device to which the embodiment of the present invention can be applied. Referring to FIG. 17A, a flash memory 1010 includes, for example, a logic circuit of a control circuit 1 0 1 2 for controlling various operations of the flash circuit; and an address register 10 12a for storing an address Information; a data register 1012b for storing planning information; a command register 1012c for storing command data information; a high voltage circuit for generating required planning and erasing voltage; and a core memory circuit For accessing the memory array 1014. The control circuit 1012 includes a command decoder and logic for performing internal flash operations such as reading, planning, and erasing functions. Those skilled in the art will appreciate that these operations can be performed in response to command data stored in command register 1012c, sometimes in conjunction with address data stored in individual address register 1012a and data register 1012b. -41 - 200828338 and planning information, depending on the operation to be performed. The command data, address data, and planning data are issued by a memory controller and latched into the corresponding register for the flash memory 1 〇 1 2 . The circuit block functions shown in flash memory 1 0 1 0 are known in the art. It will be appreciated by those skilled in the art that the flash memory 1 0 1 0 shown in Figure 1 represents one of many possible architectures that may be a flash memory architecture. For proper operation of the flash memory 1 0 1 0, the scratchpad storage address, data and command information must be reliable. An improper storage in the scratchpad caused the device to malfunction. For example, the varying voltage may cause the scratchpad to randomly change the state of the information stored in the command register 10 12c, possibly resulting in a bit pattern corresponding to the receive plan or erase command. In this example, a dummy pseudo-planning operation will cause the random data in the data register 1012b to be mapped to a random address in the address register 1012a of the memory array 1014. If the data exists at this address, the memory cell corresponding to that address will be subject to the planned voltage and its threshold voltage will change. A dummy erase operation may result in the erasure of the presence of data in the memory array 1 01. Since the memory controller is not known to be a fake operation performed by the flash memory 1010, the lost data cannot be recovered. The flash memory 1 〇 1 0 register is typically constructed with a two-state flip-flop circuit. Type D flip-flops are known in the art, as shown in Figure 17. The D-type flip-flop 1 0 50 has a D input 'to receive the input data D_IN, which is internally latched at the edge of the clock signal CLK, such as the rising edge of CLK. When latched, the Q-output will provide D_OUT corresponding to the D_IN logic state, while the complementary Qb output will provide D_OUTb corresponding to the D_IN logic-42-28828 state inversion. A reset input clears the latch 'and the signal RESET is at the active level, such as Vss or ground. Each flip-flop circuit stores one bit of data, and the command register l〇12c will contain most of the flip-flop circuits. As is known in the art, the flip-flop circuit can include a pair of cross-connected inverter circuits. Figure 18 shows the voltage source vcc, the low active logic level reset signal RST#, and the low active logic level enable signal CE# during power and power down operation in a typical flash memory 1010. In a typical power supply operation, at turn-on time t0N, supply voltage Vcc is shifted from a low GND or Vss voltage level to a high Vcc voltage level. The Vcc voltage level rises and reaches a stable voltage level VST at time tST, at which point the flash memory 1010 can operate. Finally, at time tv, the Vcc voltage level reaches the maximum 値Vcc level. The device reset and enable signals RST# and CE# are respectively received by an associated memory controller and simultaneously driven to a non-active high logic level at time t0N, but following the rising voltage of Vcc. Once RST# is released, or is at a high level of inactivity, the device is in a "ready" state and is operable to receive commands from the memory controller. Alternatively, while the device is in the reset state, the controller deactivates the CE# signal at time t0N by driving it to the immovable high logic level. Because Vcc rises to the minimum voltage level, CE# will follow the VCC boost. At time tCEOff, the CE# signal can be asserted to allow the device to enter a normal execution state. This time tCEOif occurs after the RST# signal has been released or driven to the inactive high logic state (i.e., after time tv), after a time interval of at least tCE#. Once the unit has entered the normal execution state, the start operation can be performed at the device level and system level -43-200828338. However, at the vcc transfer time, i.e., from time t〇N to time tv, or at least to time tST, the control signal to the register cannot be accurately controlled. This may cause the dummy information to be stored in various registers of the flash memory 1010, resulting in improper planning or erasing of the data, resulting in loss of data integrity in the flash memory 1 〇 10 . Due to the involuntary planning/erasing operation during power transfer, the loss of data integrity caused by this generation is exacerbated in this generation of flash memory devices. This generation of memory devices requires speed, size reduction, and To have low power consumption, this requires the flash device to operate frequently at a lower Vcc voltage level. The lower vcc level amplifies the problem that dummy information is stored in the registers of the flash device, thereby adversely affecting data reliability. This case describes a method of data protection when power is transferred to a non-volatile memory device, such as during a power operation or a power down operation. A reset signal is asserted to de-function the memory device before claiming any power transfer. The reset signal is maintained for a predetermined time while the device voltage is expected to stabilize. At this time, all internal registers, such as the device's command register, are set to default to prevent data loss due to the dummy/erase commands executed by the device. FIG. 19 is a diagram showing a voltage source Vcc, a low-state effective logic level reset signal RST#, and a low-state effective logic level in the power supply and power-off operation in the non-volatile memory device according to the embodiment of the present invention. Can signal CE#. As mentioned earlier, at time, the Vcc voltage is shifted from a low GND or Vss voltage level to a high VCC voltage level. Alternatively, the Vcc voltage level can be shifted from the low - 44 - 200828338 power level to the vcc voltage level. In time, the Vcc voltage level rises and exceeds a stable voltage level VST that can be operated by a flash memory 1 〇 1 时间 at time tST. Finally, at time tv, the 'Vcc voltage level reaches the maximum vcc level. However, in order to prevent the device from malfunctioning due to the false information being latched into the command register, for example, the controller of the memory controller of the non-volatile memory device retains the RST# signal in the low active logic level to go All functions of the device can be a waiting time period, which is at least the time taken for the Vcc voltage level to reach the stable VST voltage level (time t0N to tST). In the embodiment shown in Fig. 19, the RST# signal is held at the low active logic level for an extended time period tRST (from time t〇N to tST) plus the stable voltage level VST at the Vcc level. After at least one time interval U. When the RST# signal is at the active low logic level, the internal registers of all devices will therefore remain in a preset or reset state. Finally, the controller will release RST# after the time interval tRST, as shown in Figure 19. Shown. At this point, power will stabilize and the device components can be ready or initiated. Alternatively, when the device is in the reset state, at time t0N, the controller deactivates the CE# signal by driving it to a high logic state that is not active. Since VCC rises to its maximum voltage level, CE# will follow VCC rise. The CE# signal is asserted at time tCEOff to allow the device to enter a normal execution state. The time tCEOff occurs after a time interval of at least t2, after the RST# signal is released, or after driving to a high logic level that is not active. Once the device enters a normal execution state, the initiation operation can be performed at the device level or system level. During the power conversion operation, the device is held in a reset state for a predetermined amount of time to prevent the dummy information from being stored or latched to the registers of the device. The device is therefore protected against improper and careless planning or erasure of data to ensure complete data integrity during power conversion. A similar procedure ensures that data protection can be followed during power down operations, by when vcc is turned off and driven to When the GND or Vss voltage level is low, at a predetermined time, before t0FF, it is claimed that 1^丁#, or drive 1187# to the low active logic level. A flow chart showing the method of data protection at the time of power conversion is shown in Fig. 20 in a non-volatile memory device according to an embodiment of the present invention. A memory controller that controls a non-volatile memory device, such as a flash memory device, maintains RST# low before any power conversion (step 1100) to cause the device to be in a reset state. At this time, the internal register of the device is set to a preset or reset state. The controller then allows power conversion (step 1102) and waits for a preset time to wait for the internal voltage of the device to stabilize (step 1104). The wait time period corresponds to tRST shown in Figure 19, and at least the time it takes for the Vcc voltage level to reach the stable VST voltage level (time t0N to tST) plus after the Vcc level reaches a stable voltage level VST At least one time interval t 1 . The time interval t 1 can be determined based on, for example, operating voltage and device characteristics of the processing technique. For example, the total time period in which RST# remains low', that is, t r s τ may be 1 〇 microsecond or more. During the time period of the device, various components are stabilized and the clock becomes operational and becomes frequency and phase stable. After the elapse of time period tRST, when the device expects to be in the "standby" state -46-200828338, the controller asserts the RST# high signal (step 1106). The controller asserts the CE# signal at time t0N as described with reference to Fig. 19, while the device is in the reset state and is released at RST# to release the memory device from the reset condition. The CE# signal is released at time tCEOff to allow the device to enter a normal execution state. The time tCEOff is after at least one time interval of t2, after the RST# signal has been asserted. Once the device enters the normal execution state, the start operation can be performed at the device level or system level (step Η 08). Similar to time U, the time interval t2 can be determined based on device characteristics and will be systematically changed from one memory system to another. For example, t2 can be 100 microseconds or more. Figure 21 depicts the steps involved in the device during power transfer to ensure data protection in accordance with embodiments of the present invention. Prior to any power transfer, the non-volatile memory device receives a RST# low signal from a memory controller that controls the device (step 1200). The device then receives power from the controller to actuate the device component (step 1202). This received power can be increased from the V S S voltage or from a low power mode voltage level to the full VCC operating voltage level. Because the RST# signal is very low, the device is placed in a reset state. At this point, the device's internal registers and any finite state machines are set and maintained in a preset or reset state (step 1204). Before asserting that RST# is high, the controller then waits for a predetermined period of time to wait for the internal voltage of the device to stabilize. After the elapse of time period tRST, the controller asserts a RST# high signal when the device is expected to have a "ready" state. The device receives the RST# high signal and places the device in "Preparation, State (step 1 206). At time tCEOff, the controller asserts the CE# signal, -47 - 200828338 to allow the device to enter a normal execution state. As previously mentioned, - Once the device enters the normal execution state, the start operation can be performed at the device level (step 1 208). In the power conversion in the memory system 200 of Fig. 4, the method of data protection is discussed. The body controller 202 will keep reset (RST#) low to keep all memory devices 204, 206, 208, and 210 reset, while power stabilization and device preparation operations. After Vcc is stabilized, RST# will be Controller 202 is held low for a minimum time t1 (e.g., 20 microseconds) as shown in Figure 19. When RST# is held low, all finite state machines in memory are initiated, and any architecture And the status register is reset to its preset or reset state. When RST# is released to a high logic level, the clock becomes operational and becomes frequency and becomes frequency and phase stable. Refer to Figure 19 as before. As shown, at time t0N, The controller 202 releases the CE# signal, and at the same time, the device is in the reset state and the main lengths CE# and RST# have been released. The CE# signal is asserted at time ^(9)^ to allow the device to enter the normal execution state. The time tCEOff is at t2 After the time interval elapses, after the RST# signal is asserted, once the device enters the normal execution state, the start operation can be performed at the device level and the system level. The initialization operation example includes the device address and the identification code generation, and The designation of each device in a series connection. The various device addresses and methods for generating the identification code are described in co-pending U.S. Patent Application Serial Nos. 1 1/622,828; 1 1/750,649; 11/692,452; 11/692,446; 11/692,326; and 11/771,023. By ensuring that the device is in a reset state for a predetermined amount of time, during the power transfer -48-200828338 operation, the dummy information is prevented from being stored or latched in the temporary storage of the device. The device is thus protected against improper planning or erasure of the data to ensure the integrity of the data during power transfer. In the foregoing description, various details have been described for the purpose of explanation. The embodiments of the present invention are fully understood. However, it will be understood by those skilled in the art that these specific details are not required in the practice of the present invention. For example, the known electrical structures and circuitry are shown in block diagrams. The present invention is hampered. For example, the specific details described in connection with the sinus embodiment of the present invention are provided as software routines, hardware circuits, firmware, or combinations thereof. Embodiments of the invention may be stored in a machine readable form. Media (referred to as computer readable media, processor readable media, or computer readable program core embodiments) is represented by software in a computer usable medium. The machine readable medium can be any suitable physical medium, including magnetic, optical or electrical storage media containing discs, compact discs (CD-ROMs), memory devices (volatile or non-volatile), or similar storage media. The machine readable medium can contain various sets of instructions, code sequences, architectural information, or other materials that, when executed, cause a processor to perform the steps of the method in accordance with embodiments of the present invention. It will be appreciated by those skilled in the art that other instructions or operations to perform the described invention may also be stored in a machine readable medium. The software executed by the machine readable medium can interact with the circuitry to perform the desired work. The above embodiments of the present invention are merely illustrative. Various changes, modifications, and variations can be made by those skilled in the art without departing from the scope of the invention, and the scope of the invention is defined by the scope of the appended claims. -49 - 200828338 [Simplified Schematic] FIG. 1 is a schematic diagram of a prior art NAND flash memory core; FIG. 2 is a block diagram of a prior art flash memory system; FIG. 3A is a serial memory system Figure 3B is a block diagram of a series memory system composed of NAND flash memory devices; Figure 3C is a block diagram of a series memory system constructed by mixing different memory devices; The figure shows a block diagram of the parallel clock design in the series memory system architecture of Figure 3A; Figure 5 is a block diagram of the active synchronous clock design of the series memory system architecture in Figure 3A; Figure 6 is a dynamically adjustable series memory. Block diagram of the body system; Figure 7 is a block diagram of a memory device having a local core and serial input/output interface for the series memory system of Figures 3A to 3C and 4 to 6; Figure 8 is a module Figure 9 is a schematic diagram of a structure of a command packet; Figure 9 is a flowchart for illustrating a module command packet for operating a flash memory device of Figure 7; Figure 10 is a flow chart for performing a simultaneous operation method in a memory device Figure 11 is a timing diagram of simultaneous read operations for two different banks of memory devices; Figure 12 is a timing diagram for simultaneous operation of the memory devices for two different banks - 50-200828338 Figure 13 is a timing diagram of simultaneous reading and planning operations for two different banks of memory devices; Figure 14 is a timing diagram for simultaneous block erase of memory devices for two different banks; Figure 15 is a timing diagram of simultaneous planning and reading operations of different memory devices with suspension and recovery operations. φ Figure 16 is a timing diagram for the operation of two serially connected memory devices; Figure A is a block diagram of a flash memory device applicable to the embodiment of the present invention; Figure 17B is a schematic diagram of the flip-flop; Figure 18 is a diagram of the power supply and power-off operation of the flash memory device of Figure 17A. Timing diagram of various control signals; Figure 19 is a timing diagram of each control signal during power supply and power-off operation of a non-volatile memory device; # Figure 20 is a power conversion in a non-volatile memory device, Data protection method Chart; and graph 21 of the present invention according to another embodiment of the non-volatile memory when the power converter embodiment, the method of flowchart data protection apparatus. [Main component symbol description] 30 : Row 32 : Data register 1 〇: Flash memory system -51 - 200828338 1 2 : Host system 1 4 : Memory controller 1 6 : Non-volatile memory device 1 8 : Channel 100: series memory system 102: memory controller 104: memory device 0 106: memory device 108: memory device 1 1 〇: memory device 1 1 2 : memory device 1 1 4 : memory Device 1 1 6 : Memory device 200 : Series memory system 202 : Memory controller # 204 : Memory device 206 : Memory device 208 : Memory device 2 1 0 : Memory device 3 0 0 : Serial memory system 3 02 : Billion Body Controller 3 04 : Memory Device 3 06 : Memory Device 3 08 : Billion Body Device - 52 - 200828338 3 1 0 : Memory Device 400 : Adjustable Series Memory System 402 : Memory Controller 404: memory device 406: memory device 408: memory device 4 1 0 : memory device φ 4 1 2 : extended link 4 1 4 · extended bond 4 1 6 : extended link 4 1 8 : extended chain Junction 420: Expansion Link 422: Expansion Module 424: Expansion Module 426: Expansion Module • 428: Jumper 4 3 0 : Jumper 500: remembers the body device 502: memory array row 5〇4: memory array row 5 06: local control and I/O circuit 5 0 8: serial interface and control logic block 6 0 0 : Command packet 6 0 2 : Command packet -53- 200828338 604: Address field 606: Data field 608: Device address field 610: Op-code field 800: Page read command packet 8 02 : Page read command packet 8 04 : Crowd read command packet φ 806: read data packet 808: burst read command packet 8 1 0: read data packet 8 2 0: command packet 822: command packet 8 24: burst data load command packet 826: page read command packet 828: read status command packet Φ 830: read data packet 8 3 2: read status command packet 834: read data packet 840: page read command packet 8 42: burst data Incoming command packet 844: page read command packet 846: burst read command packet 848: read data packet 8 5 0: burst data status command packet -54- 200828338 852: read data packet 860: block erase bit Address input command packet 862: erase command packet 864: block erase address input command packet 866: wipe Command packet 8 6 8 : Read status command packet 870 : Read status command packet φ 872 : Read data packet 8 74 : Read data packet 8 80 : Crowd data load start command packet 8 82 : Page read command Packet 8 8 4: Crowd Data Loading Command Packet 8 8 6 : Page Read Command Packet 8 8 8 : Crowd Read Command Packet 890 : Data Read Packet # 892 : Read Status Command Packet 894 : Read Data Packet 8 9 6: burst read command packet 898: read data packet 900: strobe signal 902: read data packet 904: command packet 906: strobe signal 1 〇1 〇: flash memory -55- 200828338 1 0 1 2 : Control circuit 1012a : Address register 1012b : Data register 1012c : Command register 1 〇 1 4 : Memory array 1 05 0 : D-type flip-flop