KR101476463B1 - scalable memory system - Google Patents
scalable memory system Download PDFInfo
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- KR101476463B1 KR101476463B1 KR1020097005767A KR20097005767A KR101476463B1 KR 101476463 B1 KR101476463 B1 KR 101476463B1 KR 1020097005767 A KR1020097005767 A KR 1020097005767A KR 20097005767 A KR20097005767 A KR 20097005767A KR 101476463 B1 KR101476463 B1 KR 101476463B1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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Abstract
The memory system architecture has memory devices connected in series. The memory system is scalable to include any number of memory devices without any performance penalties or complex redesign. Each memory device has a serial input / output interface for communication between the other memory devices and the memory controller. The memory controller issues instructions in at least one bitstream, where the bitstream is in accordance with a modular instruction protocol. The instruction includes an operation code with optional address information and a device address, so that only the addressed memory device follows the instruction. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream to identify the type of data and the length of the data. The modular command protocol is used to perform concurrent operations on each memory device to further improve performance.
Description
This application is related to U.S. Provisional Patent Application No. 60 / 839,329, filed August 22, 2006; U.S. Provisional Patent Application No. 60 / 868,773, filed December 6, 2006; U.S. Provisional Patent Application No. 60 / 902,003, filed February 16, 2007; U.S. Provisional Patent Application No. 60 / 892,705, filed March 2, 2007, and U.S. Patent Application No. 11 / 840,692, filed August 17, 2007, all of which are incorporated by reference herein.
The present invention relates generally to memory systems. More specifically, the present invention relates to a memory system of a serially-connected memory device for mass storage applications.
Flash memory is a commonly used type of nonvolatile memory that is widely used as a mass storage device for consumer products such as digital cameras and portable digital music players. The density of flash memory chips currently on the market may be up to 32 Gbits (4 GB), which is suitable for use with popular USB flash devices due to the small size of a single flash chip.
1 is an overall block diagram of one bank of a known NAND flash memory. Those skilled in the art will appreciate that flash memory devices may have any number of banks. The
Outside the
The advent of portable digital entertainment devices with 8 megapixel digital cameras and music and video capable outputs has increased the need for ultra high capacity to store large amounts of data that can not be satisfied by a single flash memory device. Thus, a plurality of flash memory devices are combined together in a memory system to efficiently increase available storage capacity. For example, a 20 GB play storage density may be required for such applications.
2 is a block diagram of a prior art
The
In the
There is a special problem that adversely affects the performance of the system. The configuration of the
Since the drive capability of a single memory device is small compared to loading of long signal tracks, there is also a practical limit to the number of memory devices that can be connected in parallel to the channel. In addition, as the number of memory devices increases, more chip enable signals CE # are required, and the clock signal CLK needs to be routed to additional memory devices. Clock performance issues due to extended clock distribution are well known in the art and need to be addressed. Thus, to accommodate a large number of memory devices in a memory system, a controller with more channels needs to be used, and / or the system needs to be clocked at a lower frequency. A controller configured to have a plurality of channels and an additional chip enable signal increases the cost of the memory system. Otherwise, the memory system is limited to a small number of memory devices.
Accordingly, it is desirable to provide a memory system architecture capable of supporting any number of memory devices.
It is an aspect of embodiments to remove or mitigate at least one drawback of the prior memory system.
In a first aspect, a memory system having a controller and a memory device is provided. The controller includes a serial channel output port providing a serial bitstream command packet and a serial channel input port receiving a serial bit stream read data packet. The serial bitstream instruction packet includes an operation code and a device address. The memory device having an input port for receiving the serial bitstream instruction packet from the controller and for executing the operation code if the device address corresponds to the memory device. The memory device provides the serial bitstream command packet through an output port and then provides the serial bit stream read data packet through the output port if the operation code corresponds to a read function.
According to one embodiment of this aspect, there is at least one intervening memory device connected in series between the memory device and the controller. Wherein the at least one intervening memory device has an input port for receiving and delivering the serial bitstream instruction packet to the memory device and then if the device address corresponds to the memory device and the operation code corresponds to a read function, Bit stream read data packet.
According to another embodiment, a complementary clock signal is provided in parallel to the memory device and the at least one intervening memory device, or a complementary clock signal is provided to the at least one intervening memory device, And transferred to the memory device by the memory device.
According to another embodiment of this aspect, a memory system includes an expansion link between the controller and the memory device and an expansion link for receiving one of the jumper. The at least one intervening memory device is part of an expansion module having connection means configured for electrical connection with the expansion link.
According to yet another embodiment, the memory device and the at least one intervening memory device each include a native memory core and a serial interface, and a controller for controlling the native memory core in response to the serial bitstream command packet Control logic block. The memory device native memory core and the at least one intervening memory device native memory core may be NAND flash based, or may be DRAM, SRAM, NAND flash, and NOR flash memory cores.
According to another embodiment of the present aspect, the serial bitstream command packet has a modular structure in which the size of the serial bitstream command packet is variable. The serial bitstream instruction packet may include an instruction field providing the operation code and the device address, wherein the instruction field comprises a first subfield providing the operation code and a second subfield providing the
According to one aspect of the previous embodiment, the controller provides an instruction strobe in parallel with the serial bitstream instruction packet, and the instruction strobe has an active level consistent with the length of the serial bitstream instruction packet.
The controller also provides a data input strobe in parallel with the serial bit stream read data packet, and the data input strobe has an active level that matches the length of the serial bit stream read data packet. Wherein the memory device latches the serial bitstream instruction packet in response to the active level of the instruction strobe when the device address corresponds to the memory device and the memory device output port is responsive to the active level of the data input strobe Lt; / RTI > The command strobe and the data input strobe are non-overlapping signals and are separated by at least one data latching clock edge. [0222] Optionally, the instruction strobe is separated from adjacent instruction strobe by at least one latching clock edge, and the data input strobe is separated from adjacent data input strobe by at least one latching clock edge.
In a second aspect, an instruction packet is provided that includes a series of bits for a memory system having a memory device connected in series. The instruction packet includes an instruction field for selecting a memory device of one of the serially connected memory devices to execute a specific memory operation.
In one embodiment of the second aspect, the instruction field includes a first sub-field providing a device address for selecting the memory device, and a second sub-field providing an op- eration code corresponding to the particular memory operation. Wherein the instruction packet further comprises an address field subsequent to the instruction field providing one of a row address and a column address when the operation code corresponds to a read or write operation and wherein the address field is associated with the row address or the column address And has a corresponding bit length. Wherein the command packet further comprises a data field subsequent to the address field for providing write data for storage in the memory device when the operation code corresponds to the write operation, Lt; / RTI >
In a third aspect, a method is provided for performing concurrent operation in a selected memory device of a memory system having a serially-connected memory device. The method includes receiving a first command; Executing a core operation in a first memory bank of the selected memory device in response to the first instruction; Receiving a second instruction while executing a core operation in the first memory bank; And executing a core operation in a second memory bank of the selected memory device in response to the second instruction.
According to an embodiment of the third aspect, there is provided a method comprising: receiving a third instruction requesting result information from one of the first memory bank and the second memory bank; and receiving the result information in response to the third instruction And outputting the read data packet. The result information includes one of status register data and read data.
In another embodiment of this aspect, the first instruction, the second instruction, and the third instruction may comprise a mandatory command field providing an operation code and a device address, a row of instructions that when the operation code corresponds to a read or write operation, An optional address field following the command field providing one of the column addresses, and an optional data field following the address field providing write data when the operation code corresponds to the write operation. Lt; / RTI >
In one aspect of the present embodiment, a first command strobe is received in parallel with the first command, the first command strobe has an active duration corresponding to the length of the first command, 2 instruction, and the second instruction strobe has an active duration corresponding to the length of the second instruction. The first instruction strobe and the second instruction strobe are separated by at least one data latching clock edge. A data input strobe is also received to enable the output of the read data packet while the data input strobe is at an active level, the second instruction strobe and the data input strobe being coupled by at least one data latching clock edge Separated.
In another embodiment, the method further comprises powering up the selected memory device prior to receiving the first command. Raising the power comprises: asserting a control signal to maintain the selected memory device in a default state prior to power transfer; Transitioning the power level of the selected memory device from a first voltage level to a second voltage level while the control signal is asserted; Waiting for a predetermined duration so that the power level is stabilized; And de-asserting the control signal to release the selected memory device from the default state, thereby preventing an accidental program or erase operation in the selected memory device. The second voltage level may be a minimum voltage level for stable circuit operation or a maximum operating voltage level of the power source. The first voltage level may correspond to the low power mode operating voltage level of the power supply, or the absence (absence) state of the power supply.
In yet another embodiment, maintaining the memory device in the default state includes setting a device register in the memory device to a default value, wherein the device register includes an instruction register. The further step of the method may further comprise performing device initialization upon release of the memory device from the default state. The step of performing the device initialization may comprise generating a device address and device identifier information for the memory device.
In another embodiment, the step of raising the power comprises: asserting a control signal at a first time to keep the memory device in a default state prior to power transfer; Transitioning the power level of the memory device from a first level to a second level at a second subsequent time while the control signal is asserted; Waiting for a predetermined duration so that the power level is stabilized; And deasserting the control signal at a third subsequent time to release the memory device from the default state, thereby preventing an accidental program or erase operation in the memory device.
In a fourth aspect, a memory system is provided that includes a plurality of memory devices and a controller for controlling the devices. The controller has an output port for providing a bitstream command packet to a first one of the plurality of memory devices, wherein the bitstream command packet includes an operation code and a device address. Wherein each of the plurality of memory devices receives the bitstream command packet from one of the controller and an advanced memory device and executes the opcode if the device address corresponds thereto, Providing a command packet to one of the next memory device and the controller, wherein a bitstream read data packet is provided from the last of the plurality of memory devices to the controller if the opcode corresponds to a read function.
According to one embodiment of this aspect, the plurality of memory devices are connected in series, the first and last memory devices are connected to the controller, and the controller is operable to cause the first device of the plurality of memory devices, And transmits a data packet. The bit stream data packet and the bit stream read data packet from the controller comprise a serial bit stream or a parallel bit stream. The plurality of memory devices is one of a mixture of memory devices of the same type or of different types.
According to another aspect, there is provided a memory system including a plurality of memory devices and a controller for controlling the device, the memory system being capable of performing a function of powering up a selected memory device before receiving a first command.
For example, the power-up function may include asserting a control signal to maintain the selected memory device in a default state prior to power transfer; Transitioning the power level of the selected memory device from a first voltage level to a second voltage level while the control signal is asserted; Waiting for a predetermined duration so that the power level is stabilized; And deasserting the control signal to release the selected memory device from the default state, thereby preventing an accidental program or erase operation in the selected memory device. In addition, the power raising function may include asserting a control signal at a first time to maintain the memory device in a default state prior to power transfer; Transitioning the power level of the memory device from a first level to a second level at a second subsequent time while the control signal is asserted; Waiting for a predetermined duration so that the power level is stabilized; And deasserting the control signal at a third subsequent time to release the memory device from the default state, thereby preventing an accidental program or erase operation in the memory device.
Other aspects and features of the present invention will become apparent to those skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying drawings.
Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings.
1 is a schematic diagram of a prior art NAND flash memory core.
2 is a block diagram of a prior art NAND flash memory system.
3A is a general block diagram of a serial memory system.
3B is a block diagram of a serial memory system comprised of a NAND flash memory device.
3C is a block diagram of a serial memory system made up of a mixture of different memory devices.
Figure 4 is a block diagram of the serial memory system of Figure 3A configured with a parallel clock scheme.
Figure 5 is a block diagram of the serial memory system of Figure 3A configured with a source synchronous clock scheme.
Figure 6 is a block diagram of a dynamically adjustable serial memory system.
Figure 7 is a block diagram of a memory device having a serial input / output interface and a native core suitable for use in the serial memory system of Figures 3A-3C and 4-6.
8 is a diagram showing a modular command packet structure.
Figure 9 shows a table listing examples of modular instruction packets operating the flash memory device of Figure 7;
10 is a flowchart of a method of simultaneously executing an operation in one memory device.
11 is a sequence diagram illustrating simultaneous read operations for two different banks of a memory device.
12 is a sequence diagram illustrating concurrent programming operations for two different banks of memory devices.
Figure 13 is a sequence diagram illustrating simultaneous read and program operation for two different banks of memory devices.
14 is a sequence diagram illustrating simultaneous block erase for two different banks of memory devices.
15 is a sequence diagram showing simultaneous programming and read operations for two different banks of memory devices in a pause and resume operation;
16 is a sequence diagram showing the operation of two serially connected memory devices.
17A is a block diagram of a flash memory device to which embodiments of the present invention may be applied.
17B is a schematic diagram of a flip-flop.
FIG. 18 is a sequence diagram of various control signals during the power-up and power-down operations in the flash memory device of FIG. 17A.
19 is a sequence diagram of various control signals during power-up and power-down operations in the nonvolatile memory device.
20 is a flow chart illustrating a method for protecting data during power transition in a non-volatile memory device.
21 is a flowchart illustrating a method of protecting data during power transition in a non-volatile memory device according to another embodiment of the present invention.
In the following detailed description of embodiments of the present invention, reference is made to the accompanying drawings which form a part which, by way of illustration of specific embodiments in which the invention may be practiced, may be embodied. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that logical, electrical, and other changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
A memory system architecture with serially connected memory devices is described. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input / output interface for communication between the other memory devices and the memory controller. The memory controller issues instructions in at least one bitstream, where the bitstream is in accordance with a modular instruction protocol. The instruction includes an operation code with optional address information and a device address, so that only the addressed memory device follows the instruction. A separate data output strobe and command input strobe signal are provided in parallel with each output data stream and input command data stream to identify the type of data and the length of the data. The modular command protocol is used to perform concurrent operations on each memory device to further improve performance.
3A is a block diagram illustrating conceptual features of a serial memory system architecture according to one embodiment. In Figure 3A, the
Although the current embodiment includes seven memory devices, alternate embodiments may include up to one memory device and any number of memory devices. Thus, since the
The
The channel of the
In a typical operation, the
Since the instructions and data are provided in a serial bitstream, a clock is used by each memory device to clock in and out the serial bits and to synchronize internal memory operations. This clock is used by all the memory devices in the
FIG. 3B is a block diagram illustrating that the memory system of FIG. 3A may include one type of memory device, such as a NAND flash memory device. Each NAND flash memory device may be different from, or identical to, each other, for example, by having different storage densities. FIG. 3C is a block diagram illustrating that the memory system of FIG. 3A may include various types of memory devices. These memory devices may include, for example, a NAND flash memory device, a NOR flash memory device, a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a magnetoresistive random access memory have. Of course, alternative memory devices not mentioned here may be employed in the memory system. A configuration with such a mixed type of memory device is disclosed in U. S. Patent Application 60 / 868,773, filed December 6, 2006.
Figure 4 is a block diagram of a serial memory system using a parallel clock scheme. The
The channel of the
The data latching clock edge may be, for example, a rising clock edge. If n is 2, one byte of data is received after four latching edges of the clock. If n is 4, one byte of data is received after two latching edges of the clock. The memory device may be statistically constructed or dynamically configured for Qn and Dn of any width. Thus, in a configuration where n is greater than one, the memory controller provides the data as a parallel bit stream. CSI is used to latch the command data appearing at the input port Dn and has a pulse duration corresponding to the length of the received command data. More specifically, the command data will have a duration measured by a number of clock cycles, and the pulse duration of the CSI signal will have a corresponding duration. The DSI is used to enable the output port (Qn) buffer to output data, and has a pulse duration corresponding to the length of the required read data. A more detailed description of the DSI and CSI signals will be discussed later.
4, each memory device has the same serial input / output interface, including RST #, CE #, CK #, and CK input ports, which receive signals of the same name from
In actual implementation of the embodiment of FIG. 4, each memory device is disposed on a printed circuit board so that the distance between the input and output ports and the signal track is minimized. Alternatively, four memory devices may be implemented with a system in package module (SIP), which is a system that further minimizes the signal track length. The
The performance of the memory device in the
An important advantage of the
Although the serial memory system embodiment of FIG. 4 provides significant performance advantages over prior art memory systems, additional performance improvements are obtained using the alternate series memory system embodiment of FIG. The
The main advantage of the embodiment of FIG. 5 is the absence of a minimal clock interconnect between memory devices and some complex clock distribution scheme. Thus, the minimum clock frequency can be increased to 166 MHz, resulting in a data rate of at least 333 Mbps per pin. As in the embodiment of FIG. 4, the embodiment of FIG. 5 may be defined to include any number of memory devices. For example, a fifth memory device may be connected to the
The configuration of the
6 is a block diagram illustrating a dynamically adjustable serial memory system embodiment. The adjustable
The tunable
The serial memory system shown in Figs. 3A to 3C and Figs. 4 to 6 employs a memory device such as a flash memory device having a compatible serial input / output interface. One example of a flash memory device having a serial input / output interface is described in co-owned
According to another embodiment, a serial input / output interface may be used with any type of memory device. More specifically, other memory types may be adapted to operate with the serial input / output interface. FIG. 7 is a block diagram illustrating a conceptual configuration of a general purpose memory device having a serial input / output interface and a native core suitable for use in the serial memory system of FIGS. 3A to 3C and FIGS. 4-6.
Generally, a memory device uses an instruction decoder that asserts the internal control signal to initialize the associated circuitry in response to the received command. These memory devices will also include well-known I / O circuits that receive and latch data, instructions and addresses. In accordance with the present embodiment, the existing I / O circuitry is replaced by a serial interface and control
The serial interface and control
Thus, the serial memory system of Figs. 3A-3C and Figs. 4-6 may include a mix of memory device types that each provide different advantages for larger systems. For example, a high-speed DRAM memory may be used for caching operations, while a non-volatile flash memory may be used for storing large amounts of data. Regardless of the type of memory device used, each memory device is individually addressable to follow the instruction because the serial interface and control logic block 506 is configured to receive commands in accordance with a predetermined protocol.
According to another embodiment, these instructions consist of instruction packets with a modular instruction structure used to control the individual memory devices of the serial memory system. In the proposed command structure, a particular command may be issued to the memory device at another time as a separate command packet. A command packet may initiate a specific operation for the first memory bank and a subsequent command packet may be received to initiate another operation for the first memory bank while the core operation is executed in response to the first command packet . Additional instruction packets may be received to complete operations on the first memory bank and the second memory bank in a similar insertion manner. It is assumed that the operation is performed simultaneously in the memory device. Before discussing concurrent operation, a description of the modular command protocol is given. A more detailed description of the modular command protocol is described in U. S. Patent Application 60 / 892,705, filed March 2, 2007, entitled " Modular Command Structure in Memory System and its Use "
The
The
Fig. 9 lists examples of instruction packets that can be used to operate a flash memory device having the configuration shown in Fig. 7 for use in the serial memory system described above. The byte positions in FIG. 9 correspond to the order in which they are received serially by the memory device. The
Only a memory device having a device address that is to be received serially by each memory device in the system and issued to the
An example of the command packet listed in FIG. 9 indicates flash memory operation. A set of instruction packets for any other type of memory device having different operations may be configured to conform to the described instruction structure.
The previously described command packet may be advantageously used to perform concurrent operation in a memory device, such as
The concurrent operation improves the performance of the system because it does not have to wait until the memory controller completes the first operation before sending the command packet for the second operation. In a typical NAND flash memory device, the memory device will either not accept another command or will respond to a command received for a different memory bank until the core operation is completed for the current memory bank. Thus, the memory device executes several operations in series before accepting another instruction. In a simultaneous operation of this embodiment, one instruction packet initiates one operation in one memory bank and a subsequent instruction packet is received from a second memory bank of the same memory device while the core operation is being executed for the first memory bank Will immediately begin another operation of the < / RTI > Thus, both operations will be executed almost simultaneously by the two memory banks.
10 is a flow chart illustrating a method of performing concurrent operation in one memory device, such as
In
Figures 11-15 are sequence diagrams illustrating examples of concurrent operations that may be performed by a flash memory device of the type described in
11 is a sequence diagram illustrating simultaneous read operations for two different banks of memory devices. The page read
The page read
Since the core operation of
12 is a sequence diagram illustrating concurrent programming operations for two different banks of memory devices. From this point forward, note that the command packet received at the Dn input port of the memory device is forwarded to its Qn output port shown in the Qn signal trace of FIGS. 11-15. To program the memory bank, program data is first programmed for a particular row after being loaded into a data register of a memory device based on a particular column address. In Figure 12, a burst data
If necessary, the memory controller may request the status of the memory device by issuing a read
Figure 13 is a sequence diagram illustrating simultaneous read and program operation for two different banks of memory devices. The page read
14 is a sequence diagram illustrating simultaneous block erase for two different banks of memory devices. A block erase address
In the sequence diagrams of Figures 11-14, different combinations of simultaneous operation are illustrated. An advantage of the modular command packet structure described in the previous embodiments is that different command packets can be issued at different times. As shown above, a page program command packet follows immediately after the burst data load instruction packet. However, this is not always necessary, and a page program command packet may be issued later if desired. When the command packets are used in combination with the command strobe signal (CSI) and the data strobe signal (DSI), a further advantage is realized, which is the ability to pause the operation of the memory device. As previously mentioned, the CSI strobe signal may be provided by the memory controller to indicate that the command data on the Dn input port is to be latched by the command register, and may have a duration corresponding to the length of the command packet being issued . It will be appreciated by those skilled in the art that a relatively long period of time is required to input or output such data amount, since the input data for programming the memory bank and the output data read from the memory bank may exceed 1000 bytes in length. According to the present embodiment, the CSI and DSI strobe signals can be deasserted as soon as program data is loaded or read data is output, and can be resumed at a later time.
Figure 15 is a sequence diagram illustrating simultaneous programming and read operations for two different banks of memory devices, with a pause and resume operation. The burst data load
However, since a large amount of data is output, the host system may want to make sure that programming for
The example of the paused operation of FIG. 15 represents the advantage of a modular instruction structure that performs concurrent operations, and each of the concurrent operations can be paused and resumed to maximize utilization of the cores and channels.
The examples of sequences and operations in Figures 11-15 relies on the CSI and DSI strobe signals to provide information about the command packet or the read data packet. Since the command packet is variable in size and there is no header information for indicating the bit length of the command packet, the CSI strobe signal functions as a header of the command packet provided in parallel with the serial command packet. The CSI signal is active for the length of the instruction packet and is used by the memory device to latch the instruction packet data appearing on the Dn input port into the appropriate register. The DSI signal is active for the length of the expected read data packet that is known by the memory controller and moves in parallel with the read data packet. Thus, the active DSI signal serves as the header of the read data packet. Thus, the length of the command packet and the read data packet corresponds to the length of their respective CSI and DSI strobe signals.
Since both the read data packet and the instruction packet move along the same signal line connected between the Dn and Qn ports of adjacent memory devices, the presence of the CSI strobe with the data specifies the data as the command data packet, The presence of the DSI strobe having data designates the data as read data. Thus, the strobe signals also identify the type of data moving through the memory system. The memory controller tracks the DSI strobe that it issues so that the received read data packet and the expected data type match. For example, the read data packet may include status register information or data read from the memory array.
Considering the functional relationship of the CSI and DSI signals, a minimum separation time is inserted between any type of subsequent strobe signals. This ensures that all command packets and read data packets are defined separately and ensures that the appropriate type of data is latched by the memory device of the memory controller. There are four possible situations where separation is used. These are CSI-CSI separation (t CCS ), CSI-DSI separation (t CDS ), DSI-CSI separation (t DCS ), and DSI-DSI separation (t DDS ).
The CSI-CSI separation (t CCS ) is the minimum separation time during the clock period (t CK ) between successive command packets to the same or a different device. This isolation time allows the previous instruction to be cleared from the memory device, for example, by clearing the instruction register and resetting some instruction logic when preparing a new instruction. The DSI-DSI separation (t DDS ) is the minimum separation time during the clock period (t CK ) between consecutive read data packets to the same device. This isolation time causes the output buffer circuit to reset when it prepares the next data to be output. The DSI-CSI separation (t DCS ) is the minimum separation time during the clock period (t CK ) between the read data packet and the subsequent command packet to the same or a different device. The CSI-DSI separation (t CDS ) is the minimum separation time during the clock period (t CK ) between the command packet and the read data packet to the same device. These two isolation times ensure that the appropriate data types are latched by the memory device, since they can appear continuously on the Dn input port of the memory device. Since the memory controller issues the CSI and DSI signals to inform the instruction packet or the data packet bit length, the instruction packets and the data packets themselves are guaranteed to be separated by the same minimum time as the strobe signals.
Examples of these separation times are annotated in Figures 11-14 and the minimum separation time can be one data latching edge of the clock, which may be part of a clock period depending on the data rate structure employed. For example, in a single data rate structure (SDR) where data is latched at the rising edge of the clock, the minimum separation time is one clock cycle or period. In a double data rate structure (DDR) where data is latched on both the rising and falling edges of the clock, the minimum separation time is 0.5 of the clock period. 11 to 15 are examples of simultaneous operation in a single memory device and do not clearly show the relationship of CSI-DSI isolation or DSI-CSI isolation. 16 is a sequence diagram showing the relationship between CSI-DSI and DSI-CSI separation.
16 is an example of a scenario in which the first memory device outputs its read data from its Qn output port and the second memory device receives the command packet after the read data is output from the first memory device. The two memory devices mentioned in this example can correspond, for example, to those shown in Figures 4 and 5. Signal traces for the DSI_1, CSI_1, DSO_1, CSO_1 and Qn_1 ports are shown for a first memory device, where the appended "_1" represents the port of the first memory device. The signal traces for DSI_2, CSI_2, and Dn_2 are shown for the second memory device, where the appended "_2" represents the port of the second memory device. It is assumed that the first memory device is already receiving one or more instruction packets for reading data. As a result, DSI_1 receives the
The memory controller now issues a
Memory devices, particularly non-volatile memory devices, in the memory system described above have the advantage of being able to retain stored data in the absence of power supplied to the memory device. However, the transition between full power operation and no power or transition between power saving levels can jeopardize the integrity of the stored data.
17A shows a flash memory device to which embodiments of the present invention can be applied. 17A, the
For proper operation of the
The register of the
18 shows a sequence of a voltage source ( Vcc ), an active low logic level reset signal (RST #), and an active low logic level chip enable signal CE # during power up and power down operations in a
The loss of data integrity due to unintentional program / erase operations during power transfer requires a gradual increase in speed and a reduction in size as well as a demand for lower power consumption may result in the flash memory device having a lower V CC voltage level It is exacerbated by the current generation of flash devices that need to be routinely operated. The lower operating V CC level expands the problem associated with the pseudo-information stored in the various registers of the flash device, which adversely affects data reliability.
A method of protecting data during a power transition such as a power rise and a power fall operation in a nonvolatile memory device will be described. Before any power transitions are asserted, a reset signal is asserted to disable the function of the memory device. The reset signal is maintained during the preset time, during which the device voltage is expected to stabilize. During this time, all internal registers, such as the device's instruction register, are set to default values to prevent data loss due to the pseudo program / erase instruction being executed by the device.
FIG. 19 is a timing chart showing a voltage source ( Vcc ), an active low logic level reset signal (RST #), and an active low logic level chip enable signal ( Vcc ) during power up and power down operations in a nonvolatile memory device according to an embodiment of the present invention. (CE #). As previously described, the V CC voltage transitions from a low GND or V SS voltage level to a high V CC voltage level at time t ON . Alternatively, the V CC voltage level may transition from the low power mode to the V CC voltage level. The V CC voltage level may rise at timely and at time t ST , exceeding the stable voltage level V ST , at which time the
Eventually, the controller will deassert RTS # after time t RST as shown in FIG. After this time, the power is stabilized, and then the device components can prepare or initialize themselves for operation. Optionally, the controller deasserts the CE # signal at time t ON by driving the CE # signal to an inactive high logic level while the device is in the reset state. Since V CC rises to its maximum voltage level, CE # follows V CC rise. The CE # signal can be asserted at time t CEOff to bring the device into normal operation. CEOff time t occurs after the RST # signal is at least a time period t 2 has passed since the drive to the deasserted, or inactive high logic level. When the device enters the normal running state, the initializing operation can be executed at both the device level and the system level. Careful maintenance of the device in a reset state for a predetermined amount of time during a power transition operation prevents pseudo information from being stored or latched in the various registers of the device. The device is thereby protected against improper and careless programming or erasure of data, ensuring data integrity during power transfer.
A similar procedure to ensure data protection can be achieved by asserting RST # at a predefined time before t OFF when V CC is turned off and driven to a low GND or V SS voltage level or by asserting RST # Lt; / RTI > during the power down operation.
A flowchart illustrating a method of protecting data during power transfer in a nonvolatile memory device according to an embodiment of the present invention is shown in FIG. A memory controller that controls non-volatile memory devices, such as flash memory devices, keeps RST # low prior to any power transition to place the device in a reset state (step 1100). During this time, the internal registers of the device are set to the default or reset state. The controller then transitions power (step 1102) and waits for a predetermined amount of time to stabilize the device's internal voltage (step 1104). The standby time corresponds to t RST shown in Fig. 19, and at least the time required for the V CC voltage level to reach the stable V ST voltage level (the time from t ON to t ST ) + at least the V CC level becomes stable voltage level It is time t 1 after reaching V ST . The time t 1 may be determined based on device characteristics such as operating voltage and process technology. For example, the total time that RST # is kept low, that is, t RST , may be 10 s or more. During this time, various components of the device are stabilized, the clock becomes operational, and the frequency and phase become stable.
After the elapse of the time t RST , the controller asserts the RST # high signal when the device is expected to be in the "ready " state (step 1106). 19, the controller asserts the CE # signal at time t ON while the device is in the reset state and sends the signal to the disabled state after RST # is deasserted so that the memory device is in the reset state . The CE # signal is deasserted at time t CEOff to bring the device into normal operation. The time t CEOff is after at least t 2 has elapsed since the RST # signal was asserted. When the device enters a normal running state, an initializing operation may be performed at both device level and system level (step 1108). Similar to time t 1 , time t 2 can be determined based on device characteristics and changes from one memory system to another. For example, t 2 may be greater than or equal to 100 s.
Figure 21 illustrates the steps followed by the device during power transfer to ensure data protection in accordance with one embodiment of the present invention. The non-volatile memory device receives the RST # low signal before any power transition from the memory controller that controls the device (step 1200). The device then receives power from the controller to activate the device component (step 1202). This received power may be from VSS voltage or from a low power mode voltage level to a full VCC operating voltage level. Due to the low RST # signal, the device is placed in a reset state. During this time, the internal registers of the device and some finite state machine are set to the default or reset state and are maintained (step 1204). Thereafter, the controller waits for a predetermined time to stabilize the internal voltage of the device before RST # is asserted high. After elapse of time t RST , the controller asserts the RST # high signal when the device is expected to be in the "ready " state. The device receives the RST # high signal and places the device in the "ready" state (step S1206). The controller asserts the CE # signal at time t CEOff to bring the device into normal operation. As previously described, if the device enters a normal running state, an initialization operation may be performed at the device level (step 1208).
A method of data protection during power transition in the
By ensuring that the device is in a reset state for a predetermined amount of time during a power transition operation, it prevents pseudo information from being stored or latched in various registers of the device. The device is thereby protected against improper programming or erasure of data, ensuring data integrity during power transfer.
In the foregoing description, for purposes of explanation, numerous specific details are set forth in order to provide an understanding of embodiments of the invention. However, it will be apparent to those skilled in the art that these specific details are not required to practice the invention. In other instances, well-known electrical configurations and circuits are shown in block diagram form in order to facilitate clarity of the invention. For example, no specific details are provided as to whether embodiments of the invention described herein are implemented as software routines, hardware circuits, firmware, or combinations thereof.
Embodiments of the invention may be practiced with other types of computer-readable media, such as computer readable media (also referred to as computer usable media having computer readable program code embodied in a computer readable medium, Products. The machine-readable medium may be any suitable type of storage medium, including magnetic, optical, or electrical storage media including diskettes, compact disk read only memory (CD-ROM), memory devices (volatile or nonvolatile) Lt; / RTI > The machine-readable medium may include various sets of instructions, code sequences, configuration information, or other data that cause the processor to perform the steps of the method in accordance with an embodiment of the invention. Those skilled in the art will appreciate that other instructions and operations necessary to realize the described invention may be stored in a machine-readable medium. Software running from a machine-readable medium may interface with the circuitry to execute the tasks described.
The embodiments of the present invention described above are intended to be examples only. Modifications, alterations, and modifications may be made by those skilled in the art to the particular embodiments, without departing from the scope of the invention as set forth solely by the claims appended hereto.
Claims (55)
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