200826175 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體晶圓，尤指一種能夠有效 避免晶圓切割造成介層剝離(delamination)現象的半導體晶 【先前技術】 隨著半導體製程技術的不斷提昇、以及積體電路晶片 尺寸的微小化，金屬内連線間往往也形成許多不必要的寄 生電容(parasite capacitor)。由於電子要先充滿寄生電容之 後才能進行傳遞’因此使得訊號的傳遞延遲’造成所謂的 電阻電容時間延遲效應（RC time delay effects)，而且電阻一 電容時間延遲效應也成為進一步提升積體電路元件之速度 與效能的瓶頸。為了要提升積體電路元件的速度與效能， 目前大多是利用降低金屬内連線的線路電阻或者是降低介 電層的介電常數等方式來減少電阻-電容時間延遲效應的 影響。在此需求之下，電阻率較低的銅金屬漸漸取代電阻 率較高的鋁金屬成為金屬内連結線路的材料，而低介電常 數的介電材料也逐漸取代氟矽玻璃（fluorinated silicate glass，FSG)、填矽玻璃（Phosphosilicate glass，PSG)或者未摻 雜矽玻璃（undoped silicate glass，USG)等氧化矽介電材料。 然而，低介電常數材料和銅金屬之介面卻格外容易產 6 200826175 生剝落(peeling)或是介層剝離等現象。因為在半導體晶圓 之積體電路製作完成後，通常封裝廠都會以研磨輪或切割 刀來切割半導體晶圓以進行後續之封裝製程，但機械式的 切割難免會在半導體晶圓中產生機械内應力（intermal stress) ’造成裂縫(crack)，尤其是當切割道(scribe line)中包 含有低介電常數材料和銅金屬時，便特別容易引發低介電 常數材料層產生剝落或是介層剝離。因為在進行切割步驟 時’研磨輪或切割刀會從晶圓表面向下施加切割應力，而 當切割應力壓迫至較大面積之金屬結構時，整個金屬結構 便會擠壓週邊之低介電常數材料層，擠壓的結果就可能造 成低介電常數材料層剝落現象，這是由於銅金屬材料之性 負堅硬’相較於晶圓之其他材料層而言較難切割，而低介 電係數材料層卻材質鬆軟或呈多孔性結構，且與其他材料 層的附著力不佳。當剝落現象由切割道延伸至各晶粒區域 (die area)中之驅動電路時，這些潛在的問題往往會傷害到 隶終產品的可靠度。 儘管可能存在上述缺點，但切割道中卻難以避免地會 包含有金屬墊等較大面積之金屬材料。因為在半導體製程 中’為維持產品品質的穩定，就必須針對所生產之半導體 晶圓持續進行線上測試。目前業界大多是採用晶圓可接受 度測試(wafer acceptance testing，WAT)，其係於兩晶粒之週 邊區域（periphery area)提供複數個測試鍵〇est匕幻結構，用 200826175 :t別5每道半導體製程之各項缺陷 。亦即在進行各式 製程的同時，倕掂 妹用相同的步驟於晶圓之切割道中同步製 作一測試用元件，才 & $曰、，采模擬相同製程，然後再利用金屬探針 里〆則測試鍵的各項參數作為檢視製程是否正常 # M 、有政控制產品品質。上述測試鍵結構即包含 有金屬墊且位於切 ^道中’其他位於切割道中之金屬墊結 ;^有電II測4結構(test㈣、特徵尺寸(如⑽di_si㈣ 、一牛、及元件對準標記(alignmentmark)等製程測試 結構或是識別標識(logo)。 清參閱第1圖以及第2圖。第1圖為傳統半導體晶圓 的之上視示意圖’第2圖則是第1圖所示之半導體晶圓切 告1J後之側視示意圖。如第1圖所示，半導體晶圓1〇包括有 複數個呈陣列排列之晶粒區域12、複數個本質上相互平行 的第一切割道區域（scribe Hne area)i4以及複數個本質上相 互平行的第二切割道區域，其中第一切割道區域14與 第一切割道區域16之間大致上是相互垂直分佈，用以隔開 各晶粒區域12。另外，在目前之半導體晶圓10表面大多 包含有低介電常數材料層18構成之保護層（passivation layer)或金屬内介電材料層（inter_metai dielectric layer，IMD layer)。於第一切割道區域14或第二切割道區域16中設有 至少一金屬測試結構20，金屬測試結構20可為任意之電 性測試結構、特徵尺寸等之量測元件以及元件對準標記、 200826175 晶圓可靠度測試墊等製程測試結構。 後，=二，圓10上之_路製作完成之 °仃、衣製耘之時，研磨輪或切割刀會沿著第一 =告’J道區域14與第二切割道區域16進行切割，用以將半 V體日曰圓1G *剎為多個獨立之晶粒區域。—般而今， 第-切割道區域14與第二切割道區域16之寬度；隨； 導體晶圓尺寸、㈣方式、積體電路的軸等因素而定， 約介於數十微米（micr〇meter)至數百微米之間。 如第2圖所示，半導體晶圓10經域後，剝落或是介 層剝離等現象特別容易產生在最頂層之低介電常數材料層 =與下方之其他㈣層的介面，尤其是糊應力壓迫至切 剔道區域14巾較大面積之金屬結構時，整個金屬結構便會 h壓週邊之低介電常數材料層，進而造成低介電常數材料 層發生剝落、介層_等現象，而且這種絲非常容易沿 著垂直於切割路徑的行經方向進行傳遞，使低介電常數材 料層18>之剝落範圍可能觸及晶粒區域12中之金屬内連線 層而破壞晶粒内之積體電路運作。 【發明内容】 、康”本务明之主要目的在於提供一種半導體晶圓， 以解決習知技術無法克服之難題，進而防止半導體晶圓切 200826175 割引起晶粒損傷。 根據本發明之中嗜衰 辦曰P! ^ ^專心圍’本發明係提供-種半導 -曰曰®，包括有複數個晶粒 及至少一第-切幻、至）一弟一切割道區域 宝八/刀副道區域圍繞在各晶粒區域周圍、至少一 弟-=構與至少一第二金屬結構分別設置於第一與第 二二：：，而且第一金屬結構具有至少-平行於該 少-平二；Hr狹縫或開口’第二金屬結構具有至 ;一刀割道區域之第二狹縫或開口。 根據申請專利範圍，本發明另提供一種製作金屬結構 之，法°心’提供—半導體晶圓，半導體晶圓定義有一 切剔道區域，且切割道區域具有至少—第—介電層。接著， 於切剔道區域中之第—介電層中形成―第—金屬層，且第 一金屬層具有至少一平行於切割道區域之狹縫。之後，於 切^道區域中形成—第二介電層，且第二介電層具有複數 個平仃於切割道區域之狹長介層洞（viah〇le)，用以暴露出 部分之第一金屬層。最後，於第二介電層表面形成一第二 金屬層以及複數個介層條填充於狹長介層洞中，且第二金 屬層係藉由介層條電連接第一金屬層。 由於在本發明半導體晶圓之金屬結構中形成有狹縫結 構或是複數個陣列排列之開口結構，因此可以避免機械式 200826175 的切割引發材料層剝落或是介層剝離的現象，進而有效保 護晶粒不被剝落現象損傷。 為了使貴審查委員能更近一步了解本發明之特徵及 技術内容，請參閱以下有關本發明之詳細說明與附圖。然 而所附圖式僅供參考與輔助說明用，並非用來對本發明加 以限制者。 【實施方式】 請參考第3圖至第7圖，第3圖至第6圖為本發明之一 較佳實施例形成半導體晶圓之方法示意圖，而第7圖是第 6圖所示之半導體晶圓30沿著7-7’切線之剖面示意圖。如 第3圖所示，本發明之半導體晶圓30，其上包括有至少一 低介電常數之第一介電層38a、複數個晶粒區域32、複數 個本質上相互平行的第一切割道區域34以及複數個本質 上相互平行的第二切割道區域36。其中，在每一晶粒區域 32中皆形成有一積體電路，其可包括有電晶體(transistor)、 電容(capacitor)、二極體(diode)、摻雜擴散區、記憶體陣列 或者金屬内連線等之各式電子元件與導線電路。第一切割 道區域34與第二切割道區域36之間大致上是相互垂直分 佈，並構成一網狀之切割道區域，用以隔開各晶粒區域32。 接著如第4圖所示，進行一金屬製程，以於各晶粒區域 200826175 割道區域、=二取上層之金屬連線(未顯示），並於第-切 別形;H、」、第二切割道區域36之第一介電層38a中分 作μ矩形之第一金屬層40以及第—金屬層43， 二=:、特徵尺寸量測元件、元件對準標記、晶圓 可結合銅製程，而於第一切二。 層4。鑲嵌於其中，且第：二:34中形成♦金屬 弟一金屬層40上具有至少一狹缝44 :餅第一切割道區域34，並於第二切割道區域36中形 =弟—金屬層43鑲嵌於其中，且第—金屬層43上具有 至>、-狹縫45平行於第二切割道區域％。其中，狹縫料、 々—5之形狀、長度與寬度皆可依據第一金屬層仙與第一、 第刀口|J區域34、36之尺寸設計需求而調整。 如第5圖所示，之後形成至少—低介電常數之第二介電 層38b I盍在晶粒區域32、第一切割道區域34與第二切 割道區域36上。然後進行—介層洞(via h*则製程，以 於第-切割道區域34、第二切割道區域36内之第二介電 層38b中分別形成複數個平行於第一切割道區域μ、第二 切副道區域36之狹長介層洞3卜33，並相對應暴露出部 分之第一金屬層40、43。 接著如第6圖所示，利用一金屬沉積製程，以於第二介 電層38b表面形成一金屬層（未顯示），並分別填滿第一切 12 200826175 割道區域34、第二切割道區域36之各狹長介層洞3卜幻， 形成複數個介層條46a。然後再對此金屬層進行一蝕刻掣 程，以於第一切割道區域34、第二切割道區域％内之第 二介電層38b表面分別形成一第二金屬層4讣以及一第一 金屬層47b。然後，再於整個半導體晶圓3〇表面形成一保 護層48,並利用一蝕刻製程來圖案化保護層48， = 用Μ暴露 出第一切割道區域34與第二切割道區域36上部分之第一 金屬層46b、47b，完成本發明之金屬結構製程。其中# 一介電層38a、第二介電層38b與保護層48之材質可包= 有敦石夕玻璃、破石夕玻璃、未摻雜矽玻璃、氫秒酸_類 (hydrogen silseqUOXiane，HSQ)或者曱基矽酸鹽類㈦灿y silSeqU〇xiane，MSQ)等等之各式介電材料， / J乐一金屬； 40、43、介層條46a與第二金屬層46b、47b則可為鈦在曰 鎮、铭、銅、氮化鈦、氮化组等金屬或上述合全之电人纽、 此外’第4圖至第6圖所示之各金屬沉積、餘刻等势厂 亦會同時於各晶粒區域32中形成所需之最上層之金王’ 線、金屬銲塾(bondingpad)等結構(未顯 技藝者或通常知識者所妙，在此不多加料I知該項 ^參考以圖，第8圖獅為切趙晶㈣部 之上視不⑽。如帛8圖所示，半導體晶圓3 ^ 個晶粒區域32、複數個第—切 財魏 割道區域36、一保護層48以及ι4::數個第二切 罘一金屬層46b，而第二 13 200826175 金屬層46b下方則電連接有介層條46a以及第一金屬層 . 40 ’且第一金屬層40包含有至少一平行於第一切割道區域 ^ 34之狹縫44，如第7圖所示。此外，晶圓切割方向42係 為在第一切割道區域34上所預定之機械切刀的切割方 向，且晶圓切割方向42之配置大致上會平行於第一切割道 區域34之方向。 如前所述，當封裝廠採用機械切刀沿著切割道區域之方 ^ 向碾切晶圓時，會造成晶圓承受相當大的應力。由於金屬 材料屬於南機械強度之材料，因此要切割金屬材料的比切 割低機械強度之材料來得困難。倘若機械切刀碾切到一完 整無開口之第一金屬層，機械切刀需提供較大之作用力， 相對地此處則需承受較大的應力’故在晶圓切割時或者晶 圓切割後，通常會發現在低介電常數介電材料之間形成剝 落或是介層剝離等現象，而影響到積體電路晶粒的可靠 度。反觀，本發明設置於切割道區域中之金屬結構均具有 至少一平行於切割道區域之狹縫，因此當機械切刀切割之 位置沿著晶圓切割方向42而經過第一金屬層40之狹縫 44，會使所需破壞之金屬材料的面積減少，而可以有效減 少低介電常數介電材料與其他材料層之間形成剝落或是介 層剝離等現象的機率。此外，由於材料層中之斷裂端點、 拐點、分枝點等部位容易出現局部應力集中的現象。因此 • 本發明便係於切割道區域中之金屬結構均設置有至少一平 14 200826175 行於切割道區域之狹縫，以使得在進行切割製程時，若材 . 料層中發生有局部應力集中的現象時，在應力集中區域内 之應力值會比材料層平均受到的應力值大的多，使得在材 料内部之平均應力尚未達到材料之斷裂強度值前，應力集 中的部分，亦即在狹縫處之應力便已達到其斷裂強度值， 而可有利於切割製程的進行，減少低介電常數介電材料與 其他材料層之間形成剝落或介層剝離等現象。例如，當機 械切刀沿著晶圓切割方向42碾切至第一金屬層40時，第 一金屬層40之狹縫44的端點即可能出現局部應力集中的 現象，使切割應力自第一金屬層40與第一、第二介電層 38a、38b之外圍介面位置分散至第一金屬層40之狹縫44 位置，進而讓第一金屬層40之切割步驟較為容易進行。此 外，第一金屬層40、43之各狹縫44、45更可作為裂縫阻 擋結構(crack stress stopper)，用以阻擋裂縫由切割道延伸 至各晶粒區域中之驅動電路。 請參考第9圖與第10圖。第9圖為本發明之另一較佳 實施例半導體晶圓的部分切割道之上視示意圖，第10圖則 是第9圖所示之半導體晶圓沿著切線9-9’之剖面示意圖。 如第9圖與第10圖所示，半導體晶圓50包括有複數個晶 粒區域52(為求清楚明瞭，圖中僅示二個晶粒區域52)、至 少一切割道區域54、至少一金屬結構60位於切割道區域 • 54之中，以及至少一保護層58覆蓋於金屬結構60與切割 15 200826175 道區域54之上，其中在每一晶粒區域52中包括有至少_ 電路元件，例如電晶體、電容、二極體、摻雜擴散區、記 憶體陣列或者金屬内連線等等。金屬結構60可為鈦、鈕、 鎢、鋁、銅、氮化鈦、氮化鈕等金屬或上述合金之組合， 用以作為電性測試結構、特徵尺寸等之量測元件以及元件 對準標記、晶圓可靠度測試墊等製程測試結構。特別注意 的是，為了避免晶圓切割時所產生的應力破壞，此較佳實 施例之金屬結構60包含有複數個陣列排列之矩形開口 56，例如第9圖中所示之九個開口 56。開口 56之數量、 形狀、長度與寬度皆可依據金屬結構60與切割區域54之 設計需求而調整，不受本較佳實施例所侷限。 於本較佳實施例中，切割道區域54上之金屬結構60具 有：數個陣列排列之開口 56,宏觀上，機械切刀所需破壞 ’’屬材料的面積可以減少，進而降低低介電常數介電材 料與其他材料層之間形成剝落或是介層剝離等現象的機 外’當機械切刀礙切至金屬結構60時，金屬結構 割道延伸1至各56日I作為裂縫阻擔結構’用以阻擔裂縫由切 割步驟較為=域中之駆動電路’使金屬結構-之切 上述圖示係用以說明本發 偈限本發明之結構 ^式’亚非用以 寺别/主思的是’本發明金屬結構不單 200826175 可如韵述之说明设置於半導體晶圓表面，更可設置於切巧 Λ 道中之各個金屬内連線層間，用以檢測半導體晶圓之生產 - 過程中之各金屬内連線層製程的穩定度。此外，本發明之 金屬結構亦可僅設置於同一金屬内連線層之單一方向之切 割道區域中，例如只設置於X方向上的切割道區域内，或 只設置於Υ方向上的切割道區域内。 本發明半導體晶圓之金屬結構可具有狹縫結構或是複 數個陣列排列之開口結構’除了上述二實施例之外，亦可 採用其他樣式之金屬結構作為實施例。舉例來說，第u圖 至第|4圖即為本發明之各式金屬結構的示意圖。第^圖回 所示係為-包含有二個狹縫之金屬結構％;第η圖所干 料-包含有五個狹縫之金屬結構8G;第13圖所示係為 一包含有四個呈陣列排列之開口的金屬結構9〇 ;第Μ圖 :示係為-包含有十二個呈陣列排列之開口的金屬結構 ::更此外，為了更進一步提昇本發明=護 17 200826175 如第15圖所示，第15圖繪示的是一具有不連續邊緣 之金屬結構110。金屬結構11〇係為一矩形結構，其邊緣部 分（圖中虛線116a以内之區域與虛線116b以外之區域二者 所父集部分）具有複數個交錯狹縫112與複數個邊界狹縫 114。交錯狹縫112大致上係垂直於金屬結構n〇之四邊而 設置於金屬結構110中，而邊界狹縫114則自金屬結構11〇 之四個邊界向内延伸，並與交錯狹縫112交錯排列。由於 父錯狹縫112與邊界狹縫114成交錯排列，故可使金屬結 構110之邊緣部分成為不連續結構116。 第16圖繪示的是一具有開口 128與不連續邊緣之金屬 結構120。如第16圖所示，金屬結構12〇之邊緣部分不但 具有第15圖所示之不連續結構116，而且金屬結構12〇之 中央部分具有複數個開口 128呈陣列排列。第17圖所示係 為一具有中央狹縫138與不連續邊緣之金屬結構13()，其 中金屬結構130之邊緣部分除了具有第15圖所示之不連續 結構116，且金屬結構13〇之中央部分具有複數個中央狹 縫138平行於切割道而排列。 第18圖所示係為一具有中央狹縫148與不連續邊緣之 金屬結構140。如第18圖所示，金屬結構14〇之中央部分 具有複數個中央狹縫148，且其邊緣部分具有複數個邊界7 200826175 狹縫144。邊界狹縫144係自金屬結構140之四個邊界向 内延伸，而中央狹縫148則平行於切割道而排列。尤其注 意的是，各中央狹缝148之二端延伸至二對邊之邊界狹縫 144之間，而使中央狹縫148與二對邊之邊界狹縫144呈 交錯排列。 第19圖所示係為一具有中央狹縫158與不連續邊緣之 金屬結構150。如第19圖所示，金屬結構150具有複數個 中央狹縫158，且其邊緣部分具有複數個交錯狹縫152與 複數個邊界狹縫154。邊界狹縫154係自金屬結構150之 四個邊界向内延伸，而中央狹縫158則平行於切割道而排 列。尤其注意的是，各中央狹縫158之二端延伸至二對邊 之邊界狹縫154之間，使中央狹縫158與二對邊之邊界狹 縫154呈交錯排列。此外，交錯狹縫152係設置於中央狹 縫158二側之金屬結構150的邊緣部份中，與其所在位置 之邊界狹縫154呈交錯排列。 另外，為配合上述具有不連續邊緣之金屬結構的形 狀，金屬結構下方之金屬層或介層條亦可包含有對應於上 層金屬結構之鋸齒形狀、方波形狀或波浪形狀的邊緣。 由於本發明係於半導體晶圓之切割道區域中之金屬結 構均設置有至少一平行於切割道區域之狹縫、複數個陣列 19 200826175 靠 排列之開口衫連續邊緣，使得金屬結構成為不連續姓 構，因此能有效地減少低介電材料層與其他材料層之^ 成剝落或是介層_等聽賴率，進㈣護晶粒不被剝 洛專現象祕。另外，在進行切割製程時，本發明便可藉 由金屬結射的狹縫或開口作為裂縫阻擋結構，用以阻^ 裂縫由切割道延伸至各晶粒區域中之驅動電路，而且可使田 切割應力分散至金屬結構之狹縫朗口處，崎放2 的應力’進而避免裂縫延伸至晶粒區域傷害到產品的可刀 專_所：=:=發= 【圖式簡單說明】 第1圖為傳統半導體晶圓的之上視示意圖。 ^ ^為» !圖所示之半導_切割後之側視示意圖。 弟之圖t第6圖為本發明之—較佳實施例形成半導體晶圓 之方法示意圖。 不 弟7圖是第6圖所示之半導體晶圓沿著7_7,切線之 意圖。 第 第 8圖所示為半導體晶圓的部分切割道之上視示意圖。 9圖為本發明之另一較佳實施例半導體晶圓的部分切割 道之上視不意圖。 20 200826175 弟_則是第9圖所示之半導體晶圓沿著切線9_9,之剖面 示意圖。 f U圖至f 14圖係為本發明之各式金屬結構的示意圖。 々15圖至第19圖係為本發明各式具有不連續邊緣之金屬 結構的示意圖。 【主要元件符號說明】 10 半導體晶圓 14 第一切割道區域 18 低介電常數材料層 30 半導體晶圓 32 晶粒區域 34 第一切割道區域 38a 第一介電層 40 第一金屬層 43 第一金屬層 45 狹縫 46b 第二金屬層 48 保護層 52 晶粒區域 56 開口 60 金屬結構 80 金屬結構 12 晶粒區域 16 第二切割道區域 20金屬測試結構 31 狹長介層洞 33 狹長介層洞 36 弟—切割道區域 38b第二介電層 42晶圓切割方向 44 狹縫 46a介層條 47b第二金屬層 50半導體晶圓 54 切割道區域 58 保護層 70金屬結構 90金屬結構 21 200826175 100金屬結構 112 交錯狹縫 116不連續結構 116b虛線 128 開口 138 中央狹縫 144邊界狹縫 150金屬結構 154邊界狹縫 110金屬結構 114邊界狹縫 116a虛線 120金屬結構 130金屬結構 140金屬結構 148中央狹縫 152交錯狹縫 158中央狹縫 22200826175 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor wafer, and more particularly to a semiconductor crystal capable of effectively preventing delamination caused by wafer dicing. [Prior Art] With Semiconductor With the continuous improvement of process technology and the miniaturization of the size of integrated circuit chips, many unnecessary parasite capacitors are often formed between metal interconnects. Since the electrons are first filled with parasitic capacitances before they can be transmitted 'so the delay of signal transmission' causes so-called RC time delay effects, and the resistance-capacitance time delay effect is further enhanced by the integrated circuit components. The bottleneck of speed and performance. In order to improve the speed and performance of integrated circuit components, most of the current methods are to reduce the resistance of the resistor-capacitor time delay by reducing the line resistance of the metal interconnect or reducing the dielectric constant of the dielectric layer. Under this demand, copper metal with lower resistivity gradually replaces the aluminum material with higher resistivity as the material of the metal interconnecting line, and the dielectric material with low dielectric constant gradually replaces the fluorinated silicate glass. FSG), Phosphosilicate glass (PSG) or yttrium oxide dielectric material such as undoped silicate glass (USG). However, the interface between the low dielectric constant material and the copper metal is particularly prone to production. 200826175 Peeling or interpenetration. Because after the integrated circuit of the semiconductor wafer is completed, the packaging factory usually cuts the semiconductor wafer with a grinding wheel or a dicing blade for subsequent packaging process, but the mechanical cutting will inevitably produce a mechanical inside the semiconductor wafer. Intermal stress 'cracking, especially when the scribe line contains a low dielectric constant material and copper metal, it is particularly prone to cause spalling of the low dielectric constant material layer or interlayer peeling. . Because the grinding wheel or cutter will apply cutting stress downward from the wafer surface during the cutting step, and when the cutting stress is pressed to a large area of the metal structure, the entire metal structure will squeeze the low dielectric constant of the periphery. The material layer, the result of extrusion may cause the peeling of the low dielectric constant material layer, because the negative and hard nature of the copper metal material is more difficult to cut than the other material layers of the wafer, and the low dielectric constant The material layer is soft or porous and has poor adhesion to other material layers. These potential problems often jeopardize the reliability of the end-of-life product when the spalling phenomenon extends from the scribe line to the drive circuitry in each die area. Although the above disadvantages may exist, it is difficult to avoid a large area of metal material such as a metal pad in the dicing street. Because in the semiconductor manufacturing process, in order to maintain the stability of product quality, it is necessary to continue online testing for the semiconductor wafers produced. At present, most of the industry adopts wafer acceptance testing (WAT), which provides multiple test keys 〇 est 匕 结构 structure in the peripheral area of two dies, using 200826175 : t not 5 The defects of the semiconductor manufacturing process. That is, while performing various processes, the sisters use the same steps to simultaneously create a test component in the wafer scribe line, only & $曰,, simulate the same process, and then use the metal probe. Then test the parameters of the key as the inspection process is normal # M, the quality of the product is controlled by the government. The above test key structure comprises a metal pad and is located in the cutting path of the other metal pad in the cutting channel; ^ has an electric II test 4 structure (test (four), feature size (such as (10) di_si (four), a cow, and component alignment mark (alignmentmark) The process test structure or identification mark (logo). See Figure 1 and Figure 2. See Figure 1 for a top view of a conventional semiconductor wafer. Figure 2 is a semiconductor crystal shown in Figure 1. A schematic view of the side after 1J. As shown in FIG. 1, the semiconductor wafer 1 includes a plurality of die-arranged die regions 12 and a plurality of first dicing regions that are substantially parallel to each other (scribe Hne) And a plurality of second scribe line regions substantially parallel to each other, wherein the first scribe line region 14 and the first scribe lane region 16 are substantially perpendicular to each other to partition the respective die regions 12. In addition, the surface of the semiconductor wafer 10 currently contains a passivation layer or an inter-metai dielectric layer (IMD layer) composed of a low dielectric constant material layer 18. At least one metal test structure 20 is disposed in the track region 14 or the second scribe track region 16. The metal test structure 20 can be any electrical test structure, feature size, etc., and component alignment marks, and the 200826175 wafer is reliable. Test bench structure such as test pad. After the second, the round 10 on the road is completed, the grinding wheel or the cutting knife will follow the first = ' 'J road area 14 and the first The second cutting path region 16 is cut to brake the half V body sundial 1G* into a plurality of independent grain regions. Typically, the width of the first cutting channel region 14 and the second cutting channel region 16; Depending on the size of the conductor wafer, (4) mode, the axis of the integrated circuit, etc., it is between tens of micrometers (micrometers) to hundreds of micrometers. As shown in Fig. 2, the semiconductor wafer 10 is via the domain. Afterwards, peeling or interlayer peeling is particularly likely to occur at the topmost layer of low dielectric constant material = the interface with the other (four) layers below, especially the paste stress is pressed to the area of the cut-off area 14 When the structure is used, the entire metal structure will be pressed around the periphery. The dielectric constant material layer, which in turn causes the low dielectric constant material layer to peel off, the interlayer layer, etc., and the wire is very easy to transfer along the direction perpendicular to the cutting path, so that the low dielectric constant material layer 18 > The peeling range may touch the metal interconnect layer in the die region 12 to destroy the integrated circuit operation in the die. SUMMARY OF THE INVENTION The main purpose of the present invention is to provide a semiconductor wafer to solve the conventional problem. Technology can not overcome the problem, and thus prevent semiconductor wafer cutting 200826175 cutting caused by grain damage. According to the present invention, the invention is provided by the invention. The invention provides a semi-conductive-曰曰®, including a plurality of crystal grains and at least one first-cutting-to-cut one-to-one cutting line. The regional treasure/knife sub-channel region surrounds each of the grain regions, at least one of the second structure and the at least one second metal structure are respectively disposed on the first and second two::, and the first metal structure has at least-parallel The second metal structure has a second slit or opening in the region of the cutting path of the Hr slit or the opening. According to the scope of the patent application, the present invention further provides a method of fabricating a metal structure, wherein the semiconductor wafer defines a cut-out region, and the scribe region has at least a first-dielectric layer. Next, a "first" metal layer is formed in the first dielectric layer in the scribing track region, and the first metal layer has at least one slit parallel to the scribe line region. Thereafter, a second dielectric layer is formed in the cut region, and the second dielectric layer has a plurality of via holes (via) that are flat on the scribe line region to expose the first portion Metal layer. Finally, a second metal layer is formed on the surface of the second dielectric layer, and a plurality of via stripes are filled in the elongated via holes, and the second metal layer is electrically connected to the first metal layer by the via stripes. Since the slit structure or the plurality of arrayed opening structures are formed in the metal structure of the semiconductor wafer of the present invention, the peeling of the material layer or the peeling of the dielectric layer of the mechanical type 200826175 can be avoided, thereby effectively protecting the crystal. The grain is not damaged by peeling. In order to provide a more detailed understanding of the features and technical aspects of the present invention, the following detailed description of the invention and the accompanying drawings. The drawings are for illustrative purposes only and are not intended to limit the invention. [Embodiment] Please refer to FIG. 3 to FIG. 7 , FIG. 3 to FIG. 6 are schematic diagrams showing a method of forming a semiconductor wafer according to a preferred embodiment of the present invention, and FIG. 7 is a semiconductor diagram shown in FIG. A schematic cross-sectional view of the wafer 30 along a 7-7' tangent line. As shown in FIG. 3, the semiconductor wafer 30 of the present invention includes at least one low dielectric constant first dielectric layer 38a, a plurality of die regions 32, and a plurality of first cuts substantially parallel to each other. The track area 34 and a plurality of second cut track areas 36 that are substantially parallel to each other. Wherein, an integrated circuit is formed in each of the die regions 32, which may include a transistor, a capacitor, a diode, a doped diffusion region, a memory array or a metal. Connect various electronic components and wire circuits. The first scribe line region 34 and the second scribe line region 36 are substantially perpendicular to each other and form a meshed scribe line region for spacing the die regions 32. Then, as shown in FIG. 4, a metal process is performed to cut the region of each of the die regions 200826175, and the metal wires of the upper layer (not shown) are removed, and are in the first-cut shape; H, ", The first dielectric layer 38a of the second scribe region 36 is divided into a first metal layer 40 and a first metal layer 43 of a μ-shaped rectangle, and two:: a feature size measuring component, a component alignment mark, and a wafer bondable copper Cheng, and cut the second in the first. Layer 4. Inlaid therein, and formed in the second: 34: ♦ metal-metal layer 40 has at least one slit 44: the first scribe line region 34 of the cake, and in the second scribe line region 36, the shape of the metal layer 43 is embedded therein, and the first metal layer 43 has a >, the slit 45 is parallel to the second scribe line area %. The shape, length and width of the slit material and the crucible 5 can be adjusted according to the design requirements of the size of the first metal layer and the first and third cutting edges |J regions 34 and 36. As shown in Fig. 5, a second dielectric layer 38b, at least a low dielectric constant, is then formed over the die region 32, the first dicing region 34 and the second dicing region 36. Then, a via hole (via h* process) is formed in the second dielectric layer 38b in the first scribe line region 34 and the second dicing region 36, respectively, parallel to the first dicing region μ, The narrow intervening hole 3 of the second cut sub-channel region 36 is 33, and correspondingly exposes a portion of the first metal layer 40, 43. Next, as shown in Fig. 6, a metal deposition process is used for the second A metal layer (not shown) is formed on the surface of the electrical layer 38b, and fills each of the narrow via holes 3 of the first cut 12 200826175 cut region 34 and the second cut track region 36, respectively, to form a plurality of via strips 46a. Then, an etching process is performed on the metal layer to form a second metal layer 4 and a first surface respectively on the surface of the second dielectric layer 38b in the first dicing area 34 and the second dicing area %. Metal layer 47b. Then, a protective layer 48 is formed on the entire surface of the semiconductor wafer 3, and the protective layer 48 is patterned by an etching process, and the first dicing area 34 and the second dicing area are exposed by Μ The first metal layer 46b, 47b of the upper portion of 36 completes the gold of the present invention The structural process, wherein the material of a dielectric layer 38a, the second dielectric layer 38b and the protective layer 48 can be included: there are Dunshixi glass, broken stone glass, undoped bismuth glass, hydrogen ic acid (hydrogen) silseqUOXiane, HSQ) or bismuth phthalate (7) y y silSeqU 〇 xian, MSQ) and other various dielectric materials, / J Le metal; 40, 43, the layer strip 46a and the second metal layer 46b, 47b can be a metal such as titanium in the town, Ming, copper, titanium nitride, nitrided group or the like, or the metal deposition, residual, etc. shown in Figure 4 to Figure 6. At the same time, the potential plant will also form the required top-level Jinwang's wire, bonding pad and other structures in each grain area 32 (not known to the skilled person or the general knowledge, no more feeding I) Knowing that the reference to the figure is shown in Figure 8, the lion is cut on the top of the Zhaojing (four) part (10). As shown in Figure 8, the semiconductor wafer 3 ^ grain area 32, a plurality of the first - cut Cai Wei The track region 36, a protective layer 48 and ι4:: a plurality of second tangential metal layers 46b, and the second 13 200826175 metal layer 46b is electrically connected to the vias 46a and a metal layer 40' and the first metal layer 40 includes at least one slit 44 parallel to the first scribe region 34, as shown in Fig. 7. In addition, the wafer cutting direction 42 is at the first cutting The cutting direction of the predetermined mechanical cutter on the track area 34, and the arrangement of the wafer cutting direction 42 is substantially parallel to the direction of the first scribe line area 34. As previously mentioned, when the packaging factory employs a mechanical cutter along the direction When the scribe line area is rolled, the wafer is subjected to considerable stress. Since the metal material is a material of the south mechanical strength, it is difficult to cut the metal material than cutting the material having low mechanical strength. If the mechanical cutter is milled to a complete metal layer without a gap, the mechanical cutter needs to provide a large force, and relatively large stress is required here. Therefore, during wafer cutting or wafer cutting After that, it is generally found that peeling or interlayer peeling occurs between the low-k dielectric materials, which affects the reliability of the integrated circuit die. In contrast, the metal structures disposed in the scribe line region of the present invention each have at least one slit parallel to the scribe line region, such that the position at which the mechanical cutter is cut passes through the narrowness of the first metal layer 40 along the wafer cutting direction 42. The slit 44 reduces the area of the metal material to be destroyed, and can effectively reduce the probability of peeling or interlayer peeling between the low-k dielectric material and other material layers. In addition, local stress concentration is likely to occur due to fracture end points, inflection points, branch points, and the like in the material layer. Therefore, the metal structure in the scribe line region is provided with at least one slit 14 200826175 slit in the scribe line region, so that local stress concentration occurs in the material layer during the cutting process. In the case of a phenomenon, the stress value in the stress concentration region is much larger than the average stress value of the material layer, so that the stress concentration portion, that is, the slit, before the average stress inside the material has not reached the fracture strength value of the material The stress at the point has reached the value of the breaking strength, which can facilitate the cutting process and reduce the phenomenon of spalling or interlayer peeling between the low-k dielectric material and other material layers. For example, when the mechanical cutter is milled to the first metal layer 40 along the wafer cutting direction 42, the end of the slit 44 of the first metal layer 40 may have a local stress concentration phenomenon, so that the cutting stress is from the first The peripheral interface of the metal layer 40 and the first and second dielectric layers 38a, 38b is dispersed to the position of the slit 44 of the first metal layer 40, thereby facilitating the cutting step of the first metal layer 40. In addition, the slits 44, 45 of the first metal layers 40, 43 serve as crack stress stoppers for blocking the drive of the cracks from the scribe lines to the respective die regions. Please refer to Figure 9 and Figure 10. Figure 9 is a top plan view of a portion of a dicing street of a semiconductor wafer in accordance with another preferred embodiment of the present invention, and Figure 10 is a cross-sectional view of the semiconductor wafer shown in Figure 9 taken along a tangential line 9-9'. As shown in FIGS. 9 and 10, the semiconductor wafer 50 includes a plurality of die regions 52 (only two die regions 52 are shown for clarity), at least one scribe region 54 and at least one The metal structure 60 is located in the scribe line region 54 and at least one protective layer 58 overlies the metal structure 60 and the dicing 15 200826175 track region 54 wherein at least _ circuit components are included in each die region 52, such as Transistors, capacitors, diodes, doped diffusion regions, memory arrays or metal interconnects, etc. The metal structure 60 may be a metal such as titanium, a button, a tungsten, an aluminum, a copper, a titanium nitride, a nitride button or a combination thereof, and is used as a measuring component and an element alignment mark of an electrical test structure, a feature size, and the like. Process test structure such as wafer reliability test pad. It is particularly noted that in order to avoid stress cracking during wafer dicing, the metal structure 60 of the preferred embodiment includes a plurality of rectangular openings 56 arranged in an array, such as the nine openings 56 shown in FIG. The number, shape, length and width of the openings 56 can be adjusted depending on the design requirements of the metal structure 60 and the cutting area 54, and are not limited by the preferred embodiment. In the preferred embodiment, the metal structure 60 on the scribe line region 54 has a plurality of arrays of openings 56. Macroscopically, the mechanical cutter needs to be destroyed, and the area of the material can be reduced, thereby reducing the low dielectric. The external dielectric material forms a phenomenon of peeling or interlayer peeling between the other material layers. When the mechanical cutter is cut to the metal structure 60, the metal structure cuts the extension 1 to each 56 days as the crack resistance. The structure 'used to resist cracks by the cutting step = the turbulent circuit in the domain' to make the metal structure - the above diagram is used to illustrate the structure of the present invention. It is thought that the metal structure of the present invention can be set on the surface of the semiconductor wafer as described in the description of the rhyme, and can be disposed between the various metal interconnect layers in the cautious channel to detect the production of the semiconductor wafer - in the process The stability of each metal interconnect layer process. In addition, the metal structure of the present invention may be disposed only in the scribe line region of the single metal interconnect layer in a single direction, for example, only in the scribe line region in the X direction, or only in the Υ direction. within the area. The metal structure of the semiconductor wafer of the present invention may have a slit structure or a plurality of arrayed open structures. In addition to the above two embodiments, other types of metal structures may be employed as embodiments. For example, the figures u through -4 are schematic views of various metal structures of the present invention. The figure shown in the figure back is - the metal structure % containing two slits; the dry material of the nth figure - the metal structure 8G containing five slits; the figure 13 is one containing four a metal structure 9 开口 arranged in an array; a second figure: a metal structure comprising twelve openings arranged in an array: moreover, in order to further enhance the invention = 17 1726175 as the 15th As shown in the figure, Fig. 15 shows a metal structure 110 having discontinuous edges. The metal structure 11 is a rectangular structure having a plurality of interlaced slits 112 and a plurality of boundary slits 114 at an edge portion thereof (the portion of the area other than the dotted line 116a and the area other than the broken line 116b). The staggered slits 112 are disposed substantially perpendicular to the four sides of the metal structure n〇 and disposed in the metal structure 110, and the boundary slits 114 extend inwardly from the four boundaries of the metal structure 11〇 and are staggered with the staggered slits 112. . Since the parent-corrected slits 112 are staggered with the boundary slits 114, the edge portions of the metal structures 110 can be made into the discontinuous structure 116. Figure 16 illustrates a metal structure 120 having an opening 128 and a discontinuous edge. As shown in Fig. 16, the edge portion of the metal structure 12 has not only the discontinuous structure 116 shown in Fig. 15, but also the central portion of the metal structure 12 has a plurality of openings 128 arranged in an array. Figure 17 is a metal structure 13 () having a central slit 138 and a discontinuous edge, wherein the edge portion of the metal structure 130 has a discontinuous structure 116 as shown in Fig. 15, and the metal structure 13 The central portion has a plurality of central slits 138 aligned parallel to the cutting lane. Figure 18 shows a metal structure 140 having a central slit 148 and a discontinuous edge. As shown in Fig. 18, the central portion of the metal structure 14 has a plurality of central slits 148, and its edge portion has a plurality of boundaries 7 200826175 slits 144. The boundary slits 144 extend inwardly from the four boundaries of the metal structure 140, while the central slits 148 are aligned parallel to the scribe lines. It is particularly noted that the two ends of each central slit 148 extend between the boundary slits 144 of the two opposite sides such that the central slit 148 and the boundary slits 144 of the two opposite sides are staggered. Figure 19 shows a metal structure 150 having a central slit 158 and a discontinuous edge. As shown in Fig. 19, the metal structure 150 has a plurality of central slits 158, and an edge portion thereof has a plurality of staggered slits 152 and a plurality of boundary slits 154. The boundary slits 154 extend inwardly from the four boundaries of the metal structure 150, while the central slits 158 are aligned parallel to the scribe lines. It is particularly noted that the two ends of each central slit 158 extend between the boundary slits 154 of the two opposite sides such that the central slit 158 and the boundary slits 154 of the two opposite sides are staggered. Further, the staggered slits 152 are disposed in the edge portions of the metal structures 150 on both sides of the center slit 158, and are staggered in the slits 154 at the boundary between them. Further, in order to conform to the above-described shape of the metal structure having discontinuous edges, the metal layer or the via strip under the metal structure may also include edges corresponding to the zigzag shape, the square wave shape or the wave shape of the upper metal structure. Since the metal structure in the scribe line region of the semiconductor wafer is provided with at least one slit parallel to the scribe line region, the plurality of arrays 19 200826175 are arranged on the continuous edges of the open shirts, so that the metal structure becomes a discontinuous surname Therefore, it can effectively reduce the delamination of the low dielectric material layer and other material layers, or the gradation of the interlayer, and the (4) protective grain is not detached. In addition, in the cutting process, the present invention can use a slit or opening formed by metal as a crack blocking structure for blocking the driving circuit of the crack extending from the scribe line to each of the die regions, and The cutting stress is dispersed to the slit of the metal structure, and the stress of the strip 2 is further prevented. The crack is prevented from extending to the grain area and the product is damaged. _:=:= hair = [simple description of the figure] The figure shows a top view of a conventional semiconductor wafer. ^ ^ is a schematic view of the semi-guided _ after cutting. Figure 6 is a schematic view of a method of forming a semiconductor wafer in accordance with a preferred embodiment of the present invention. The figure 7 is the intention of the semiconductor wafer shown in Fig. 6 along 7_7, tangent. Figure 8 is a top plan view of a portion of a dicing street of a semiconductor wafer. 9 is a view of a portion of a dicing street of a semiconductor wafer in accordance with another preferred embodiment of the present invention. 20 200826175 Brother _ is a schematic view of the semiconductor wafer shown in Figure 9 along the tangential line 9_9. The f U to f 14 drawings are schematic views of various metal structures of the present invention. Figures 15 through 19 are schematic views of various metal structures having discontinuous edges of the present invention. [Major component symbol description] 10 semiconductor wafer 14 first scribe region 18 low dielectric constant material layer 30 semiconductor wafer 32 die region 34 first scribe region 38a first dielectric layer 40 first metal layer 43 a metal layer 45 slit 46b second metal layer 48 protective layer 52 grain region 56 opening 60 metal structure 80 metal structure 12 grain region 16 second scribe region 20 metal test structure 31 narrow via hole 33 narrow via hole 36-Cleaning track area 38b Second dielectric layer 42 Wafer cutting direction 44 Slit 46a Interlayer strip 47b Second metal layer 50 Semiconductor wafer 54 Cutting track area 58 Protective layer 70 Metal structure 90 Metal structure 21 200826175 100 Metal Structure 112 staggered slit 116 discontinuous structure 116b dashed line 128 opening 138 central slit 144 boundary slit 150 metal structure 154 boundary slit 110 metal structure 114 boundary slit 116a dashed line 120 metal structure 130 metal structure 140 metal structure 148 central slit 152 staggered slit 158 central slit 22