TW200741739A - Methods and systems for writing non-volatile memories for increased endurance - Google Patents

Methods and systems for writing non-volatile memories for increased endurance

Info

Publication number
TW200741739A
TW200741739A TW095149570A TW95149570A TW200741739A TW 200741739 A TW200741739 A TW 200741739A TW 095149570 A TW095149570 A TW 095149570A TW 95149570 A TW95149570 A TW 95149570A TW 200741739 A TW200741739 A TW 200741739A
Authority
TW
Taiwan
Prior art keywords
write
segment
field
segments
methods
Prior art date
Application number
TW095149570A
Other languages
Chinese (zh)
Other versions
TWI313467B (en
Inventor
Yosi Pinto
Geoffrey S Gongwer
Oren Honen
Original Assignee
Sandisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/320,916 external-priority patent/US20070150644A1/en
Priority claimed from US11/321,217 external-priority patent/US7245556B1/en
Application filed by Sandisk Corp filed Critical Sandisk Corp
Publication of TW200741739A publication Critical patent/TW200741739A/en
Application granted granted Critical
Publication of TWI313467B publication Critical patent/TWI313467B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation
    • H03K21/403—Arrangements for storing the counting state in case of power supply interruption

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

A memory system that incorporates methods of amplifying the lifetime of a counter made up of memory elements, such as EEPROM cells, having finite endurance. A relatively small memory made up of a number of individually accessible write segments, where, depending on the embodiment, each write segment is made up of a single memory cell or a small number of cells (e.g., a byte). A count is encoded so that it is distributed across a number of fields, each associated with one of the write segments, such that as the count is incremented only a single field (or, in the single bit embodiments, occasionally more than one field) is changed and that these changes are evenly distributed across the fields. The changed field is then written to the corresponding segment, while the other write segments are unchanged. Consequently, the number of rewrites to a given write segment is decreased, and the lifetime correspondingly increased, by a factor corresponding to the number of write segments used.
TW95149570A 2005-12-28 2006-12-28 Methods and systems for writing non-volatile memories for increased endurance TWI313467B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/320,916 US20070150644A1 (en) 2005-12-28 2005-12-28 System for writing non-volatile memories for increased endurance
US11/321,217 US7245556B1 (en) 2005-12-28 2005-12-28 Methods for writing non-volatile memories for increased endurance

Publications (2)

Publication Number Publication Date
TW200741739A true TW200741739A (en) 2007-11-01
TWI313467B TWI313467B (en) 2009-08-11

Family

ID=38218856

Family Applications (1)

Application Number Title Priority Date Filing Date
TW95149570A TWI313467B (en) 2005-12-28 2006-12-28 Methods and systems for writing non-volatile memories for increased endurance

Country Status (2)

Country Link
TW (1) TWI313467B (en)
WO (1) WO2007076492A2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI473253B (en) * 2010-04-07 2015-02-11 Macronix Int Co Ltd Nonvolatile memory array with continuous charge storage dielectric stack
TWI492225B (en) * 2008-04-01 2015-07-11 Samsung Electronics Co Ltd Memory system and wear leveling method thereof
TWI503827B (en) * 2008-11-27 2015-10-11 Samsung Electronics Co Ltd System-on-a-chip storing chip data and/or security data and method of processing chip data and/or security data for a device

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1465614B1 (en) 2002-01-11 2008-01-02 Matthias Rath A nutrient pharmaceutical formulation comprising polyphenols and use in treatment of cancer
US7573969B2 (en) * 2007-09-27 2009-08-11 Sandisk Il Ltd. Counter using shift for enhanced endurance
TWI497511B (en) 2012-11-08 2015-08-21 Ind Tech Res Inst Chip with embedded non-volatile memory and testing method therefor
JP2018065315A (en) * 2016-10-20 2018-04-26 富士ゼロックス株式会社 Image formation apparatus and program

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2180083A (en) * 1985-09-06 1987-03-18 Motorola Inc Non-volatile electronic counters
US5181231A (en) * 1990-11-30 1993-01-19 Texas Instruments, Incorporated Non-volatile counting method and apparatus
US6084935A (en) * 1998-08-13 2000-07-04 Microchip Technology Incorporated Binary counter and method for counting to extend lifetime of storage cells
US6249562B1 (en) * 1999-08-23 2001-06-19 Intel Corporation Method and system for implementing a digit counter optimized for flash memory
US7113432B2 (en) * 2000-09-14 2006-09-26 Sandisk Corporation Compressed event counting technique and application to a flash memory system
US6772276B2 (en) * 2002-01-04 2004-08-03 Intel Corporation Flash memory command abstraction
US6792065B2 (en) * 2003-01-21 2004-09-14 Atmel Corporation Method for counting beyond endurance limitations of non-volatile memories
US6794997B2 (en) * 2003-02-18 2004-09-21 Sun Microsystems, Inc. Extending non-volatile memory endurance using data encoding

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI492225B (en) * 2008-04-01 2015-07-11 Samsung Electronics Co Ltd Memory system and wear leveling method thereof
TWI503827B (en) * 2008-11-27 2015-10-11 Samsung Electronics Co Ltd System-on-a-chip storing chip data and/or security data and method of processing chip data and/or security data for a device
TWI473253B (en) * 2010-04-07 2015-02-11 Macronix Int Co Ltd Nonvolatile memory array with continuous charge storage dielectric stack

Also Published As

Publication number Publication date
TWI313467B (en) 2009-08-11
WO2007076492A3 (en) 2007-11-29
WO2007076492A2 (en) 2007-07-05

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees