TW200717729A - Lead frame - Google Patents

Lead frame

Info

Publication number
TW200717729A
TW200717729A TW095138819A TW95138819A TW200717729A TW 200717729 A TW200717729 A TW 200717729A TW 095138819 A TW095138819 A TW 095138819A TW 95138819 A TW95138819 A TW 95138819A TW 200717729 A TW200717729 A TW 200717729A
Authority
TW
Taiwan
Prior art keywords
plating
lead frame
layer
coated
underlayer
Prior art date
Application number
TW095138819A
Other languages
English (en)
Inventor
Seishi Oida
Takahiro Nakano
Yoshihito Miyahara
Takashi Yoshie
Harunobu Satou
Kouichi Kadosaki
Kazumitsu Seki
Original Assignee
Matsushita Electric Ind Co Ltd
Shinko Electric Ind Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd, Shinko Electric Ind Co filed Critical Matsushita Electric Ind Co Ltd
Publication of TW200717729A publication Critical patent/TW200717729A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85464Palladium (Pd) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • H05K3/3426Leaded components characterised by the leads

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
TW095138819A 2005-10-20 2006-10-20 Lead frame TW200717729A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005306379A JP4820616B2 (ja) 2005-10-20 2005-10-20 リードフレーム

Publications (1)

Publication Number Publication Date
TW200717729A true TW200717729A (en) 2007-05-01

Family

ID=37719312

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095138819A TW200717729A (en) 2005-10-20 2006-10-20 Lead frame

Country Status (5)

Country Link
US (1) US8283759B2 (zh)
EP (1) EP1777743A3 (zh)
JP (1) JP4820616B2 (zh)
CN (1) CN1953168B (zh)
TW (1) TW200717729A (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006032074B3 (de) * 2006-07-11 2007-12-27 Infineon Technologies Ag Bauelement und zugehöriger Anschlussdraht
JP5215305B2 (ja) 2007-07-06 2013-06-19 第一電子工業株式会社 電子部品の製造方法及び該方法により製造する電子部品
JP5762081B2 (ja) * 2011-03-29 2015-08-12 新光電気工業株式会社 リードフレーム及び半導体装置
CN105018995A (zh) * 2015-07-10 2015-11-04 陈圳浩 银饰品表面光亮五层电镀工艺

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0335608B1 (en) * 1988-03-28 1995-06-14 Texas Instruments Incorporated Lead frame with reduced corrosion
US5014113A (en) * 1989-12-27 1991-05-07 Motorola, Inc. Multiple layer lead frame
JP2543619B2 (ja) 1990-09-05 1996-10-16 新光電気工業株式会社 半導体装置用リ―ドフレ―ム
JPH04337657A (ja) 1991-05-14 1992-11-25 Hitachi Cable Ltd 半導体装置用リードフレーム
US5360991A (en) * 1993-07-29 1994-11-01 At&T Bell Laboratories Integrated circuit devices with solderable lead frame
US5650661A (en) * 1993-12-27 1997-07-22 National Semiconductor Corporation Protective coating combination for lead frames
US5436082A (en) * 1993-12-27 1995-07-25 National Semiconductor Corporation Protective coating combination for lead frames
JP3550875B2 (ja) 1996-05-14 2004-08-04 ソニー株式会社 リードフレームとこれを用いた半導体装置
JPH1074879A (ja) 1996-08-30 1998-03-17 Mitsui High Tec Inc 半導体装置用リードフレーム
KR100231828B1 (ko) * 1997-02-20 1999-12-01 유무성 다층 도금 리드프레임
US5994767A (en) * 1997-04-09 1999-11-30 Sitron Precision Co., Ltd. Leadframe for integrated circuit package and method of manufacturing the same
DE19850526C2 (de) * 1998-11-03 2002-11-28 Heraeus Gmbh W C Substrat mit metallischer Beschichtung und seine Verwendung
ES2171088T3 (es) * 1998-06-10 2002-08-16 Heraeus Gmbh W C Procedimiento para producir un sustrato exento de plomo.
US20030011048A1 (en) 1999-03-19 2003-01-16 Abbott Donald C. Semiconductor circuit assembly having a plated leadframe including gold selectively covering areas to be soldered
JP2001230360A (ja) 2000-02-18 2001-08-24 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2002076229A (ja) 2000-07-13 2002-03-15 Texas Instruments Inc 銀めっきを含む半導体のリードフレームおよびその製造方法
KR100371567B1 (ko) * 2000-12-08 2003-02-07 삼성테크윈 주식회사 Ag 선도금을 이용한 반도체 패키지용 리드프레임
JP2003198117A (ja) 2001-12-28 2003-07-11 Matsushita Electric Ind Co Ltd はんだ付け方法および接合構造体
JP3519726B1 (ja) * 2002-11-26 2004-04-19 Fcm株式会社 端子およびそれを有する部品
CN101546803B (zh) * 2003-01-16 2010-12-08 松下电器产业株式会社 光学半导体器件
JP2004241542A (ja) 2003-02-05 2004-08-26 Matsushita Electric Ind Co Ltd はんだ付け方法およびこのはんだ付け方法により接合される部品および接合された接合構造体
JP2005019922A (ja) * 2003-06-30 2005-01-20 Shinko Electric Ind Co Ltd 半導体パッケージ用リードフレーム
KR100998042B1 (ko) * 2004-02-23 2010-12-03 삼성테크윈 주식회사 리드 프레임 및 이를 구비한 반도체 패키지의 제조방법
CN100483707C (zh) * 2004-05-27 2009-04-29 新光电气工业株式会社 用于半导体器件的引线框架
JP2006269903A (ja) * 2005-03-25 2006-10-05 Shinko Electric Ind Co Ltd 半導体装置用リードフレーム

Also Published As

Publication number Publication date
EP1777743A3 (en) 2008-11-19
JP4820616B2 (ja) 2011-11-24
US8283759B2 (en) 2012-10-09
EP1777743A2 (en) 2007-04-25
US20070090501A1 (en) 2007-04-26
CN1953168A (zh) 2007-04-25
CN1953168B (zh) 2010-07-28
JP2007115925A (ja) 2007-05-10

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