TW200713330A - Delay locked loop circuit - Google Patents

Delay locked loop circuit

Info

Publication number
TW200713330A
TW200713330A TW095123948A TW95123948A TW200713330A TW 200713330 A TW200713330 A TW 200713330A TW 095123948 A TW095123948 A TW 095123948A TW 95123948 A TW95123948 A TW 95123948A TW 200713330 A TW200713330 A TW 200713330A
Authority
TW
Taiwan
Prior art keywords
power down
down mode
signal
clock
clock signal
Prior art date
Application number
TW095123948A
Other languages
Chinese (zh)
Other versions
TWI308346B (en
Inventor
Hoon Choi
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200713330A publication Critical patent/TW200713330A/en
Application granted granted Critical
Publication of TWI308346B publication Critical patent/TWI308346B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/225—Clock input buffers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

A synchronous memory device having a normal mode and a power down mode includes a power down mode controller for generating a power down mode control signal in response to a clock enable signal, thereby determining onset or termination of a power down mode. A clock buffering unit buffers an external clock signal in response to the power down mode control signal and outputs first and second internal clock signals. A clock selection unit selects one of the first and second internal clock signals based on the power down mode control signal to output the selected signal as an intermediate output clock signal. A phase update unit performs a phase update operation by using the intermediate output clock signal to output a delay locked loop (DLL) clock signal, the first internal clock signal differing in frequency from the second internal clock signal.
TW095123948A 2005-09-29 2006-06-30 Synchronous memory device, delayed locked loop and method for generating a delay locked loop clock of a synchronous memory device TWI308346B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20050091659 2005-09-29
KR1020050127734A KR100753101B1 (en) 2005-09-29 2005-12-22 Delay locked loop clock generation method and device for locking fail stop

Publications (2)

Publication Number Publication Date
TW200713330A true TW200713330A (en) 2007-04-01
TWI308346B TWI308346B (en) 2009-04-01

Family

ID=37959233

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095123948A TWI308346B (en) 2005-09-29 2006-06-30 Synchronous memory device, delayed locked loop and method for generating a delay locked loop clock of a synchronous memory device

Country Status (3)

Country Link
KR (1) KR100753101B1 (en)
CN (1) CN100593821C (en)
TW (1) TWI308346B (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100863010B1 (en) * 2007-04-11 2008-10-13 주식회사 하이닉스반도체 Semiconductor integrated circuit
KR100907002B1 (en) * 2007-07-12 2009-07-08 주식회사 하이닉스반도체 Delay Locked Loop And Method For controlling The Same
KR100940849B1 (en) 2008-08-08 2010-02-09 주식회사 하이닉스반도체 Semiconductor integrated circuit and method of controlling the same
CN102142268B (en) * 2010-02-02 2014-04-30 慧荣科技股份有限公司 Control device and relevant control method thereof
KR101923023B1 (en) 2011-08-10 2018-11-28 에스케이하이닉스 주식회사 Delay locked loop
KR102099406B1 (en) 2013-12-30 2020-04-09 에스케이하이닉스 주식회사 Semiconductor apparatus
CN104134457B (en) * 2014-07-17 2018-01-09 北京航空航天大学 A kind of resistance characteristic using non-volatile component realizes the circuit that signal is delayed on piece
KR102439583B1 (en) * 2018-04-30 2022-09-05 에스케이하이닉스 주식회사 Memory device and signal transmitting circuit for the same
US10515670B1 (en) * 2018-06-13 2019-12-24 Nanya Technology Corporation Memory apparatus and voltage control method thereof
CN116545438B (en) * 2023-07-03 2023-11-03 麦斯塔微电子(深圳)有限公司 Frequency divider and multi-modulus frequency divider

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100529041B1 (en) * 2003-05-16 2005-11-17 주식회사 하이닉스반도체 Delay lock loop and phase locking method of synchronous dram
KR100543460B1 (en) * 2003-07-07 2006-01-20 삼성전자주식회사 Delay Locked Loop

Also Published As

Publication number Publication date
TWI308346B (en) 2009-04-01
KR20070036562A (en) 2007-04-03
CN100593821C (en) 2010-03-10
CN1941165A (en) 2007-04-04
KR100753101B1 (en) 2007-08-29

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