TW200713029A - Merging entries in processor caches - Google Patents

Merging entries in processor caches

Info

Publication number
TW200713029A
TW200713029A TW095134603A TW95134603A TW200713029A TW 200713029 A TW200713029 A TW 200713029A TW 095134603 A TW095134603 A TW 095134603A TW 95134603 A TW95134603 A TW 95134603A TW 200713029 A TW200713029 A TW 200713029A
Authority
TW
Taiwan
Prior art keywords
entry
request
requests
incoming
entries
Prior art date
Application number
TW095134603A
Other languages
English (en)
Inventor
Yang Jeff Jiao
Yi-Ping Chen
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Publication of TW200713029A publication Critical patent/TW200713029A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW095134603A 2005-09-19 2006-09-19 Merging entries in processor caches TW200713029A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/229,884 US20070067567A1 (en) 2005-09-19 2005-09-19 Merging entries in processor caches

Publications (1)

Publication Number Publication Date
TW200713029A true TW200713029A (en) 2007-04-01

Family

ID=37885581

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095134603A TW200713029A (en) 2005-09-19 2006-09-19 Merging entries in processor caches

Country Status (3)

Country Link
US (1) US20070067567A1 (zh)
CN (1) CN1967506B (zh)
TW (1) TW200713029A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI453584B (zh) * 2010-08-17 2014-09-21 Intel Corp 處理非對準式記憶體存取的設備、系統及方法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070153015A1 (en) * 2006-01-05 2007-07-05 Smedia Technology Corporation Graphics processing unit instruction sets using a reconfigurable cache
US20100250651A1 (en) * 2009-03-31 2010-09-30 Inventec Corporation Data access method for making asynchronous request to block device
US8301865B2 (en) * 2009-06-29 2012-10-30 Oracle America, Inc. System and method to manage address translation requests
US9361165B2 (en) * 2009-12-03 2016-06-07 International Business Machines Corporation Automated merger of logically associated messages in a message queue
US8370582B2 (en) * 2010-01-26 2013-02-05 Hewlett-Packard Development Company, L.P. Merging subsequent updates to a memory location
US8447932B2 (en) * 2010-06-22 2013-05-21 International Business Machines Corporation Recover store data merging
US9684601B2 (en) * 2012-05-10 2017-06-20 Arm Limited Data processing apparatus having cache and translation lookaside buffer
US9892125B1 (en) * 2014-05-23 2018-02-13 MapD Technologies, Inc. Method for logging update queries
CN104778131B (zh) * 2015-04-29 2017-07-21 浪潮电子信息产业股份有限公司 一种数据缓存方法及一种缓冲存储器
US9626232B2 (en) * 2015-07-23 2017-04-18 Arm Limited Event queue management
US11099990B2 (en) * 2019-08-20 2021-08-24 Apple Inc. Managing serial miss requests for load operations in a non-coherent memory system
US20220374359A1 (en) * 2021-05-19 2022-11-24 Apple Inc. Multi-block Cache Fetch Techniques
CN117742793B (zh) * 2023-11-01 2024-07-02 上海合芯数字科技有限公司 数据缓存指令的指令合并电路、方法及芯片

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5615343A (en) * 1993-06-30 1997-03-25 Intel Corporation Method and apparatus for performing deferred transactions
US5809530A (en) * 1995-11-13 1998-09-15 Motorola, Inc. Method and apparatus for processing multiple cache misses using reload folding and store merging
US6055605A (en) * 1997-10-24 2000-04-25 Compaq Computer Corporation Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches
US6336168B1 (en) * 1999-02-26 2002-01-01 International Business Machines Corporation System and method for merging multiple outstanding load miss instructions
US6321303B1 (en) * 1999-03-18 2001-11-20 International Business Machines Corporation Dynamically modifying queued transactions in a cache memory system
US7941585B2 (en) * 2004-09-10 2011-05-10 Cavium Networks, Inc. Local scratchpad and data caching system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI453584B (zh) * 2010-08-17 2014-09-21 Intel Corp 處理非對準式記憶體存取的設備、系統及方法

Also Published As

Publication number Publication date
CN1967506A (zh) 2007-05-23
CN1967506B (zh) 2010-10-06
US20070067567A1 (en) 2007-03-22

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