ATE467174T1 - Effiziente speicherhierarchieverwaltung - Google Patents

Effiziente speicherhierarchieverwaltung

Info

Publication number
ATE467174T1
ATE467174T1 AT07710245T AT07710245T ATE467174T1 AT E467174 T1 ATE467174 T1 AT E467174T1 AT 07710245 T AT07710245 T AT 07710245T AT 07710245 T AT07710245 T AT 07710245T AT E467174 T1 ATE467174 T1 AT E467174T1
Authority
AT
Austria
Prior art keywords
instruction
cache
data
data cache
processor
Prior art date
Application number
AT07710245T
Other languages
English (en)
Inventor
Michael William Morrow
Thomas Andrew Sartorius
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Application granted granted Critical
Publication of ATE467174T1 publication Critical patent/ATE467174T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Debugging And Monitoring (AREA)
  • Communication Control (AREA)
  • Automatic Assembly (AREA)
AT07710245T 2006-01-20 2007-01-22 Effiziente speicherhierarchieverwaltung ATE467174T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/336,282 US7552283B2 (en) 2006-01-20 2006-01-20 Efficient memory hierarchy management
PCT/US2007/060815 WO2007085011A2 (en) 2006-01-20 2007-01-22 Efficient memory hierarchy management

Publications (1)

Publication Number Publication Date
ATE467174T1 true ATE467174T1 (de) 2010-05-15

Family

ID=38058452

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07710245T ATE467174T1 (de) 2006-01-20 2007-01-22 Effiziente speicherhierarchieverwaltung

Country Status (12)

Country Link
US (1) US7552283B2 (de)
EP (1) EP1974256B1 (de)
JP (1) JP5065298B2 (de)
KR (1) KR100955101B1 (de)
CN (2) CN102866879B (de)
AT (1) ATE467174T1 (de)
BR (1) BRPI0707149A2 (de)
CA (1) CA2635116C (de)
DE (1) DE602007006276D1 (de)
ES (1) ES2345733T3 (de)
RU (1) RU2397534C2 (de)
WO (1) WO2007085011A2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE602005017832D1 (de) * 2004-11-22 2009-12-31 Honda Motor Co Ltd Vorrichtung zur Installation eines weichen Elements
JP4376173B2 (ja) * 2004-11-30 2009-12-02 本田技研工業株式会社 モール装着方法及びその装置
EP1950125B1 (de) * 2005-11-16 2009-07-15 HONDA MOTOR CO., Ltd. Verfahren und vorrichtung zur montage eines weichen elements
EP1953073B1 (de) * 2005-11-24 2011-06-22 Honda Motor Co., Ltd. Verfahren und vorrichtung zur installation einer offenen dichtung
US7555605B2 (en) * 2006-09-28 2009-06-30 Freescale Semiconductor, Inc. Data processing system having cache memory debugging support and method therefor
KR100877611B1 (ko) * 2007-02-08 2009-01-09 삼성전자주식회사 플래시 메모리 내장 마이크로 컨트롤러 유닛 시스템 및상기 마이크로 컨트롤러 유닛의 플래시 메모리 접근 방법
US8255629B2 (en) * 2009-06-22 2012-08-28 Arm Limited Method and apparatus with data storage protocols for maintaining consistencies in parallel translation lookaside buffers
JP5903173B2 (ja) * 2012-02-22 2016-04-13 ヒューレット−パッカード デベロップメント カンパニー エル．ピー．Ｈｅｗｌｅｔｔ‐Ｐａｃｋａｒｄ Ｄｅｖｅｌｏｐｍｅｎｔ Ｃｏｍｐａｎｙ， Ｌ．Ｐ． コンピュータ上のオペレーティングシステムからの論理プロセッサの隠蔽
WO2014142867A1 (en) 2013-03-14 2014-09-18 Intel Corporation Power efficient level one data cache access with pre-validated tags
CN105103121B (zh) 2013-03-28 2018-10-26 慧与发展有限责任合伙企业 刀片***以及刀片***的分区执行方法
WO2014158161A1 (en) 2013-03-28 2014-10-02 Hewlett-Packard Development Company, L.P. Error coordination message for a blade device having a logical processor in another system firmware domain
US9781015B2 (en) 2013-03-28 2017-10-03 Hewlett Packard Enterprise Development Lp Making memory of compute and expansion devices available for use by an operating system
US9824021B2 (en) 2014-03-31 2017-11-21 International Business Machines Corporation Address translation structures to provide separate translations for instruction fetches and data accesses
US9734083B2 (en) * 2014-03-31 2017-08-15 International Business Machines Corporation Separate memory address translations for instruction fetches and data accesses
US9715449B2 (en) 2014-03-31 2017-07-25 International Business Machines Corporation Hierarchical translation structures providing separate translations for instruction fetches and data accesses

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4719568A (en) * 1982-12-30 1988-01-12 International Business Machines Corporation Hierarchical memory system including separate cache memories for storing data and instructions
US5287467A (en) * 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
US5440707A (en) * 1992-04-29 1995-08-08 Sun Microsystems, Inc. Instruction and data cache with a shared TLB for split accesses and snooping in the same clock cycle
JPH06100982B2 (ja) * 1992-05-20 1994-12-12 工業技術院長 階層キャッシュ・メモリ装置
JPH086853A (ja) * 1994-06-22 1996-01-12 Hitachi Ltd 記憶制御方法
US5737749A (en) 1996-05-20 1998-04-07 International Business Machines Corporation Method and system for dynamically sharing cache capacity in a microprocessor
US6260114B1 (en) * 1997-12-30 2001-07-10 Mcmz Technology Innovations, Llc Computer cache memory windowing
US6480952B2 (en) * 1998-05-26 2002-11-12 Advanced Micro Devices, Inc. Emulation coprocessor
JP2002007212A (ja) * 2000-06-19 2002-01-11 Sony Corp キャッシュ・メモリ・システム及びキャッシュ・メモリ制御方法
US7873776B2 (en) * 2004-06-30 2011-01-18 Oracle America, Inc. Multiple-core processor with support for multiple virtual processors
GB2426082B (en) 2005-05-09 2007-08-15 Sony Comp Entertainment Europe Memory caching in data processing

Also Published As

Publication number Publication date
WO2007085011A3 (en) 2007-10-04
CN102866879A (zh) 2013-01-09
CA2635116A1 (en) 2007-07-26
EP1974256A2 (de) 2008-10-01
CA2635116C (en) 2011-05-17
BRPI0707149A2 (pt) 2011-04-19
US7552283B2 (en) 2009-06-23
WO2007085011A2 (en) 2007-07-26
ES2345733T3 (es) 2010-09-30
RU2008134124A (ru) 2010-02-27
KR20080091481A (ko) 2008-10-13
CN101371224B (zh) 2013-03-27
CN102866879B (zh) 2015-10-28
CN101371224A (zh) 2009-02-18
JP5065298B2 (ja) 2012-10-31
DE602007006276D1 (de) 2010-06-17
RU2397534C2 (ru) 2010-08-20
JP2009524168A (ja) 2009-06-25
EP1974256B1 (de) 2010-05-05
KR100955101B1 (ko) 2010-04-28
US20070174553A1 (en) 2007-07-26

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties