TW200711074A - Packaging for high speed integrated circuits - Google Patents

Packaging for high speed integrated circuits

Info

Publication number
TW200711074A
TW200711074A TW095125824A TW95125824A TW200711074A TW 200711074 A TW200711074 A TW 200711074A TW 095125824 A TW095125824 A TW 095125824A TW 95125824 A TW95125824 A TW 95125824A TW 200711074 A TW200711074 A TW 200711074A
Authority
TW
Taiwan
Prior art keywords
lead
pad
adjacent
packaging
high speed
Prior art date
Application number
TW095125824A
Other languages
Chinese (zh)
Inventor
Sehat Sutardja
Original Assignee
Marvell World Trade Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/248,985 external-priority patent/US20070018292A1/en
Application filed by Marvell World Trade Ltd filed Critical Marvell World Trade Ltd
Publication of TW200711074A publication Critical patent/TW200711074A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

An integrated circuit package comprises an integrated circuit die comprising a first pad, a second pad adjacent to the first pad, a third pad adjacent to the second pad, and a fourth pad adjacent to the third pad. A lead frame comprises a first lead, a second lead adjacent to the first lead, a third lead adjacent to the second lead, and a fourth lead adjacent to the third lead, wherein a first end of the fourth lead extends beyond at least one of the first, second, and third leads and in a direction towards a path defined by the third lead. First, second, third and fourth bondwires connecting the first, second, fourth and third leads to the first, second, third and fourth pads, respectively.
TW095125824A 2005-07-22 2006-07-14 Packaging for high speed integrated circuits TW200711074A (en)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US70170105P 2005-07-22 2005-07-22
US72227205P 2005-09-30 2005-09-30
US11/248,985 US20070018292A1 (en) 2005-07-22 2005-10-12 Packaging for high speed integrated circuits
US11/472,904 US7884451B2 (en) 2005-07-22 2006-06-22 Packaging for high speed integrated circuits
US11/472,697 US20070096277A1 (en) 2005-07-22 2006-06-22 Packaging for high speed integrated circuits
US11/472,953 US20070018289A1 (en) 2005-07-22 2006-06-22 Packaging for high speed integrated circuits
US11/473,702 US7638870B2 (en) 2005-07-22 2006-06-23 Packaging for high speed integrated circuits
US11/473,631 US20070018293A1 (en) 2005-07-22 2006-06-23 Packaging for high speed integrated circuits
US11/474,198 US20070018294A1 (en) 2005-07-22 2006-06-23 Packaging for high speed integrated circuits

Publications (1)

Publication Number Publication Date
TW200711074A true TW200711074A (en) 2007-03-16

Family

ID=50158248

Family Applications (3)

Application Number Title Priority Date Filing Date
TW095125822A TW200733827A (en) 2005-07-22 2006-07-14 Packaging for high speed integrated circuits
TW095125824A TW200711074A (en) 2005-07-22 2006-07-14 Packaging for high speed integrated circuits
TW095125825A TWI418012B (en) 2005-07-22 2006-07-14 Packaging for high speed integrated circuits

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW095125822A TW200733827A (en) 2005-07-22 2006-07-14 Packaging for high speed integrated circuits

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW095125825A TWI418012B (en) 2005-07-22 2006-07-14 Packaging for high speed integrated circuits

Country Status (1)

Country Link
TW (3) TW200733827A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI819960B (en) * 2023-02-03 2023-10-21 瑞昱半導體股份有限公司 Ic package structure capable of increasing isolation between interference sources

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI456939B (en) * 2012-02-24 2014-10-11 Realtek Semiconductor Corp Ethernet communication circuit with auto mdi/mdix function

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5457340A (en) * 1992-12-07 1995-10-10 Integrated Device Technology, Inc. Leadframe with power and ground planes
US5646451A (en) * 1995-06-07 1997-07-08 Lucent Technologies Inc. Multifunctional chip wire bonds
US6567413B1 (en) * 2001-05-18 2003-05-20 Network Elements, Inc. Optical networking module including protocol processing and unified software control

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI819960B (en) * 2023-02-03 2023-10-21 瑞昱半導體股份有限公司 Ic package structure capable of increasing isolation between interference sources

Also Published As

Publication number Publication date
TW200733827A (en) 2007-09-01
TWI418012B (en) 2013-12-01
TW200742027A (en) 2007-11-01

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