TW200605215A - Semiconductor device fabrication method - Google Patents

Semiconductor device fabrication method

Info

Publication number
TW200605215A
TW200605215A TW094120281A TW94120281A TW200605215A TW 200605215 A TW200605215 A TW 200605215A TW 094120281 A TW094120281 A TW 094120281A TW 94120281 A TW94120281 A TW 94120281A TW 200605215 A TW200605215 A TW 200605215A
Authority
TW
Taiwan
Prior art keywords
silicon layer
semiconductor device
fabrication method
device fabrication
insulating layer
Prior art date
Application number
TW094120281A
Other languages
English (en)
Inventor
Takashi Kawasaki
Original Assignee
Sharp Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kk filed Critical Sharp Kk
Publication of TW200605215A publication Critical patent/TW200605215A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW094120281A 2004-06-18 2005-06-17 Semiconductor device fabrication method TW200605215A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004181390A JP2006005237A (ja) 2004-06-18 2004-06-18 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
TW200605215A true TW200605215A (en) 2006-02-01

Family

ID=34979291

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094120281A TW200605215A (en) 2004-06-18 2005-06-17 Semiconductor device fabrication method

Country Status (6)

Country Link
US (1) US7030019B2 (zh)
EP (1) EP1608008A3 (zh)
JP (1) JP2006005237A (zh)
KR (1) KR100726746B1 (zh)
CN (1) CN1710704A (zh)
TW (1) TW200605215A (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100805832B1 (ko) * 2005-10-24 2008-02-21 삼성전자주식회사 화학기계적 연마 방법 및 이를 이용한 반도체 장치의 제조방법
KR100842471B1 (ko) 2006-12-28 2008-07-01 동부일렉트로닉스 주식회사 반도체 소자의 ｍｉｍ캐패시터 형성 방법
US7832090B1 (en) 2010-02-25 2010-11-16 Unity Semiconductor Corporation Method of making a planar electrode
JP5938920B2 (ja) * 2012-01-26 2016-06-22 富士通セミコンダクター株式会社 半導体装置の製造方法
CN113540389B (zh) * 2021-07-19 2024-02-02 昆山梦显电子科技有限公司 一种oled阳极的制备方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5618381A (en) * 1992-01-24 1997-04-08 Micron Technology, Inc. Multiple step method of chemical-mechanical polishing which minimizes dishing
JPH07249626A (ja) * 1994-03-10 1995-09-26 Toshiba Corp 半導体装置の製造方法
US6069081A (en) * 1995-04-28 2000-05-30 International Buiness Machines Corporation Two-step chemical mechanical polish surface planarization technique
JP3477484B2 (ja) * 1997-03-24 2003-12-10 松下電器産業株式会社 半導体装置の製造方法
US5804490A (en) * 1997-04-14 1998-09-08 International Business Machines Corporation Method of filling shallow trenches
US6103625A (en) * 1997-12-31 2000-08-15 Intel Corporation Use of a polish stop layer in the formation of metal structures
US6162368A (en) 1998-06-13 2000-12-19 Applied Materials, Inc. Technique for chemical mechanical polishing silicon
KR100347533B1 (ko) * 1999-12-24 2002-08-03 주식회사 하이닉스반도체 반도체 소자의 금속 배선 형성 방법
JP2001358105A (ja) 2000-06-12 2001-12-26 Mitsubishi Electric Corp 埋め込み配線の形成方法およびｃｍｐ装置、並びに半導体装置およびその製造方法
KR100382541B1 (ko) * 2000-09-21 2003-05-01 주식회사 하이닉스반도체 반도체 소자의 플러그 형성 방법
KR100416587B1 (ko) * 2000-12-22 2004-02-05 삼성전자주식회사 씨엠피 연마액
KR20030044363A (ko) * 2001-11-29 2003-06-09 주식회사 하이닉스반도체 반도체소자의 평탄화방법
US6723640B2 (en) * 2002-06-29 2004-04-20 Hynix Semiconductor Inc. Method for forming contact plug of semiconductor device
KR100546133B1 (ko) * 2002-07-19 2006-01-24 주식회사 하이닉스반도체 반도체소자의 형성방법
JP4083502B2 (ja) 2002-08-19 2008-04-30 株式会社フジミインコーポレーテッド 研磨方法及びそれに用いられる研磨用組成物

Also Published As

Publication number Publication date
US7030019B2 (en) 2006-04-18
EP1608008A3 (en) 2008-02-20
JP2006005237A (ja) 2006-01-05
CN1710704A (zh) 2005-12-21
US20050282389A1 (en) 2005-12-22
KR20060049199A (ko) 2006-05-18
KR100726746B1 (ko) 2007-06-11
EP1608008A2 (en) 2005-12-21

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