200540874 16712pif.doc 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種快閃記憶體裝置，且特別是 ' 於一種電壓升壓控制的電路與方法。 【先前技術】 通常，快閃記憶體具有三種操作模式，即讀取，程式 化，擦除。依照快閃記憶體的類型，每種快閃記憶體使^ 纟典型的偏壓電壓。例如，-個分離間極型快閃記憶體藉 響㈣極側的熱載流子注人來程式化，即從源_汲極注乂 一個程式化電流到記憶胞。一個升壓電壓用於提供程式化 電流。-般，升壓電壓總是高於資料讀取操作所需的電壓。 一個不同的電壓是用於為擦除操作而產生足夠的電場。 圖1繪示了一個習知的分離閘極快閃記憶胞陣列。快 閃記憶胞未程式化時其資料為“丨”，為給記憶胞編入資料 ，比如M5，源極線(SL)連接到升壓電壓VPP，字元線 (WL2)連接到稍低於升壓電壓的電壓。位元線(BLl)連接到 • 邏輯“0”準位，傳輸電晶體(P1)被(A1)之啟動電壓所開啟。 加了上述電壓後，記憶胞(M5)開啟，程式化電流⑴從源極 線(SL)流到位元線(BL1)。程式化電流(1)產生的熱載流子注 入到分離閘極並且程式化記憶胞(M5)。由於一般有大量記 憶胞連接到源極線上，如果有很多記憶胞要被編為資料 0，總程式化電流增加，源極線(SL)上的電墨準位由於負 載大而降低。連接到源極線(SL)的升壓電壓(VPP)不得不上 升以適應這種情況。但是，如果升壓電壓(vpp)上升，當較 200540874 16712pif.doc 胞要被編為轉τ時，就會有超過需要的過量注 =電==。在此财，由於高的升㈣齡料化電流， 作…量的的記憶胞的操 圖2纟t^F 了-㈣知的提供升壓祕νρ 電路包括—電顧升部份2卜其依 一個幫浦電路213。當受到振盡器221振 盧二’幫浦電路213在不同準位輸出—個制電壓替， 二關，在幫浦電路中的電荷幫浦(未顯示） 個斗iU 111預5又的向準位。通過位準檢測器23，— η vpp的檢測部分輸出到VDET。當檢測 „高於參她vref時，hvdet ί輯輸出0sc#閉鎖’反或閘212的輸出ί 電路213的電荷抽取停止，VPP輪出一個 =設的高準位。使用這種習知的升壓電路，由於升壓電壓 =回授部分被婦的檢測，所以電壓升壓控制是粗輪的押 :。用_習知升壓電路’當要編為τ的記憶胞數量從一 =己憶胞陣列到下-個陣列不同時，記憶胞陣列的單獨吃 隱胞仍會因高注人電流而受到不必要壓力的準位。 因此，需要-個控制升壓電壓的電路和方法， L用於改+ ¾式化記‘It胞的數量的程^化電流。 【發明内容】 本發明提供了-種用於記憶裝置的電路，包括 位準檢測器’其接收多數個程式化輸入信號’檢測那些程 200540874 16712pif.doc 式化準位為有效的’並根據有效的多數個程式化輸入信 號’輸出可變權重的多數個檢測信號。—個信號產生器， ，位準檢測ϋ接收檢測信號並輪出—產生㈣，此產生信 號具有—可變電壓準位且此可變電壓準位係與檢測信號 的可變權重成_。與-個電壓升壓器，其控制一個基於 產生彳a 5虎的偏壓源電壓準位。 上述之電路其準位檢測電路包括：多數個接收電晶 體，其接收各自的多個程式化輸人信號。與—個連接到多 晶體的第-電阻網路’其根據程式化輸人信號有效 立文畺在相應的母個網路節點上輸出一個固定電壓的一 部分。 „„上述之電路更包括一個連接到各網路節點的比較 裔’將在網路節點上的電壓準位與參考電壓相比較，並基 於各網路節點上的電壓準位，輸出可變權重的檢測信號。 上述之電路其㈣產生器包括多數個接收相應檢測 _號的電日日體’接收電晶體連接到—個受偏壓源偏壓的第 電阻網路’該第二電阻網路有_個供輸出產生信號的節 黑占。 ^上述之電路其電壓升壓器包括一個比較器，其將產生 =號與參考信號比較以輸出一個比較信號，該比較信號在 一個準位導致偏壓源電壓上升而在另一個準位則不會上 升。 曰 上述之電路其記憶體是快閃記憶體。 上述之電路其快閃記憶體是分離閘極型或者堆疊閘 200540874 167I2pif.doc 極型中的一種。 上述之f路其偏壓源用於提供快閃記憶體的程式化 電流。 上述之電路其偏壓源的電壓準位是與程式化輸入信 號有效的之數量成比例的增加。 同時也提供了一個控制記憶裝置偏壓源的方法，包括 接收夕數個耘式化輸入信號。根據程式化信號有效的數量 的可k權重產生檢難號。產生—產生健且該產生信號 具有一可變電壓準位與檢測信號的可變權重成比例。和基 於產生信號控制偏壓源的電麼準位。 上述之方法更包括在多數個接收電晶體上接收相應 的多數個程式化輸入信號，接收電晶體連接到一個電阻網 路，根據程式化輸入仏號有效的數量在相應的每個網路節 點上輸出一個固定電壓的一部分。 上述之方法更包括將在網路節點上的電壓準位與_ 參考電壓相比較，並基於各網路節點上的電壓準位，產生 可變權重的檢測信號。 上述之方法更包括在多數個接收電晶體上接收相應 的一檢測信號，接收電晶體連接到一個受偏壓源偏壓的電 阻網路，此電阻網路有一個節點輸出產生信號。 上述之方法更包括比較產生信號的電壓準位與_表 考電壓以輸出一個比較信號，該比較信號在一個準位導^欠 偏壓源電壓上升而在另一個準位則偏壓源電壓不會上升。 上述之方法其記憶體是快閃記憶體。 8 200540874 16712pif.doc 上述之方法其快閃記憶體是分離閘極型或者堆疊間 極型中的一種。 ^ 上述之方法其偏_用於提供快閃記憶體的程式化 電流。 上述之方法其偏壓源的電壓準位是與程式化輸入信 號有效的之數量成比例的增加。 依照本案的另-表述，提供了一個用於記憶裝置的電 路，包括.接收多數個程式化輸入信號，檢測哪些程式化 輸入信财效的，並根據程式化錢為有效的之數量輸出 :變權重的檢翁號料段。減_錢並輸出一產生 信號，此產生信號具有與檢測信號的可變權重成比例變化 的電壓準㈣手段。以及基於此產生錢控機魏電壓 準位的手段。 上述之用於記憶裝置的電路其記憶體是快閃記憶體。 上述之用於記憶裝置的電路其快閃記憶體是分離閘 極型或者堆疊閘極型中的一種。 上述之用於記憶裝置的電路其偏壓源用於提供快閃 記憶體的程式化電流。 上述之用於記憶裝置的電路其偏壓源的電壓準位是 與程式化輸入信號為有效的之數量成比例地增加。 ^個用於ό己憶裝置的電路，包括一個輸入測量器，其 ^又夕數個程式化輸人㈣，㈣程式化信號有效的數量 輸^個具有可變電壓準位的產生信號。以及―個基於產 生仏號控制偏壓源之電壓準位的電壓升壓器。 9 200540874 16712pif.doc 上述之用於記憶裝置的電路其記憶體是快閃記憶體。 上述之用於記憶裝置的電路其快閃記憶體是分離閘 極型或者堆疊閘極型中的一種。 上述之用於記憶裝置的電路其偏壓源用於提供快閃 記憶體的程式化電流。 上述之用於記憶裝置的電路其此偏壓源的電壓準位 疋與私式化輸入信號為有效的之數量成比例地增加。 【實施方式】 圖3繪示了一個依照本發明的一個實施例的升壓電 路。胃升壓電路300包括一個幫浦控制電路3丨以及一個升壓 電壓和程式化輸入檢測電路(此後稱“檢測電路，，)33。幫浦 控制電路31包括一個振盪器311用以提供一個振盪信號給 幫浦電路313以在變化的準位輸出一個升壓電壓vpp。振 盈器311的振盪信號可以藉由來自運算放大器314的 HVDET的高準位輸入而鎖定在反或閘312。運算放大器 314的輸入是參考電壓VREF和來自檢測電路％的升壓檢 測輸出VDET。 檢測電路33包括一個位準檢測器331和一個信號產 生為333。位準檢測器331接收輸入資料DATA(O)到DATA (η)和輸出DET(x)信號，其表示了 DAT A0到DAT An要被 程式化信號數量的權重。信號產生器333接收DETx信號 並輸出一個升壓檢測信號VDET，其與DETx信號及升壓 電壓VPP的準位成比例。當VDET信號高於VREF，運算 放大器314的HVDET信號處於高準位，閉鎖來自振盪器 200540874 16712pif.doc 311的OSC輸出。在此例中，反或閘312的輸出是邏輯 “〇”，電荷，浦停止，VPP設為預設的非幫浦準位。200540874 16712pif.doc IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a flash memory device, and more particularly, to a circuit and method for voltage boost control. [Prior art] Generally, flash memory has three operation modes, namely, read, program, and erase. Depending on the type of flash memory, each flash memory uses a typical bias voltage. For example, a split-type flash memory is programmed by injecting hot carriers on the cathode side, that is, a stylized current is injected from the source_drain to the memory cell. A boost voltage is used to provide a stylized current. -Generally, the boosted voltage is always higher than the voltage required for the data read operation. A different voltage is used to generate a sufficient electric field for the erase operation. Figure 1 illustrates a conventional split-gate flash memory cell array. When the flash memory cell is not programmed, its data is "丨". To program the memory cell, such as M5, the source line (SL) is connected to the boost voltage VPP, and the character line (WL2) is connected to Voltage of the voltage. The bit line (BL1) is connected to a logic “0” level, and the transmission transistor (P1) is turned on by the start voltage of (A1). After the above voltage is applied, the memory cell (M5) is turned on, and the stylized current 流 flows from the source line (SL) to the bit line (BL1). The hot carriers generated by the programmed current (1) are injected into the separation gate and the memory cell (M5) is programmed. Because there are generally a large number of memory cells connected to the source line, if there are many memory cells to be programmed as data 0, the total programmed current increases, and the level of the electro-ink on the source line (SL) decreases due to the large load. The boosted voltage (VPP) connected to the source line (SL) has to rise to accommodate this situation. However, if the boosted voltage (vpp) rises, when the cell is programmed to be τ as compared to 200540874 16712pif.doc, there will be more than necessary. Note = electricity ==. In this case, due to the high aging current, the operation of the memory cell is as follows: 2 纟 t ^ F-Known to provide a boosting circuit νρ circuit includes-the electric Gu Sheng part 2 According to a pump circuit 213. When it is subjected to the vibration killer 221, the pump circuit 213 is output at a different level—a switching voltage, the second switch, and the charge pump in the pump circuit (not shown). Level. Through the level detector 23, the detection portion of -n vpp is output to VDET. When the detection level is higher than the reference vref, the hvdet ί series output 0sc # locks the output of the OR gate 212. The charge extraction of the circuit 213 stops, and the VPP turns to a high level. Voltage circuit, because the boost voltage = feedback part of the woman's detection, so the voltage boost control is a rough round:. Use the _know boost circuit 'when the number of memory cells to be programmed as τ from one = memory cell array When the next array is different, the individual cells of the memory cell array will still be subjected to unnecessary pressure due to the high injection current. Therefore, a circuit and method for controlling the boost voltage are needed, and L is used to modify + ¾ formulaized the current of the number of It cells. [Summary of the invention] The present invention provides a circuit for a memory device, including a level detector 'which receives a plurality of stylized input signals' to detect those Cheng 200540874 16712pif.doc formulates the level to be effective 'and outputs a plurality of detection signals with variable weights according to the effective number of stylized input signals'. A signal generator, level detection ϋ receives the detection signal and turns出 —produce tritium, this property The generation signal has a variable voltage level and this variable voltage level is _ with a variable weight of the detection signal. And a voltage booster that controls a voltage source based on the bias source voltage of 彳 a 5 tiger The level detection circuit of the above-mentioned circuit includes: a plurality of receiving transistors, which receive respective multiple stylized input signals. And a -resistive network connected to the polycrystals, which are inputted according to the stylization. The signal is valid, and a part of a fixed voltage is output on the corresponding network nodes. „„ The above circuit also includes a comparison node connected to each network node 'and the voltage level on the network nodes and The reference voltage is compared, and a variable weighted detection signal is output based on the voltage level on each network node. The above-mentioned circuit includes a plurality of electric generators that receive the corresponding detection _ number of electric sun and sun body 'receiving transistor connections To a second resistor network that is biased by a bias source. The second resistor network has a node for the output to generate a signal. ^ The voltage booster of the above circuit includes a comparator, which will generate = It compares with the reference signal to output a comparison signal. The comparison signal causes the bias source voltage to rise at one level but not rise at the other level. The circuit of the above-mentioned circuit is a flash memory. The circuit described above The flash memory is one of the split gate type or stacked gate 200540874 167I2pif.doc. The above f-channel bias source is used to provide the programmed current of the flash memory. The above circuit has its bias source The voltage level is increased in proportion to the number of programmed input signals available. It also provides a method for controlling the bias source of the memory device, including receiving several input signals. The effective according to the programmed signal The number of k-weights can generate a detection number. The generation-generation signal has a variable voltage level proportional to the variable weight of the detection signal. The sum level is controlled based on the signal generated by the sum signal. The above method further includes receiving a corresponding plurality of stylized input signals on a plurality of receiving transistors, the receiving transistors are connected to a resistor network, and the number of valid input signals according to the stylized input is on each corresponding network node. Outputs a portion of a fixed voltage. The above method further includes comparing the voltage level on the network node with the reference voltage and generating a variable weighted detection signal based on the voltage level on each network node. The above method further includes receiving corresponding detection signals on a plurality of receiving transistors, and the receiving transistors are connected to a resistor network biased by a bias source. The resistor network has a node output to generate a signal. The above method further includes comparing the voltage level of the generated signal with the test voltage to output a comparison signal. The comparison signal leads to an increase in the voltage of the under-biased source at one level and the voltage of the biased source does not rise at another level. Will rise. The memory of the above method is flash memory. 8 200540874 16712pif.doc The flash memory of the above method is one of the split gate type or stacked stack type. ^ The above method is biased to provide a stylized current for flash memory. In the above method, the voltage level of the bias source is increased in proportion to the number of stylized input signals available. According to another expression of this case, a circuit for a memory device is provided, including: receiving a plurality of stylized input signals, detecting which stylized inputs are financially effective, and outputting according to the amount of stylized money that is valid: change The weight of the checker number material segment. The money is subtracted and a generation signal is output, the generation signal having a voltage standard means that varies in proportion to the variable weight of the detection signal. And based on this means to generate money control machine Wei voltage level. The memory of the circuit for a memory device described above is a flash memory. In the above-mentioned circuit for a memory device, the flash memory is one of a split gate type or a stacked gate type. In the above circuit for a memory device, the bias source is used to provide a programmed current for the flash memory. The voltage level of the bias source of the aforementioned circuit for a memory device is increased in proportion to the number of stylized input signals that are valid. A circuit for a self-memory device includes an input measuring device, which includes several programmed input signals, and the effective number of the programmed signals inputs a generated signal with a variable voltage level. And a voltage booster based on the voltage level of the control bias source that generates the signal. 9 200540874 16712pif.doc The circuit used in the memory device described above is flash memory. In the above-mentioned circuit for a memory device, the flash memory is one of a split gate type or a stacked gate type. In the above circuit for a memory device, the bias source is used to provide a programmed current for the flash memory. In the above-mentioned circuit for a memory device, the voltage level 此 of the bias source is increased in proportion to the number of validating input signals. [Embodiment] FIG. 3 illustrates a booster circuit according to an embodiment of the present invention. The gastric boost circuit 300 includes a pump control circuit 3, and a boost voltage and stylized input detection circuit (hereinafter referred to as "detection circuit," 33). The pump control circuit 31 includes an oscillator 311 to provide an oscillation The signal is supplied to the pump circuit 313 to output a boosted voltage vpp at a changed level. The oscillation signal of the oscillator 311 can be locked at the inverse OR gate 312 by the high-level input of the HVDET from the operational amplifier 314. The operational amplifier The input of 314 is the reference voltage VREF and the boost detection output VDET from the detection circuit%. The detection circuit 33 includes a level detector 331 and a signal generated as 333. The level detector 331 receives the input data DATA (O) to DATA (η) and the output DET (x) signal, which indicates the weight of the number of signals to be programmed from DAT A0 to DAT An. The signal generator 333 receives the DETx signal and outputs a boost detection signal VDET, which is in combination with the DETx signal and the The level of the voltage VPP is proportional. When the VDET signal is higher than VREF, the HVDET signal of the operational amplifier 314 is at a high level, and the OSC output from the oscillator 200540874 16712pif.doc 311 is blocked In this embodiment, the output of NOR gate 312 is a logic "square", charge pump is stopped, the VPP is set to a predetermined level of non-pump.
圖4是一個圖3中的位準檢測器331的示意方塊圖。 位準檢測器、311包括一個檢測電壓產生$ 41卩及一個比 較電路43。檢測電壓產生器41通過]^厘〇§電晶體nm(〇) 到NM(n)檢測輸入資料DATA〇到DATAn (本實例中， n=31) ’電晶體的閘極連接到相應的輸入端data〇到 DATAn，其汲極共同連接到節點N而源極連接到地或 vss。在閘極輸入接收到有效信號時，NM〇到NMn的各 個電晶體在節點N對地或VSS呈現低阻抗。因此，如果 大量記憶胞要被程式化，大量電晶體NM〇到NMn將呈現 低阻抗，呈現在節點N上的並聯阻抗將甚至低於或接近FIG. 4 is a schematic block diagram of the level detector 331 in FIG. 3. The level detector 311 includes a detection voltage generating $ 41 卩 and a comparison circuit 43. The detection voltage generator 41 detects the input data DATA0 to DATAn (in this example, n = 31) through the transistor nm (〇) to NM (n) 'The gate of the transistor is connected to the corresponding input terminal data0 to DATAn, whose drains are connected in common to node N and the source is connected to ground or vss. When a valid signal is received at the gate input, each transistor of NM0 to NMn exhibits low impedance at node N to ground or VSS. Therefore, if a large number of memory cells are to be programmed, a large number of transistors NM0 to NMn will exhibit low impedance, and the parallel impedance presented at node N will even be lower or close to
Rw間的各節點上產生了檢測電壓DETI1、DETI2、 日日體PM1，電晶體pM1並連接到偏壓電壓VDD。、 RY、RX和汉冒的阻值以1K、1K、2K和1〇Κ歐姆為佳。 通過此電晶體和電阻網路，在串聯電阻RZ、RY、RX和 DETD，其表示了依DATA0到DATAn的有效信號數量變 化的權重。比如資料DATA“〇，，(增加），=> 關閉的NM〇s (增加）=>IDET (減少卜〉電壓DETI1〜DETI3 (增加）。 比較電路43包括放大器431與位準移位器433。放大 為431接收檢測信號(DET1到3)和參考電壓VREF作比較 並輸出到位準移位器、433，其巾，VPP同時輸入作適當的 轉換和輸出信號(DET01〜DET03)的參考。資料‘‘〇，，（增加) 200540874 16712pif.doc DET11〜DETI3的電壓> VREF =>高邏輯準位輸出 (DET01 〜DET03)。例如，資料 “〇”（減少）=> DETn 〜 DETI3的電壓< VREF =>低邏輯準位輸出（DET〇1〜 • DET03) 〇 圖5是一個按照本發明的一個實施例的示意性的信號 產生器333的示意圖。信號產生器333包括pM〇s電晶體 PM2、PM3和PM4用以接收位準檢測器331的相應輸出 DET01、DET02和DET03。電晶體pm2到PM4依次連 馨接到電晶體RTa、RTb和RTc。當大量資料(DATA)要編 為‘‘0，，時，ΝΜ0到NMn的大量電晶體關閉，使得在節點n 上呈現冋阻抗。DET01、DET02、DET03位於高邏輯準 位’ PM2、3、4關閉，電流流過所有的電阻(路徑a)， 接近於VSS或在一個低的電壓準位。 當少量資料(DATA)要編為“〇，，時，det〇卜2、3位於 低準位’ PM2、3、4開啟，電流流過電晶體和電阻尺丁及 RB(路徑B)，VDET接近升壓電壓vpp或在一個高的準位。 • 彳以看到，即使升壓電壓VPP保持恒定，電壓檢測 VDET也隨輸人資料DATAG到DATAn成關的變化。 圖6繪示檢測電路33的操作，以當DATA被程式化 為0的數量是“32”的時候為例。所有NM〇s電晶體 (ΝΜ0〜NM31)都被關閉。所有檢測信號(DEm、2、墙高 於VREF。所有位準檢測器的輪出信號都是高。所有pM〇s 電晶體(PM2、3、4)都關閉。電壓檢測VMT是它連接到 的電阻網路所給的最低的電璧。VDET的電壓可以表示為： 12 200540874 16712pif.doc {RB/(Rta + RTb + RTc + RT +RB)}* VPP = VDET (1) 如果VDET高於VREF，電荷幫浦停止。升壓電壓vpp 由下式得到： {RB/(Rta + RTb + RTc + RT +RB)}* VPP = VDET > = VREF 门、 然後， VPP = {(Rta + RTb + RTc + RT + RB)/RB} *VREF (3) 按照此例，當所有32個記憶胞要被程式化時，需要 大量的程式化電流和一個大的升壓電壓Vpp。此處，vpp 设為最南升壓準位。 圖7緣示檢測電路33的操作，以當DATA被程式化 為〇的數量是“24”的時候為例。DATA0到DATA31中的 24個為低準位，相應地，ΝΜ0到NM31中的24個NMOS 電晶體被關閉。ΝΜ0到NM31中的8個NMOS電晶體保 持開啟並在節點N產生相應的低阻抗。DETI1和DETI2 高於 VREF，DETI3 低於 VREF。DET01 和 DET02 為高 準位而DET03為低準位。只有一個pm〇S電晶體(PM4) 開啟。 VDET電壓為： {RB/(Rta + RTb + RT + RB)} * vpp = VDET (4) 如果VDET高於VREF，電荷幫浦停止。升壓電壓Vpp 13 200540874 16712pif.doc 設為： {RB/(RTa + RTb + RT + RB)} * VPP = VDET >= VREF (5) 然後， VPP = {(RTa + RTb + RT + RB)/RB} * VREF (6) 按照此例，當24個記憶胞要被程式化時，需要一個由 電阻網路提供的如方程式（6)所述的稍大但不是最大的升 壓電壓VPP。 圖8繪示檢測電路33的操作，以當DATA被程式化 為〇的數量是“16”的時候為例。16個NMOS電晶體被關 閉。16個NMOS電晶體開啟。DETI1高於VREF，DETI2 和DETI3低於VREF〇DET01為高準位而DET02和 DET03為低準位。只有一個PMOS電晶體(PM2)被關閉。 VDET電壓為： {RB/(Rta + RT + RB)} * VPP = VDE丁 m (8)The detection voltages DETI1, DETI2, and solar-body PM1 are generated at each node between Rw, and the transistor pM1 is connected to the bias voltage VDD. The resistance values of RY, RY, RX and Chinese braces are preferably 1K, 1K, 2K and 10K ohms. Through this transistor and resistor network, the series resistances RZ, RY, RX, and DETD represent the weights that vary according to the number of valid signals from DATA0 to DATAn. For example, the data DATA "0 ,, (increase), => NM0s (increase) => IDET (decrease in voltage> DETI1 ~ DETI3 (increase). The comparison circuit 43 includes an amplifier 431 and a level shifter. 433. It is amplified to 431 to receive the detection signal (DET1 to 3) and compare it with the reference voltage VREF and output it to the level shifter, 433, its towel, VPP input at the same time as the reference for appropriate conversion and output signals (DET01 ~ DET03). Data''〇 ,, (increase) 200540874 16712pif.doc Voltage of DET11 ~ DETI3> VREF => high logic level output (DET01 ~ DET03). For example, data "〇" (decrease) = > DETn ~ DETI3 The voltage < VREF = > low logic level output (DET〇1 ~ • DET03) 〇 FIG. 5 is a schematic diagram of a schematic signal generator 333 according to an embodiment of the present invention. The signal generator 333 includes pM 〇s transistors PM2, PM3, and PM4 are used to receive the corresponding outputs DET01, DET02, and DET03 of the level detector 331. Transistors pm2 to PM4 are connected to the transistors RTa, RTb, and RTc in sequence. When a large amount of data (DATA) To program as '' 0 ,, a large amount of electricity from NM0 to NMn The body is turned off, so that 冋 impedance appears on node n. DET01, DET02, and DET03 are at high logic levels' PM2, 3, and 4 are turned off, and current flows through all the resistors (path a), close to VSS or at a low voltage Level. When a small amount of data (DATA) is to be programmed as “〇,”, det〇 2 and 3 are at the low level. PM2, 3, and 4 are turned on, and current flows through the transistor and the resistance scale D and RB (path B ), VDET is close to the boosted voltage vpp or at a high level. • It can be seen that even if the boosted voltage VPP remains constant, the voltage detection VDET changes with the input data DATAG to DATAn. Figure 6 shows The operation of the detection circuit 33 is taken as an example when the number of DATA programmed to 0 is "32". All NMOS transistors (NM0 ~ NM31) are turned off. All detection signals (DEm, 2, wall height) To VREF. The turn-out signal of all level detectors is high. All pM0s transistors (PM2, 3, 4) are turned off. The voltage detection VMT is the lowest voltage given by the resistor network to which it is connected. The voltage of VDET can be expressed as: 12 200540874 16712pif.doc {RB / (Rta + RTb + RTc + RT + RB)} * VPP = VD ET (1) If VDET is higher than VREF, charge pumping stops. The boosted voltage vpp is obtained from the following formula: {RB / (Rta + RTb + RTc + RT + RB)} * VPP = VDET > = VREF gate, then VPP = {(Rta + RTb + RTc + RT + RB) / RB} * VREF (3) According to this example, when all 32 memory cells are to be programmed, a large amount of programmed current and a large boost voltage Vpp are required. Here, vpp is set to the southernmost boost level. Figure 7 shows the operation of the detection circuit 33, taking the case where the number of DATA programmed to 0 is "24" as an example. Twenty-four of DATA0 to DATA31 are low levels, and accordingly, 24 NMOS transistors in NM0 to NM31 are turned off. The eight NMOS transistors in NM0 to NM31 remain on and generate correspondingly low impedance at node N. DETI1 and DETI2 are above VREF, and DETI3 is below VREF. DET01 and DET02 are high and DET03 is low. Only one pMOS transistor (PM4) is on. The VDET voltage is: {RB / (Rta + RTb + RT + RB)} * vpp = VDET (4) If VDET is higher than VREF, the charge pumping stops. The boost voltage Vpp 13 200540874 16712pif.doc is set to: {RB / (RTa + RTb + RT + RB)} * VPP = VDET > = VREF (5) Then, VPP = {(RTa + RTb + RT + RB) / RB} * VREF (6) According to this example, when 24 memory cells are to be programmed, a slightly larger but not maximum boost voltage VPP as described in equation (6) provided by the resistor network is required. Fig. 8 illustrates the operation of the detection circuit 33, taking the case when the number of DATA programmed to 0 is "16" as an example. Sixteen NMOS transistors are turned off. Sixteen NMOS transistors are turned on. DETI1 is higher than VREF, DETI2 and DETI3 are lower than VREF. DET01 is the high level and DET02 and DET03 are the low level. Only one PMOS transistor (PM2) is turned off. The VDET voltage is: {RB / (Rta + RT + RB)} * VPP = VDE and m (8)
{RB/(RTa+ RT + RB)} * VPP = VDET VREF 如果VDET咼於VREF，電荷幫浦停止。升壓電壓vpp 設為： VPP = {(RTa+ RT + RB)/RB} * VREF (9) 當16個記憶胞要被程式化時，升壓電壓應該位於最高 和最低電壓準位的中間，如方程式(9)所示。 14 200540874 16712pif.doc 圖9繪示檢測電路33的操作，以當組八被程式化 為0的數量是“8”的時候為例。8個NM〇s電晶體被關閉。 24個NMOS電晶體開啟。所有的檢測信號2、3) 都低於VREF。位準檢測器331的所有輸出信號從det〇i 到DET03都為低準位。所有的pM〇s電晶體(pM2、3、 4)都開啟。 VDET的電壓為·· {RB/( RT + RB)} * VPP = VDET (1〇) (11) (12){RB / (RTa + RT + RB)} * VPP = VDET VREF If VDET is below VREF, the charge pumping stops. The boost voltage vpp is set to: VPP = {(RTa + RT + RB) / RB} * VREF (9) When 16 memory cells are to be programmed, the boost voltage should be in the middle of the highest and lowest voltage levels, such as Equation (9) is shown. 14 200540874 16712pif.doc Figure 9 shows the operation of the detection circuit 33, taking the case when the number of groups eight programmed to zero is "8" as an example. Eight NMOS transistors were turned off. 24 NMOS transistors are turned on. All detection signals 2, 3) are lower than VREF. All output signals of the level detector 331 are from low level to det0i to DET03. All pMos transistors (pM2, 3, 4) are turned on. The voltage of VDET is ... {RB / (RT + RB)} * VPP = VDET (1〇) (11) (12)
如果VDET高於VREF，電荷幫浦停止 {RB/(RT + RB)} * Vpp = VDET >= VREF 升壓電壓VPP設為：If VDET is higher than VREF, charge pumping stops {RB / (RT + RB)} * Vpp = VDET > = VREF Boost voltage VPP is set to:
VPP = {(RT + RB)/RB} * VREF 依照本發明的此實施例，升壓電壓vpp位於低電壓準 φ 位為8個記憶胞提供程式化電流。 圖10繪示了一個電壓VPP1的類比結果，其是習知結 構的升壓電壓；VSL1，習知結構的源極線電壓（可變）； VPP2，本發明電路提供的升壓電壓；以及VSL2，提供給 本發明電路的源極線電壓。由此可見在習知的升壓電路 中，升壓電壓VPP，保持幾乎恒定，與要程式化為“〇”資料 的數量無關，而當要程式化為“〇，，資料增加時，源極線電壓 VSL1減小。依照本發明，可以看到相反的情況，例如， 200540874 I67l2pif.doc 邛澄冤壓VPP2上升 當要程式化為“〇，，資料增加時 極線電壓VSL2保持不變。 雖然本發明已以較佳實施例揭露如 限定本發明，任何熟習此技 二並非用以 和範圍内，當可作此$ 二在不脫離本發明之精神 顯易技能的人更明 說明，其中，相同的元件’、、’配°所附圖式’作詳細 圖1緣示-個習二:為相同的參考號。 圖2、㈣-:;:=射•快閃記⑽ 圖3 *牙—彳㈣於提供升㈣㈣升壓電路。 發明的-個實例的升壓電路。 m C B . 的位準檢測器的示意方堍圖。 生器二::照本發明的—個實例的示意性的信號產 以當DATA被程式化 以當DATA被程式化 以當DATA被程式化 以當DATA被程式化 圖6繪示檢測電路33的操作 為〇的數量是“32”的時候為例。 圖7綠示檢測電路33的操作 為。的數量是“24”的時候為例： 圖8緣示檢測電路33 為〇的數量是“ 16”的時候為例。、乍 圖9繪示檢測電路％的 為〇的數量是“8”的時候為例。 200540874 16712pif.doc 圖10繪示了一個電壓VPP1的類比結果，其是習知結 構的升壓電壓；VSL1，習知結構的源極線電壓（可變）； VPP2，本發明電路提供的升壓電壓；以及VSL2，提供給 本發明電路的源極線電壓。 【主要元件符號說明】 200 :升壓電路 21 :升壓部 211 :振盪器 212 :反或閘 213 :幫浦電路 214 :運算放大器 23 :位準檢測器 300 :升壓電路 31 :幫浦控制電路 311 :振盪器 312 :反或閘 313 :幫浦電路 314 ·•運算放大器 33 :檢測電路 331 :位準檢測器 333 :信號產生器 41 :檢測電壓產生器 43 ·•比較電路 431 :放大器 17 200540874 16712pif.doc 433 :位準移位器VPP = {(RT + RB) / RB} * VREF According to this embodiment of the present invention, the boosted voltage vpp is located at a low voltage level φ to provide a programmed current for 8 memory cells. FIG. 10 shows an analog result of the voltage VPP1, which is the boost voltage of the conventional structure; VSL1, the source line voltage (variable) of the conventional structure; VPP2, the boost voltage provided by the circuit of the present invention; and VSL2 , The source line voltage provided to the circuit of the present invention. It can be seen that in the conventional booster circuit, the boosted voltage VPP remains almost constant, regardless of the amount of data to be programmed as "〇", and when the data is to be programmed as "〇," the source is increased. The line voltage VSL1 decreases. According to the present invention, the opposite situation can be seen, for example, 200540874 I67l2pif.doc 邛 Cheng unfair pressure VPP2 rises. When it is to be programmed as "0", the pole line voltage VSL2 remains unchanged when the data increases. Although the present invention has been disclosed in a preferred embodiment, such as limiting the present invention, any person familiar with this technique is not intended to be used within the scope. When this can be done, it will be more clearly explained by those who do not deviate from the spirit of the invention, Identical elements', 'matched drawings' are shown in detail in Figure 1-a second practice: the same reference number. Figure 2. ㈣-:;: = shoot • flash memory⑽ Figure 3 * 牙 — 彳 ㈣ provides a boost circuit. An invented boost circuit. m C B. Schematic square diagram of the level detector. Life generator 2 :: An exemplary signal according to an example of the present invention is generated when DATA is programmed to when DATA is programmed to when DATA is programmed to when DATA is programmed. FIG. 6 shows the detection circuit 33 An example is when the number of operations 0 is "32". FIG. 7 shows the operation of the detection circuit 33 in green. An example is when the number is "24": Fig. 8 shows an example when the number of detection circuits 33 is 0. At first, FIG. 9 shows a case where the number of detection circuit% is 0 as an example. 200540874 16712pif.doc Figure 10 shows an analog result of voltage VPP1, which is the boost voltage of the conventional structure; VSL1, the source line voltage (variable) of the conventional structure; VPP2, the boost provided by the circuit of the present invention Voltage; and VSL2, the source line voltage provided to the circuit of the present invention. [Description of main component symbols] 200: Booster circuit 21: Booster unit 211: Oscillator 212: Invertor gate 213: Pump circuit 214: Operational amplifier 23: Level detector 300: Booster circuit 31: Pump control Circuit 311: Oscillator 312: Invertor OR Gate 313: Pump circuit 314 · Operational amplifier 33: Detection circuit 331: Level detector 333: Signal generator 41: Detection voltage generator 43 · Comparison circuit 431: Amplifier 17 200540874 16712pif.doc 433: Level shifter
Ml、M2〜Mx :記憶胞 SL :源極線 BL :位元線 P卜P2〜Px :傳輸電晶體 I :程式化電流 VPP :升壓電壓 VREF ··參考電壓 VSL1、VSL2 :源極線電壓 VDET :升壓檢測信號 DATA卜DAT A2〜DAT An :輸入資料 OSC :振盪信號 DETH、2、3 ··檢測信號輸入 DETCM、2、3 :檢測信號輸出 ΝΜ0、NM1 〜NMx : NMOS 電晶體 PM1、PM2、3、4 : PMOS 電晶體 RW、RX、RY、RZ :電阻 VDD :工作電源正極(正） VSS :工作電源地極（負） 18M1, M2 ~ Mx: Memory cell SL: Source line BL: Bit line Pb P2 ~ Px: Transmission transistor I: Programmable current VPP: Boost voltage VREF. Reference voltage VSL1, VSL2: Source line voltage VDET: Boost detection signal DATA DAT A2 ~ DAT An: Input data OSC: Oscillation signal DETH, 2, 3 · Detection signal input DETCM, 2, 3: Detection signal output NM0, NM1 to NMx: NMOS transistor PM1, PM2, 3, 4: PMOS transistors RW, RX, RY, RZ: resistance VDD: working power positive (positive) VSS: working power ground (negative) 18