200529459 九、發明說明： 【發明所屬之技術領域】 本發明係關於薄膜半導體處理之領域，且尤其係關於處 理非矽薄膜。 【先前技術】 光電子、光電技術、電信及發光二極體（L£D)產業需要一 種基板技術，該技術允許其使用低成本、易獲得之基板（如 S1)來作為用於可以在其上製造裝置之光學材料薄膜的機械 支撐。一些明顯的優點經改良之機械強度及相對於表體光 電子材料之較高熱傳導性。 在先别技術中使用成長於表體Ge基板之上的HI-V族半 導體分層結構來產生效率超出3〇%之高效率三接點太陽能 電池。然而，此等對大眾而言極其昂貴而只限於太空應用， 此係由於Ge基板組成此成本之大部分。 光電子、光電、電信及發光二極體產業將會自採用一種 允許其使用低成本、易獲得之基板（如Si)來作為用於在其上 製造裝置之光電非矽材料薄膜的機械支撐之基板技術中受 |。些明顯優點係經改良之機械強度及相對於表體光電 子材料之較高熱傳導性。 【發明内容】 本發明係一種對在由光電子裝置基板與處理基板組成之 虛擬基板上外延地成長異質結構之方法的改良。該方法包 备開始將裝置基板結合於處理基板之步驟。裝置基板包含 適合於在此製造光電子裝置之材料，而處理基板包含適合 98027.doc 200529459 於提供機械支撐之便宜材料。Bond Berween裝置基板與處 理基板之間結合的機械強度得以改良。藉由諸如自裝置基 板上脫洛裝置薄膜來使裝置基板變薄而留下單晶薄膜。移 除自裝置基板上脫落之裝置薄膜的上部以為隨後之光電子 裝置製造提供較光滑且缺陷較少之傾斜表面。異質結構外 延地成長於光滑表面。 在所說明之實施例中，裝置基板為InP/Si，且在光滑表面 上外延地成長異質結構之步驟包含在光滑表面之上外延地 成長光致發光InP/InGaAs/InP雙異質結構。 移除自裝置基板上脫落之裝置薄膜之上部部分的步驟包 含使用損壞選擇性餘刻來化學性地研磨該上部部分，或機 械性地研磨該上部部分。 在裝置基板與處理基板呈現InP/Si介面之處，使用損壞選 擇性餘刻來化學性地研磨上部部分包含使用HCl : H3P〇4 : H2〇2以1:2:2或1:2:4之比例進行蝕刻之步驟。 在其它實施例中機械性地研磨上部部分之步驟包含使用 在次氯酸鈉溶液之膠體氧化矽研磨漿。 本發明亦可定義為一種對外延地成長於虛擬基板之上的 異質結構裝置層之改良。該改良包含形成虛擬基板之裝置 基板與處理基板。裝置基板結合於處理基板且裝置基板包 含一種適合光電子裝置製造之材料。處理基板包含適合提 供機械支撐之材料。Bond Berween裝置基板與處理基板之 間的結合之機械強度得以改良，且藉由諸如自裝置基板上 脫落裝置薄膜來使得裝置基板變薄而在虛擬基板上留下單 98027.doc 200529459 :曰^、°移除自裝置基板上脫落之裝置薄膜的上部部分而 二、光電子4置提供較光滑且缺陷較少之傾斜表面。昱質姓 構外=地成長於可製造光電子裝置之光滑表面。…、、〇 儘吕為了文法流暢已經或將要使用功能性說明來描述設 備及方法，但是應清楚地瞭解，除了在％ 下用公 ，式制說明的以外，本發明之巾請專利範圍不能理解為受 方法或步驟”之結構的任何限制，而應理解為與在司法條 例之均等物之下的中請專利範圍所提供之定義的意義與均 二等物一致，且在申請專利範圍在35 usc 112下用公式特別 說明之情形下，其應理解為與35 usc 112下之法定均等物 完全一致。藉由參看以下圖式可更好地實現本發明，其中 在該等圖式中相同元件由相同數字來表示。 【實施方式】 如在圖1之方塊圖中以圖表方式所說明的，虛擬晶圓結合 基板之製造104可需要兩個可能之步驟。該等步驟為如方塊 圖100所示之在製造功能性基板之前結合薄裝置膜與表體 基板，或如方塊圖102所示之在處理基板中製造功能性邏輯 裝置之後及/或在光電子裝置基板中製造功能性光電子基 板之後可將裝置薄膜轉移至處理基板。 此說明概括了許多光電子虛擬基板製造之實施例。吾人 首先概述一般所採用之技術及可使用虛擬基板產品之裝置 結構。其次，更多之材料處理步驟會以其在製造過程中出 現之順序加以描述。 處理與產品概況 98027.doc 200529459 為說明之目的’術語”裝置基板"10為將要自其上移除薄 膜12之光電子基板。在說明中，術語，，處理基板"14係定義 為指為用以為裝置基板12提供機械支撐之基板，即在薄膜 12移除之後的裝置基板之剩餘物。術語，，虛擬基板"16定義 為薄裝置膜12在處理基板14之上的已完成結構。 如圖2以圖表方式所丨，以下所討論之用於裝置基板^ 之可用材料可認為係所有與用於光電子、高增益裝置製造 之晶圓結合虛擬基板裝置薄膜材料相關之材料，該等材料 包括（但不限於广III/V族化合物半導體（即GaAs，inp，GaN 等）、π/νι族半導體（即CdTe等）、…族半導體（即用於GsAs 族成長之Ge)及具有光學重要性之鐵電氧化物（即，UNb〇4, BaTi〇4 等）。 ’ 處理基板14 一般為可大量獲得且具有所需電、機械及熱 特性之Si。因此，具有Si異質結構可根據本發明之教示及精 神由任何上文提及之材料製成。然而，亦可使用低成本絕 緣基板（即，玻璃，藍寶石等）來作為處理基板14。 用於製造該等虛擬基板16之一般處理包含以下步驟： 1) 裝置基板10與處理基板14可能需要進行預先結合處 理以允許薄膜12之移除（即，如圖3a中數字u以圖表方式 所示離子植入至裝置基板1〇中）。 2) 清潔裝置基板1 〇及/或使之處於鈍化狀態以便於結合 處理。 3) 如圖4a以圖表方式所示的，開始結合處理。 4) 增強結合’以改良裝置基板1〇與處理基板14之機械 98027.doc 200529459 強度。 5) 如圖4b所示，使裝置基板1〇變薄以在已完成之虛擬 基板16上留下單晶薄膜12以用於離子植入之基板。 6) 如圖5a與5b所示，在離子植入導致之層脫落情況 下產生歧置薄膜12之裝置基板10可藉由表面研磨進行 再次處理以允許再次使用基板來轉移另一裝置薄膜。 考慮到用於光電子虛擬基板丨6製造之概念，此等步驟將 會以其在上述一般處理中出現之順序列出。 處理步驟： 1)離子植入 如圖3a以圖表之方式所示，在結合處理之前，執行裝置 基板10之離子植入，以在基板中植入必要數量之氣體種類 以形成内部鈍化之表面及在退火時自基板脫落一層所必要 之内部壓力，圖3a說明了用離子光束u執行裝置基板1〇之 結合前離子植入；產生如圖3b所示之包含裝置薄膜12之經 改質之結構、用於薄膜轉移之離子損壞層13，及現在被稱 為處理基板14之大部分未受影響之裝置基板10之表體。 該處理一般使用矿或H+與He+之組合來執行。然而，可採 用其它氣體種類以產生有助於層脫落之基板内蝕刻處理。 對於一給定裝置基板材料而言，存在避免無定形之最低植 入度及所需植入溫度，即用於此處理中之最小所需劑量 關係。 a)H+植入__植入足夠劑量之Η+以在退火時允許膜脫 落’此劑量為下列因素之函數： 98027.doc 200529459 • 植入能量 • 植入溫度 •裝置基板材料 •膜脫落退火溫度 b) H+/He+共同植入__植入足夠劑量iH+/He+以在退火時 允許膜脫落。此方法之概念為Η起著使得内表面處於鈍化 狀態之化學作用，而化學性質呈惰性之116有效地移動至内 表面以提供壓力，且與Η相比每植入離子可產生更大損 壞’此改良了内表面密度。此必要劑量為下列因素之函數： • 植入能量 • 植入溫度 • H/He比率 •裝置基板材料 • 膜脫落退火溫度 c) 蝕刻劑植入一除H+植入之外或替代H+植入，可植入已 知之可蝕刻一給定材料的化學種類以產生易揮發性之内 部俘獲的化學種類，且導致在退火時之脫落。所選擇之化 學種類將為根據已知钱刻劑特性或實驗經驗所選之特定 材料。 2)表面鈍化 在植入之後及結合處理之前，需要對裝置基板1〇與處理 基板14之表面執行鈍化處理以允許疏水晶圓結合。該特定 化學處理需要特定裝置基板。此步驟之目的在於使得已完 成之虛擬基板中的裝置薄膜12與處理基板14之間產生緊密 98027.doc •11- 200529459 共價鍵，以允許歐姆、低阻介面電特性之可能。使得能夠 獲付此已完成裝置結構之必要步驟為藉由在惰性大氣中或 真空中低溫烘焙來消除所吸收之水。烘焙應達到一溫度， 使得在此溫度下水之蒸汽壓力遠遠高於周圍環境中之水的 部分壓力。 a. IV族純化—藉由使用稀釋hf餘刻處理來致使a族元 素半導體（特定言之為Ge)疏水。此留下氫化物為主之終止 表面。 b. III/V族鈍化--藉由使用特定組合物化學處理來致使 III/V族組合物半導體疏水，以留下用於結合之疏水鈍化之 表面。 c. II/VI族鈍化--藉由使用特定組合物化學處理來致使 II/VI族組合物半導體疏水，以留下用於結合之疏水鈍化之 表面。 d·鐵電氧化物--包含鐵電氧化物之應用與光電子材料 之應用相比在元素及組合物半導體方面具有本質區別。因 為此原因，處理基板材料將根據其電性及折射特性來選 擇，但通常無需對絕緣鐵電薄膜嘗試疏水晶圓結合。因 此，表面鈍化一般將集中於在裝置基板及處理基板1〇、14 上形成薄氧化物。 3)表面改質 如圖6a與6b所不，使用任意厚度之沉積表面改質層4〇來 改變基板10、14之間的物理交互性質為另一用以將此處理 延伸至更大範圍的光電子材料之有用技術。此可藉由三種 98027.doc -12- 200529459 方式中的一種來實現，其中x代表與所揭示之方法 任何類型的組合物。 4之 a•在裝置基板10上沉積材料X之層40使得X-處理材 結合成為可能。 ’ b·在處理基板14上沉積材料X之層40使得X-裝置材料 結合成為可能。 广 c•在兩個基板上沉積材料X之層40使得\_乂材料結合 成為可能。 ϋ 此技術藉由使用與所揭示過程相兼容或可修正之材料來 控制結合處理，使得大範圍之光電子材料的結合成為可 能’此時該材料僅稱為材料χ。圖6a與圖6b中說明了 一般性 處理。圖6a說明了已植入具有與處理基板14相同化學成分 之晶體或無定形薄膜40之經植入之裝置基板的改質。圖化 說明了使用此項技術展示裝置基板1〇之晶圓結合基板堆 疊、離子植入之損壞區域13、裝置薄膜12、沉積之結合調 節薄膜40、結合介面42及處理基板14。 此項技術之更特定應用為： d·外延Si結合層—此技術涉及在裝置基板材料上外延 地成長應變之Si薄膜。在此實施例中，材料χ為應變之薄 膜Si。藉由此成長可確保在裝置材料與Si外延層之間存 在緊密且超強度之結合。藉由外延層（未圖示）植入具有 應憂S i外延之裝置基板1 〇為晶圓結合及層脫落作好準 備。對於使用S i處理基板14之材料系統，此可允許使用 已建立之鈍化技術直接執行Si-Si晶圓結合處理。 98027.doc •13· 200529459 e·無定形Si結合層_•此技術包括在低溫條件下於裝置 基板10上沉積無定形Si之薄層，使得能夠使用典型μ表 面預備化學性質。在此實施例中物質X為無定形Si。此處 理可在裝置基板10之離子植入之前或之後執行。對於使 用Si處理基板14之物質系統，此可允許使用早已成熟之 純化技術之Si-Si晶圓結合處理。 4)顆粒移除 在表面純化之後，可能需要移除在裝置基板10與處理基 板14之結合表面上的殘留顆粒污染。如圖乜與仆所示，此 可藉由使用二氧化碳顆粒喷射執行清洗來有效地完成。圖 4a為在離子植入與初始結合之後的裝置基板丨〇與處理基板 14之堆疊之圖，其中說明了未損壞之表體裝置基板1〇、已 離子植入之損壞層13、裝置薄膜12、晶圓結合裝置/處理介 面42及處理基板14。圖仆為說明了在退火與層脫落之後的 晶圓結合虛擬基板16之圖，且其中說明了具有已離子植入 損壞表面區域13之未損壞表體裝置基板丨〇。亦說明了包含 裝置薄膜12之離子植入已損壞表面區域13之晶圓結合虛擬 基板、未損壞已轉移之裝置薄膜12、晶圓結合介面42及處 理基板14。將裝置基板1〇及/或處理基板14固持在高溫下， 且c〇2之經節流之氣體/顆粒喷射撞擊基板1〇與14表面，藉 此在組合物理與熱泳提昇效果之下移除顆粒。 在應用C〇2期間將基板保持在大於50。〇之溫度中，此技術 對於Si、Ge及InP已作出說明。 5 )面溫結合開始 98027.doc •14- 200529459 當結合不同材料時，一般在兩種材料之間存在熱膨脹不 相付係數’此導致視溫度而定之虛擬基板16中裝置薄膜12 之應變狀態，該應變狀態由此等式決定·· r(T)=J^Aa(r)dr 其中Δα(Τ)為作為溫度τ之函數的兩基板之熱膨脹係數之 差’且其中為零應變條件下之溫度，通常認為係結合開 始溫度。因此，藉由控制將兩基板接觸時之溫度，可以調 整所希望溫度下之應變狀態。此對於在高溫過程中改良基 板效能十分有利，或可調整裝置操作溫度應變以調整如能 帶隙、載流子遷移率之關鍵裝置特性。以下描述了作為 之正負號之函數的可達成之一般類型應變溫度-應變依靠 性0 △ a(T)= (Xhandle(T)- adevice(T) 在此應變之正值表明張力之下的薄膜，而應變之副值表 明壓力下之薄膜。 a.Aa⑺> 0 1·室溫下結合一在此情況下，薄膜12在較高處理溫度 下將處於張力下。此會導致虛擬基板16上異質外延中晶 格匹配之變化及凹基板彎曲之趨勢。 2·高溫結合一在此情況下，薄膜在結合溫度下將具有 零應變條件，使得伸張應變與凹晶圓彎曲在較高處理溫 度下會減小。同樣，在室溫下及可能地在裝置操作溫度 下，薄膜12將在壓縮應變之下導致凸晶圓彎曲。此可改 98027.doc -15- 200529459 變裝置操作且使得在物質參數之應變控制基礎上的新 穎裝置之設計成為可能。 b.Aa(T)<〇 1·室溫結合一在此情況下，薄膜12在高溫下將會處於 壓力之下。此將會導致虛擬基板上異質外延中晶格匹配 之變化及凸基板彎曲。 2 ·向溫結合―在此情況下，薄膜12在結合溫度下將具 有零應變條件，使得壓縮應變與凸晶圓彎曲在高處理溫 度下會減小。同樣，在室溫下及可能地在裝置操作溫度 下’薄膜I2將在壓縮應變之下導致凹晶圓彎曲。此可改 變裝置操作且使得在物質參數之應變控制基礎上的新 穎裝置之設計成為可能。所述絕大多數用於晶圓結合虛 擬基板16合適之材料屬於此類。 a. Ge/Si結合—圖7為說明Ge/Si結合中預測應變作 為基板在不同TG之值時結合之溫度的函數之曲線 圖。在高溫下薄膜壓力可藉由在更加高溫Tg初始結 合而減少。 b. InP/Si結合—圖8說明InP/si結合中預測應變作 為基板在不同TG之值時結合之溫度的函數之曲線 圖。同上，在高溫下薄膜壓力可藉由在更加高溫 初始結合而減少。 c. GaAs/Si—圖9說明GaAs/Si結合中預測應變作 為基板在不同T0之值時結合之溫度的函數之曲線 圖。再次同上，在高溫下薄膜壓力可藉由在更加高 98027.doc 200529459 溫T 0初始結合而減少。 6)不同溫度結合開始 對於一些所要之經調整的應變狀態，單一高溫結合溫度 將不能完成裝置之製造。同樣，對於具有同樣熱膨脹係數 之材料而言應變調整將較為困難。為了進一步使得在所要 之溫度下應變控製成為可能，可在不同溫度下在基板之間 開始結合。以此方式，可更加自由地控制熱-機械應變狀態 或手工地在已完成結構中建造。在此情況下，依靠溫度之 應變狀態由下式給出： Ητ>=(Δα(Γ)^·+γ。 其中值γ〇為在結合開始時建造在結合結構中的應變且其 由下式給出： r〇 = ta^v)dr+[y^)dr 在此表達式中 合開始之瞬間時 結合開始中基板 有在丁3與丁11之間 的實驗設備而定200529459 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to the field of thin film semiconductor processing, and particularly relates to the processing of non-silicon thin films. [Previous Technology] The optoelectronics, optoelectronics, telecommunications, and light emitting diode (L £ D) industries need a substrate technology that allows them to use low-cost, easily-available substrates (such as S1) for use on them. Mechanical support of the optical material film of the manufacturing device. Some obvious advantages are improved mechanical strength and higher thermal conductivity relative to surface optoelectronic materials. In the prior art, a HI-V group semiconductor layered structure grown on a surface Ge substrate was used to generate a high-efficiency three-contact solar cell with an efficiency exceeding 30%. However, these are extremely expensive for the general public and are limited to space applications. This is because Ge substrates make up most of this cost. The optoelectronics, optoelectronics, telecommunications, and light-emitting diode industries will adopt a substrate that allows them to use low-cost, readily available substrates (such as Si) as a mechanical support for the photovoltaic non-silicon material films used to fabricate devices thereon. Accepted by Technology. These obvious advantages are improved mechanical strength and higher thermal conductivity relative to the surface optoelectronic material. SUMMARY OF THE INVENTION The present invention is an improvement on a method for epitaxially growing a heterostructure on a virtual substrate composed of an optoelectronic device substrate and a processing substrate. The method includes a step of bonding a device substrate to a processing substrate. The device substrate contains materials suitable for manufacturing optoelectronic devices here, and the processing substrate contains inexpensive materials suitable for 98027.doc 200529459 to provide mechanical support. The mechanical strength of the bond between the Bond Berween device substrate and the processing substrate is improved. The device substrate is thinned by, for example, removing the device film from the device substrate to leave a single crystal film. The upper part of the device film peeled from the device substrate is removed to provide a smoother and less defective inclined surface for subsequent optoelectronic device manufacturing. Heterostructures grow epitaxially on smooth surfaces. In the illustrated embodiment, the device substrate is InP / Si and the step of epitaxially growing a heterostructure on a smooth surface includes epitaxially growing a photoluminescence InP / InGaAs / InP dual heterostructure on the smooth surface. The step of removing the upper portion of the device film peeled from the device substrate includes chemically grinding the upper portion using a damage selective leave, or mechanically grinding the upper portion. Where the device substrate and the processing substrate exhibit an InP / Si interface, the upper part is chemically polished using a damage selective remainder including the use of HCl: H3P〇4: H2〇2 at 1: 2: 2 or 1: 2: 4 The etching step is performed at a ratio. In other embodiments, the step of mechanically grinding the upper portion comprises using a colloidal silica abrasive slurry in a sodium hypochlorite solution. The present invention can also be defined as an improvement of a heterostructure device layer epitaxially grown on a virtual substrate. The improvement includes a device substrate and a processing substrate forming a dummy substrate. The device substrate is bonded to the processing substrate and the device substrate contains a material suitable for the manufacture of optoelectronic devices. The processing substrate contains a material suitable for providing mechanical support. The mechanical strength of the bond between the Bond Berween device substrate and the processing substrate is improved, and the device substrate is made thin by peeling off the device film from the device substrate, leaving a single on the virtual substrate. 98027.doc 200529459: ^, ° Remove the upper part of the device film peeled off the device substrate and the second photoelectron device provides a smooth and less inclined surface. Yu Zhixing Xie Xuan = Grows on a smooth surface that can manufacture optoelectronic devices. … ,, 〇 To complete the grammar fluently or will use functional descriptions to describe the equipment and methods, but it should be clearly understood that except for the use of public and formal descriptions under%, the scope of this invention's patents cannot be understood In order to be subject to any limitation of the structure of "methods or steps", it should be understood that the meaning provided by the scope of the patent claims under the equivalent of the judicial regulations is consistent with that of the equivalents, and the scope of the patent application is 35 In the case of a special description under the formula under usc 112, it should be understood to be completely consistent with the legal equivalent under 35 usc 112. The invention can be better realized by referring to the following drawings, in which the same elements are shown in the drawings It is represented by the same number. [Embodiment] As illustrated in the diagram in the block diagram of FIG. 1, the manufacturing of the virtual wafer bonded substrate 104 may require two possible steps. These steps are as shown in block diagram 100. It is shown that the thin device film is combined with the surface substrate before the functional substrate is manufactured, or after the functional logic device is manufactured in the processing substrate as shown in block diagram 102 and / or after After manufacturing a functional optoelectronic substrate in an electronic device substrate, the device film can be transferred to a processing substrate. This description summarizes many examples of optoelectronic virtual substrate manufacturing. I first outline the technology generally used and the device structure that can use virtual substrate products. Secondly, more material processing steps will be described in the order in which they appear in the manufacturing process. Process and Product Overview 98027.doc 200529459 For the purpose of illustration 'terminology' device substrates "10 for film to be removed therefrom 12 Of the optoelectronic substrate. In the description, the term, processing substrate " 14 is defined as a substrate for providing mechanical support for the device substrate 12, that is, the remainder of the device substrate after the film 12 is removed. The term "dummy substrate" is defined as a completed structure of the thin device film 12 on the processing substrate 14. As shown in the diagram in Figure 2, the available materials for device substrates discussed below can be considered to be all materials related to wafers used in optoelectronic, high-gain device manufacturing combined with virtual substrate device film materials. These materials Including (but not limited to broad III / V compound semiconductors (ie, GaAs, inp, GaN, etc.), π / νι semiconductors (ie, CdTe, etc.), ... semiconductors (ie, Ge for GsAs family growth), and optically important Ferroelectric oxides (ie, UNb〇4, BaTi〇4, etc.). 'The processing substrate 14 is generally Si that is available in large quantities and has the required electrical, mechanical, and thermal characteristics. Therefore, a Si heterostructure can be based on this The teachings and spirit of the invention are made of any of the materials mentioned above. However, low-cost insulating substrates (ie, glass, sapphire, etc.) can also be used as the processing substrate 14. General processing for manufacturing these virtual substrates 16 It includes the following steps: 1) The device substrate 10 and the processing substrate 14 may need to be pre-bonded to allow the film 12 to be removed (ie, as shown by the figure u in Figure 3a, the ions are implanted into the device). 1〇 of the substrate). 2) Clean the device substrate 10 and / or make it passivated to facilitate bonding. 3) As shown in Figure 4a, the combination process is started. 4) Enhanced bonding 'to improve the mechanical strength of the device substrate 10 and the processing substrate 14 98027.doc 200529459. 5) As shown in FIG. 4b, the device substrate 10 is thinned to leave a single crystal thin film 12 on the completed virtual substrate 16 for the substrate for ion implantation. 6) As shown in Figs. 5a and 5b, the device substrate 10 that generates the disparity film 12 in the case of layer shedding caused by ion implantation can be reprocessed by surface grinding to allow the substrate to be reused to transfer another device film. Considering the concept used for the manufacture of optoelectronic virtual substrates, these steps will be listed in the order in which they appear in the general processing described above. Processing steps: 1) Ion implantation As shown in a diagram in Figure 3a, before the bonding process, ion implantation of the device substrate 10 is performed to implant the necessary amount of gas species into the substrate to form an internally passivated surface and The internal pressure necessary to peel off a layer from the substrate during annealing. Figure 3a illustrates the use of an ion beam u to perform ion implantation before bonding of the device substrate 10; resulting in a modified structure including the device film 12 as shown in Figure 3b Ion-damaged layer 13 for thin film transfer, and the body of most of the unaffected device substrate 10, now referred to as the processing substrate 14 ,. This process is generally performed using ore or a combination of H + and He +. However, other types of gases may be used to produce an in-substrate etching process that facilitates layer peeling. For a given device substrate material, there is a minimum degree of implantation to avoid amorphousness and the required implantation temperature, i.e. the minimum required dose relationship for use in this process. a) H + implantation __ implant a sufficient dose of Η + to allow the film to fall off during annealing 'This dose is a function of the following factors: 98027.doc 200529459 • implantation energy • implantation temperature • device substrate material • film fall-off annealing Temperature b) H + / He + co-implantation __ Implant a sufficient dose of iH + / He + to allow the film to fall off during annealing. The concept of this method is that Η plays a chemical role in making the inner surface in a passivated state, and the chemically inert 116 effectively moves to the inner surface to provide pressure, and each ion implanted can cause greater damage than Η ' This improves the inner surface density. This necessary dose is a function of: • implantation energy • implantation temperature • H / He ratio • device substrate material • film peeling annealing temperature c) etchant implantation in addition to or instead of H + implantation, The chemical species known to etch a given material can be implanted to produce volatile internally trapped chemical species and cause peeling off during annealing. The type of chemical chosen will be a specific material selected based on known coinciding agent characteristics or experimental experience. 2) Surface passivation After implantation and before the bonding process, a passivation process needs to be performed on the surfaces of the device substrate 10 and the processing substrate 14 to allow the bonding of the hydrophobic wafer. This specific chemical treatment requires a specific device substrate. The purpose of this step is to make a tight bond between the device thin film 12 and the processing substrate 14 in the completed virtual substrate. 98027.doc • 11- 200529459 Covalent bond to allow the electrical characteristics of the ohmic, low-resistance interface. A necessary step to enable the payment of this completed device structure is to eliminate the absorbed water by low-temperature baking in an inert atmosphere or in a vacuum. Baking should reach a temperature at which the vapor pressure of water is much higher than the partial pressure of water in the surrounding environment. a. Group IV purification-Group A element semiconductors (specifically Ge) are rendered hydrophobic by post-treatment with diluted hf. This leaves the hydride-based termination surface. b. Group III / V passivation-Group III / V composition semiconductors are rendered hydrophobic by chemical treatment with a specific composition to leave a hydrophobic passivated surface for bonding. c. Group II / VI passivation-Group II / VI composition semiconductors are rendered hydrophobic by chemical treatment with a particular composition to leave a hydrophobic passivated surface for bonding. d. Ferroelectric oxides—Compared with the application of optoelectronic materials, the application of ferroelectric oxides has an essential difference in element and composition semiconductors. For this reason, the substrate material to be processed will be selected based on its electrical and refractive properties, but it is usually not necessary to attempt a hydrophobic wafer bonding of the insulating ferroelectric film. Therefore, surface passivation will generally focus on the formation of thin oxides on the device substrate and the processing substrates 10,14. 3) Surface modification As shown in Figures 6a and 6b, the use of a deposited surface modification layer 40 of any thickness to change the physical interaction between the substrates 10 and 14 is another way to extend this process to a larger range. Useful technologies for optoelectronic materials. This can be achieved in one of three ways 98027.doc -12-200529459, where x represents any type of composition with the disclosed method. 4a a • Depositing a layer 40 of material X on the device substrate 10 makes it possible to combine the X-treated materials. B. Depositing a layer 40 of material X on the processing substrate 14 makes it possible to combine the X-device materials. Wide c • Deposition of layer X of material X on two substrates makes it possible to combine materials. ϋ This technology controls the bonding process by using materials that are compatible or modifiable with the disclosed process, making the bonding of a wide range of optoelectronic materials possible. At this time, this material is simply called material χ. The general processing is illustrated in Figures 6a and 6b. FIG. 6a illustrates a modification of an implanted device substrate that has been implanted with a crystalline or amorphous film 40 having the same chemical composition as the processing substrate 14. FIG. The illustration illustrates the use of this technology to display the wafer-to-substrate stack of the device substrate 10, the damaged area 13 of the ion implantation, the device film 12, the deposited bonding adjustment film 40, the bonding interface 42, and the processing substrate 14. More specific applications of this technology are: d. Epitaxial Si bonding layer-This technology involves epitaxially growing a strained Si film on the device substrate material. In this embodiment, the material χ is a strained thin film Si. This growth ensures a tight and super-strong bond between the device material and the Si epitaxial layer. An epitaxial layer (not shown) is implanted into the device substrate 10 with an Si epitaxial layer to prepare for wafer bonding and layer peeling. For material systems that use Si to process substrate 14, this may allow Si-Si wafer bonding processes to be performed directly using established passivation techniques. 98027.doc • 13 · 200529459 e · Amorphous Si bonding layer_ • This technique involves depositing a thin layer of amorphous Si on the device substrate 10 at low temperature conditions, enabling the preparation of chemical properties using a typical μ surface. The substance X is amorphous Si in this embodiment. This process may be performed before or after the ion implantation of the device substrate 10. For a material system using Si to process the substrate 14, this may allow Si-Si wafer bonding processing using well-established purification techniques. 4) Particle removal After surface purification, it may be necessary to remove residual particle contamination on the bonding surface of the device substrate 10 and the processing substrate 14. As shown in Figures 乜 and 仆, this can be done efficiently by performing cleaning using carbon dioxide particle jets. Figure 4a is a stack of the device substrate and the processing substrate 14 after ion implantation and initial bonding, which illustrates the undamaged surface device substrate 10, the ion implanted damage layer 13, and the device film 12. , Wafer bonding device / processing interface 42 and processing substrate 14. The figure illustrates a wafer bonded virtual substrate 16 after annealing and layer peeling, and illustrates an undamaged surface device substrate with ion implanted damaged surface region 13. It also illustrates the wafer-bonded virtual substrate including the ion-implanted damaged surface region 13 of the device film 12, the device film 12, the wafer-bound interface 42 and the processing substrate 14 that have not been damaged and transferred. The device substrate 10 and / or the processing substrate 14 are held at a high temperature, and the throttled gas / particle spray of c02 hits the surfaces of the substrates 10 and 14, thereby moving under the combined effects of physical and thermal swimming enhancement. In addition to particles. The substrate was held at more than 50 during the application of CO2. At temperatures of 0 °, this technology has been described for Si, Ge, and InP. 5) Surface temperature bonding start 98027.doc • 14- 200529459 When combining different materials, there is generally a thermal expansion non-compliance coefficient between the two materials. This results in the strain state of the device film 12 in the virtual substrate 16 depending on the temperature, The strain state is determined by the equation: r (T) = J ^ Aa (r) dr where Δα (T) is the difference in thermal expansion coefficients of the two substrates as a function of temperature τ 'and where is the value under zero strain The temperature is generally considered to be the bonding start temperature. Therefore, by controlling the temperature when the two substrates are brought into contact, the strain state at a desired temperature can be adjusted. This is very beneficial for improving the performance of the substrate during high temperature, or it can adjust the operating temperature strain of the device to adjust key device characteristics such as band gap and carrier mobility. The following describes the general type of strain that can be achieved as a function of the sign. Temperature-strain dependence 0 △ a (T) = (Xhandle (T)-adevice (T) where the positive value of this strain indicates the film under tension The secondary value of strain indicates the film under pressure. A. Aa⑺> 0 1 · Combined at room temperature In this case, the film 12 will be under tension at a higher processing temperature. This will cause heterogeneity on the virtual substrate 16 Changes in lattice matching in epitaxy and the tendency of concave substrates to bend. 2. High temperature bonding-In this case, the film will have zero strain conditions at the bonding temperature, so that the tensile strain and bending of the concave wafer will be at higher processing temperatures. At the same time, at room temperature and possibly at the operating temperature of the device, the thin film 12 will cause the convex wafer to bend under compressive strain. This can be changed by 98027.doc -15- 200529459 changing the device operation and making the material parameters It is possible to design a novel device based on strain control. B. Aa (T) < 〇1 · Combined with room temperature In this case, the film 12 will be under pressure at high temperature. This will cause Heteroepitaxial Changes in grid matching and convex substrate bending. 2 · Warm bonding-In this case, film 12 will have zero strain conditions at the bonding temperature, so that compressive strain and convex wafer bending will decrease at high processing temperatures. Similarly At room temperature and possibly at the operating temperature of the device, the 'film I2 will cause bending of the concave wafer under compressive strain. This can change the device operation and enable the design of novel devices based on the strain control of physical parameters Most of the suitable materials for wafer bonding virtual substrate 16 belong to this category. A. Ge / Si bonding—Figure 7 illustrates the predicted strain in Ge / Si bonding as the temperature at which the substrate is bonded at different TG values. A graph of the function of the film. At high temperatures, the film pressure can be reduced by the initial bonding of Tg at higher temperatures. B. InP / Si bonding—Figure 8 illustrates the predicted strain in the InP / si bonding as the substrate is combined at different TG values. Graph of temperature as a function of the same. As above, the film pressure at high temperatures can be reduced by initial bonding at higher temperatures. C. GaAs / Si—Figure 9 illustrates the predicted strain in GaAs / Si bonding as a substrate during A graph of the function of the temperature combined with the value of T0. Again, as above, the film pressure at high temperature can be reduced by the initial combination of T0 at a higher 98027.doc 200529459 temperature. 6) The combination of different temperatures starts for some desired After adjusting the strain state, a single high temperature bonding temperature will not complete the manufacture of the device. Similarly, strain adjustment will be difficult for materials with the same thermal expansion coefficient. To further enable strain control at the desired temperature, bonding between substrates can be started at different temperatures. In this way, the thermo-mechanical strain state can be controlled more freely or manually constructed in a completed structure. In this case, the strain state depending on the temperature is given by: Ητ > = (Δα (Γ) ^ · + γ. Where γ0 is the strain built in the bonding structure at the beginning of bonding and it is given by Given: r〇 = ta ^ v) dr + [y ^) dr in this expression at the moment of the beginning of the combination, depending on the experimental equipment on the substrate between Ding 3 and Ding 11
’ L與分別為裝置基板1〇與裝置14在結 的溫度。溫度心為有效結合開始溫度。在 之不同溫度使該因數报難決定。r一定具 之一值，且其將視使用於虛擬基板製造中 ，且可藉由實驗來決定。該内建應變接近 r〇And L are the junction temperatures of the device substrate 10 and the device 14, respectively. The temperature center is the effective binding start temperature. The different temperatures make this factor difficult to determine. r must have a value, and it will be used in the manufacture of virtual substrates, and can be determined through experiments. The built-in strain is close to r〇
對於具有十分類 板14。在下列情形 似線性膨脹係數之裝置基板10與處理基 下可執行在不同晶圓溫度下之結合。 98027.doc 17 200529459 a. Aa(T)>〇： 1·7>7ν_該等條#使得導致基板薄膜纟於高溫下增加 之壓力的正應變組分之添加成為可能。 ▲ 該等條件下使得減少高溫伸張應變之負應 變組分之添加成為可能，但產生了更低溫度壓縮應變。 b. Aa(T)<〇： L心>7V-該等條件使得導致基板薄膜處於高溫下已 減少壓縮應變級別的正應變組分之添加成為可能。 2.7VCTV-該等條件下使得改良高溫伸張應變之負應 變組分的添加成為可能，但產生了已減少之低溫伸張應 變。 、 c. Aa(T) = 〇： 1.7^>八—不受溫度影響之伸張應變可按此方式應用 於裝置薄膜之上。 2.心<5—不受溫度影響之壓縮應變可添加至裝置薄 膜。 < 7)在高壓下退火以增強結合並脫落裝置層 在凌置基板10與處理基板14結合後，需要使用熱循環以 改良結合強度並活化離子植入層轉移處理。在壓力下執行 该循環，結合之表體基板堆疊中可容納熱_機械應變。另 外，結合藉由經改良之基板_基板接觸而得以加強。使用多 壓力-溫度步驟或甚至不斷變化之壓力_溫度曲線的結合處 理可用以優化在此處理中之壓力有效性。 具體言之，在脫落之前的低溫條件下，可使用較高壓力 98027.doc -18- 200529459 以保證更好基板接觸，但該等壓力在高溫下會抑制脫落。 在退火至高溫之前藉由將壓力減少至更低水平，脫落將不 受限制。 a·可變壓力循環—一可能性實施例為獨立使用變化之 壓力與溫度以優化結合處理。在低溫下，應用高壓以加 強結合。接著在高溫下減少壓力以避免裝置基板中對層 脫落之抑制。在圖10之圖表中說明了具有代表性之處 理，其中說明了作為在結合退火處理中時間之函數的晶 圓結合溫度-壓力曲線。 b·單一壓力循環—為了退火之持久，亦可藉由施加單 軸負載至結合對以改進結合處理。在此處理中該負載應 足夠小而無需對起泡進行抑制。 8)装置層之改造 在離子植入導致之層轉移處理中裝置薄膜之轉移後，裝 置薄膜12之近表面區域粗糙且佈滿瑕疵。如圖與丨比所 示忒層應控制性地移除以留下對製造光電子裝置之隨後 處理有用之表面。視裝置層1〇而定，此可以藉由以下完成： a_濕式化學研磨—此方法使用依靠裝置薄膜之蝕刻來 控制性地移除由離子植入導致之晶圓結合虛擬基板16上 的知壞層1 3，而同時使經轉移之層的表面光滑。對於特 殊材料之餘刻列出如下·· l.Ge/Si ι·ΗΡ:Η2〇2··Η2〇“此蝕刻可在不同溫度下以不同稀 釋比例x:y:z執行。 98027.doc -19- 200529459 ii. HF:HN〇3:C2H4〇2:H2〇__此蝕刻可在不同溫度下 以不同稀釋比例w:x:y:z執行。 iii. H2〇2.H2〇—此餘刻可在不同溫度下以不同稀釋 比例y:z執行。 2.InP/Si i.HC1:H3P〇4:H202—已成功使用以 1:2:2與 1:2:4之 比例的此蝕刻溶液。出〇2充當氧化劑而^^丨與出⑽斗 之混合物蝕刻該氧化物。氧化與隨後之蝕刻的組合產 生光滑表面且移除了植入損壞。圖l2a為說明對於用 _ 於不同蝕刻稀釋液的作為時間之函數的兩個表面之 粗糙度。圖12b與12c說明了分別暴露在1:2:2與1:2:4 蝕刻稀釋液之下的外延地成長於InP/Si虛擬基板上 之InP/InGaAs/InP雙異質結構之光致發光強度光 譜。已化學性處理之結構的發光強度之相對改良指示 該處理產生了用於外延生長之經改良之表面。在圖 12b中與外延準備inp基板相對應之光譜取自生長於 鲁 由表體基板製造者提供之外延準備InP基板之上的雙 異質結構。該45秒錶體InP光譜取自生長於已暴露至 化學處理達45秒之外延準備inp基板之上的雙異質結 構。該45秒InP/Si光譜取自生長於在層轉移之後被化 學處理達45秒之晶圓結合虛擬inp/si樣本之上的雙 異質結構。該已轉移之InP/Si光譜取自生長於層脫落 卜For boards with tenth category. The combination of the device substrate 10 with a linear expansion coefficient and a processing base at different wafer temperatures can be performed in the following cases. 98027.doc 17 200529459 a. Aa (T) > 〇: 1 · 7 > 7ν_ These conditions # make it possible to add a positive strain component which causes the substrate film to be subjected to an increased pressure at high temperatures. ▲ Under these conditions, the addition of negative strain components that reduce the high-temperature tensile strain becomes possible, but a lower temperature compressive strain is produced. b. Aa (T) < 〇: L center > 7V-These conditions make it possible to add a normal strain component that has reduced the compressive strain level at a high temperature of the substrate film. 2.7 VCTV-These conditions make it possible to add negative strain components that improve high temperature tensile strain, but produce reduced low temperature tensile strain. , C. Aa (T) = 〇: 1.7 ^ > VIII-The tensile strain that is not affected by temperature can be applied to the device film in this way. 2. Heart < 5—Compressive strain that is not affected by temperature can be added to the device film. < 7) Annealing under high pressure to enhance bonding and peel off the device layer After bonding the substrate 10 and the processing substrate 14, thermal cycling is required to improve the bonding strength and activate the ion implantation layer transfer process. Performing this cycle under pressure, the combined watch body substrate stack can accommodate thermal_mechanical strain. In addition, the bond is strengthened through improved substrate-to-substrate contact. Combining processes using multiple pressure-temperature steps or even changing pressure-temperature curves can be used to optimize the pressure effectiveness in this process. Specifically, under the low temperature conditions before falling off, a higher pressure 98027.doc -18- 200529459 can be used to ensure better substrate contact, but these pressures will inhibit falling off at high temperatures. By reducing the pressure to a lower level before annealing to high temperatures, shedding will not be restricted. a. Variable pressure cycling-One possible embodiment is to use varying pressure and temperature independently to optimize the combined process. At low temperatures, high pressure is applied to strengthen the bond. The pressure is then reduced at high temperatures to avoid suppression of layer shedding in the device substrate. Representative features are illustrated in the graph of Fig. 10, which illustrates the crystal circle bonding temperature-pressure curve as a function of time in the bonding annealing process. b · Single pressure cycle—For the duration of the annealing, a uniaxial load can also be applied to the bonding pair to improve the bonding process. The load should be small enough in this process to suppress foaming. 8) Modification of the device layer After the device film is transferred in the layer transfer process caused by ion implantation, the near surface area of the device film 12 is rough and full of defects. As shown in the figure, the layer should be removed in a controlled manner to leave a surface useful for subsequent processing of the optoelectronic device. Depending on the device layer 10, this can be accomplished by: a_ wet chemical polishing-this method uses the etching of the device film to controlively remove the wafer-bonded virtual substrate 16 caused by ion implantation Know the bad layer 1 3 while making the surface of the transferred layer smooth. For the special materials, the following is listed as follows: l. Ge / Si · ΗΡ: Η2〇2 ·· Η2〇 "This etching can be performed at different temperatures at different dilution ratios x: y: z. 98027.doc- 19- 200529459 ii. HF: HN〇3: C2H4〇2: H2〇__ This etching can be performed at different temperatures with different dilution ratios w: x: y: z. Iii. H2〇2.H2〇—the rest The etching can be performed at different temperatures at different dilution ratios y: z. 2.InP / Si i.HC1: H3P〇4: H202—This etching has been successfully used at a ratio of 1: 2: 2 to 1: 2: 4 The solution. Out 02 acts as an oxidant and the mixture of ^^ 丨 and out of the bucket etches the oxide. The combination of oxidation and subsequent etching produces a smooth surface and removes implant damage. Figure 12a is an illustration of the different etching used for _ Roughness of the two surfaces of the diluent as a function of time. Figures 12b and 12c illustrate the epitaxial growth of the InP / Si virtual substrate exposed to the 1: 2: 2 and 1: 2: 4 etching diluents, respectively. The photoluminescence intensity spectrum of the above InP / InGaAs / InP double heterostructure. The relative improvement of the luminous intensity of the chemically treated structure indicates that the treatment produced a modified for epitaxial growth. In Figure 12b, the spectrum corresponding to the epitaxially prepared inp substrate is taken from the double heterostructure grown on the epitaxially prepared InP substrate provided by the watch body substrate manufacturer. The 45-second table InP spectrum is taken from the grown on Double heterostructures that have been exposed to chemical processing for 45 seconds on epitaxial prepared NP substrates. The 45-second InP / Si spectrum is taken from a wafer grown on a wafer that has been chemically processed for 45 seconds after layer transfer combined with a virtual inp / si sample Double heterostructure on top. The transferred InP / Si spectrum is taken from the layer growth
之後但未經表面處理之InP/Si之晶圓結合結構之上 的雙異質結構。在圖12c中，該對應於外延準備InP 98027.doc -20- 200529459 之光譜取自生長於由表體基板製造者提供之外延準 備InP基板之上的雙異質結構。該6〇秒錶體ιηρ光譜取 自生長於已暴露至化學處理達6〇秒之外延準備Inp基 板之上的雙異質結構。該60秒InP/Si光譜取自生長於 在層移除之後被化學處理達60秒之晶圓結合虛擬 InP/Si樣本之上的雙異質結構。 b·化學與物理研磨―此使用化學與機械研磨漿以蝕 刻植入4貝壞且留下光滑表面。 l.Ge/Si-·可使用KOH化學中之膠態二氧化矽研磨漿 來研磨基板。 2.InP/Si —展示了可用次氣酸鈉溶液中之膠態二氧化 石夕研磨漿來使該等虛擬基板材料之表面光滑。圖12(1展 示了外延地生長於經過化學與機械研磨處理後之 InP/Si基板之上的InP/InGaAs/InP雙異質結構之光致發 光光譜。在圖12d中，與外延準備InP相對應之光譜取 自生長於由表體基板製造者提供之外延準備InP基板 之上的雙異質結構。該5分鐘錶體InP光譜取自生長於 已暴露至研磨處理達5分鐘之外延準備InP基板之上的 雙異質結構。該30秒InP/Si光譜取自生長於在層轉移之 後被研磨處理達3〇秒之晶圓結合虛擬InP/Si樣本之上 的雙異質結構。經研磨處理之虛擬基板光致發光強度 相對於未經研磨之基板的改良指示用於外延生長的經 改良之表面。在此處理中表面粗糙度減少至大約3 nm rms ’其之原子力顯微鏡掃描圖係如圖12e所示。 98027.doc -21 - 200529459 均質外延平滑化―甚至在化學蝕刻移除植入損壞但並未 留下用於隨後之異質外延的最佳光滑平面之情形下，已展 示經㈣之樣本上的裝置薄膜材料之均質外延，以減少表 面粗糙度。此可作為在晶圓結合虛擬基板上生長異質外延 結構之第一步驟。 9) 外延之異質結構生長 已完成之虛擬基板16係為了作為由異質外延執行之光電 子裝置生長之摸板。藉由仔細的裝置層改質，大範圍的光 電子裝置之外延成為可能。該結構之—代表性影像展示於 圖13a與13b中。圖13a為展示了包含裝置薄膜、晶圓結合 介面42及處理基板14之已完成的晶圓結合虛擬基板16之 圖。圖13b為展示了具有於裝置薄膜12上製造之外延生長之 裝置50的晶圓結合虛擬基板16之圖。 10) 應變補償層 在裝置製造中藉由如M0CVD、擴散、植入及微影技術之 標準處理在轉移層内或上建構晶圓結合基板中之一潛在挑 戰係由於在轉移層中熱膨脹產生之應變之存在所導致之晶 圓f曲之可此性。如丨4圖所示，減少此影響之一實用方法 為在處理基板14之背部表面沉積一應變補償層。圖14為一 不思性地展不了生長於包含裝置薄膜12、結合介面42、處 理基板14及沉積於基板背部表面之應變補償層18的晶圓結 合虛擬基板之上的光電子結構50之圖。 將藉由在裝置層1〇轉移至處理基板14之前或之後，在處 理基板14之背部表面沉積薄膜18來實施此概念。該應變補 98027.doc •22- 200529459 償層18必須具有如裝置薄膜⑵目對於處理基板相同之^正 負號。零、f曲狀態並非零應變狀態，但在不存在其它使基 板灸形之驅動力之條件下，裝置薄膜12之應變能量與應變 補償層之應變能量完全匹配。可選擇材料與沉積技術以最 小化與此處理步驟相關聯之製造成本。用基板直徑、薄膜 應茇及4膜厚度來増加與薄膜12相關聯之應變能量。可藉 :選擇應變補償層18、沉積溫度及厚度以調整零彎曲處‘ Μ度下列為對於一些材料系統如何執行應變補償之實例： •最簡單之情形為在Si處理基板之背部表面沉 積Ge之薄膜。 -,,^ uay ΛΆ llir , ^ aj 使用Ge薄膜’此係由於以薄膜之沉積較為簡易。 心械1 一同1nP/Si之情況相似，Ge可產生良好應變 補償層。 d ·其匕材料—對於以 負號合適之條件下，易 補償層。 上所提及之所有系統，在Δα之正 沉積之低成本材料為適合之應變A double heterostructure on top of the wafer bonding structure of InP / Si afterwards but without surface treatment. In Fig. 12c, the spectrum corresponding to the epitaxial preparation InP 98027.doc -20-200529459 is taken from the double heterostructure grown on the epitaxial preparation InP substrate provided by the body substrate manufacturer. The 60-second watch body ηρ spectrum was taken from a double heterostructure grown on an Inp substrate prepared by epitaxial preparation that has been exposed to chemical treatment for 60 seconds. The 60-second InP / Si spectrum was taken from a double heterostructure grown on a wafer combined with a virtual InP / Si sample that was chemically processed for 60 seconds after layer removal. b. Chemical and Physical Abrasives-This uses chemical and mechanical abrasive slurries to etch the implants and leave a smooth surface. l.Ge/Si-·The colloidal silica polishing slurry in KOH chemistry can be used to polish the substrate. 2.InP / Si—shows that colloidal silica slurry in sodium hypogas solution can be used to smooth the surface of these virtual substrate materials. Figure 12 (1) shows the photoluminescence spectrum of the InP / InGaAs / InP double heterostructure epitaxially grown on the InP / Si substrate after chemical and mechanical polishing. In Figure 12d, it corresponds to the epitaxial preparation of InP The spectrum was taken from the double heterostructure grown on the epitaxially prepared InP substrate provided by the watch body substrate manufacturer. The 5-minute InPumence of the watch body was taken from the InP substrate grown on the epitaxially prepared InP substrate that had been exposed to grinding for 5 minutes. Double heterostructure on the substrate. The 30-second InP / Si spectrum is taken from a double heterostructure grown on a wafer combined with a virtual InP / Si sample that has been polished for 30 seconds after layer transfer. The polished virtual substrate The improvement of the photoluminescence intensity relative to the unpolished substrate indicates an improved surface for epitaxial growth. In this process, the surface roughness is reduced to about 3 nm rms. Its atomic force microscope scan is shown in Figure 12e 98027.doc -21-200529459 Homogeneous epitaxial smoothing-Warp crickets have been shown even when implant damage is removed by chemical etching without leaving the best smooth plane for subsequent heteroepitaxial epitaxy The homogeneous epitaxy of the device thin film material on the sample to reduce the surface roughness. This can be used as the first step to grow a heteroepitaxial structure on a wafer-bonded virtual substrate. 9) The virtual substrate 16 with the epitaxial heterostructure growth completed As a model for the growth of optoelectronic devices implemented by heteroepitaxial. With careful device layer modification, a wide range of optoelectronic device epitaxy becomes possible. A representative image of this structure is shown in Figures 13a and 13b. FIG. 13a is a diagram showing a completed wafer-bonded virtual substrate 16 including a device film, a wafer-bonded interface 42 and a processing substrate 14. FIG. FIG. 13b is a diagram showing a wafer combined with a dummy substrate 16 having a device 50 for making epitaxial growth on a device film 12. FIG. 10) One of the potential challenges in strain-compensating layers in device manufacturing by standard processes such as MOCVD, diffusion, implantation, and lithography in constructing wafer-bound substrates in or on transfer layers is due to thermal expansion in the transfer layer. The feasibility of wafer f-curves caused by the presence of strain. As shown in FIG. 4, one practical method to reduce this effect is to deposit a strain compensation layer on the back surface of the processing substrate 14. FIG. 14 is a diagram showing an optoelectronic structure 50 grown on a wafer bonded virtual substrate including a device film 12, a bonding interface 42, a processing substrate 14, and a strain compensation layer 18 deposited on a back surface of the substrate. This concept will be implemented by depositing a thin film 18 on the back surface of the processing substrate 14 before or after the device layer 10 is transferred to the processing substrate 14. The strain compensation 98027.doc • 22-200529459 compensation layer 18 must have the same sign as the device film for the processed substrate. The zero and f-curved states are not zero-strain states, but in the absence of other driving forces that shape the substrate, the strain energy of the device film 12 and the strain energy of the strain compensation layer completely match. Materials and deposition techniques can be selected to minimize the manufacturing costs associated with this process step. The substrate diameter, film thickness, and film thickness are used to increase the strain energy associated with the film 12. Can be borrowed: select the strain compensation layer 18, the deposition temperature and thickness to adjust the zero bend. The following is an example of how to perform strain compensation for some material systems: • The simplest case is the deposition of Ge on the back surface of the Si-treated substrate film. -,, ^ uay ΛΆ llir, ^ aj Using Ge thin film ’is because it is easier to deposit by thin film. Heart Device 1 is similar to 1nP / Si, and Ge can produce a good strain compensation layer. d. Its dagger material-for the conditions suitable for negative sign, easy to compensate layer. For all the systems mentioned above, the low-cost materials deposited on the Δα are suitable strains.
在不背離本發明精神盥範 ^ ± , 厂、乾圍之情況下，此項技術之一般 技術者可作出諸多變化與 απ _ 、乜汉因此，應瞭解，列出所說 明之貫施例僅為了實例却昍夕β μ 專财… 的且其不應作為已由申請 寻利粑圍界定之本發明 之限制。舉例而言，儘管事實上申 請專利範圍要素在以下特 太菸明七权s, 特疋之組合尹列出，但是應明瞭， 本發明包括更少、更多或 π 素之其它組合，該等元素 揭不於上文中或甚至未在該組合中初次申請。 98027.doc -23- 200529459 在該說明書中用以描述本發明及其各種實 彙義之詞義理解，還應包括於本說明書 此構„材料之特殊定義或超出—般定義之詞義㈣圍。因 右^素在本說明書文中可理解為包括一個以上詞 ▲:八在申明專利範圍中之用途應理解為屬於由說明書 及5司彙本身支持之所有可能意思。 q彙及以下申凊專利豸圍内<元素之定義在本說 明書中界定為不僅包括逐字陳述之元素之組合’亦包括所 有均等結構、材料或用於以大體上相同之方法執行大體上 $同之力月b以獲侍大體上相同之結果的行為。因此，在此 意義上，應理解兩個或兩個以上元素之均等替代物可替代 以：申請專利範圍中之任何一元素，或一單一元素可替代 申清專利範圍中的兩個或兩個以上元素。儘管如上所述該 等元素作為特定之組合且甚至為初次如此中請，但是應明 瞭，所主張之組合中一或多個元素在一些情形中可自組合 中排除’且所主張之組合可指子組合或子組合之變體。。 此項技術之-般技術者對於所主張之標的物之非實質性 的變化（現在已知的或以後所做出的）應清楚理解為均等地 屬於該中請專利範圍之内。因此，此項技術之—般技術者 已知或以後知道之明顯替代物應定義為所定義之元素内。 因此申請專利範圍應理解為包括以上特別所說明及描述 的、在概念上均等的、明顯可替代的及本質上倂入本發明 之本質觀點的一切。 【圖式簡單說明】 98027.doc -24- 200529459 圖1為說明兩種可選擇之虛擬基板製造策略之方塊圖。 圖2為說明根據本發明用於虛擬基板之薄膜種族的方塊 圖。 圖3 A及3B為分別說明了在裝置基板中之離子植入與所 得結構之圖。 圖4 A及4B為分別說明了在離子植入與初始結合之後的 裝置與處理基板之堆疊及在退火與層脫落之後的晶圓結合 虛擬基板之圖。 圖5A及5B為分別說明了包含近表面離子植入損壞層及 未損壞之表體的後層轉移裝置基板之圖，其中藉由自表體 裝置基板蝕刻移除損壞允許處理得以重複。 圖6A及6B未分別說明了使用任一相同化學成分之薄膜 作為處理基板對已植入之裝置基板的表面改質及使用此技 術展示裝置基板的晶圓結合基板堆疊之圖。 圖7為作為Ge/Si晶圓結合虛擬基板之應變狀態之溫度之 一函數的曲線圖。 圖8為作為InP/Si晶圓結合虛擬基板之應變狀態之溫度之 一函數曲線圖。 圖9為作為GaAs/Si晶圓結合虛擬基板之應變狀態之溫度 之一函數的曲線圖。 圖10為作為用於結合退火處理中之時間之一函數的晶圓 結合溫度-壓力曲線之曲線圖。 圖11A及11B未分別說明了退火及層脫落之後的晶圓結 合虛擬基板及在損壞移除#刻、研磨及外延之成長於裝置 98027.doc -25- 200529459 薄膜上之後的晶圓結合虛擬基板的圖。 圖12A為經轉移之InP裝置薄膜的rms表面粗糙度作為 HC1:H3P04:H202按1:2:2、1:2:4比例及1:2:5比例稀釋之蝕刻 化學所使用時間之一函數的曲線圖。 圖12B為成長於通常為外延成長所提供之用於準備外延 (Epi-ready)InP 的比例為 1:2:2 之 HCl:H3P〇4:H2〇2 濕化學蚀 刻劑中蝕刻之InP/Si異質結構上的InP/InGaAs/InP雙異質結 構之光致發光強度（PL)之曲線圖，且表體InP研磨45秒， InP/Si研磨45秒且作為經轉移之InP，其為在層轉移之後與 任何表面修正之前的晶圓結合結構。InP/Si虛擬基板之研磨 所具有之提高了的機械強度說明了所處理之結構的經改良 之表面質量。 圖12C為成長於通常為外延成長所提供之用於準備外延 InP的比例為1:2:4之HC1:H3P04:H202濕化學钱刻劑中儀刻 之InP/Si異質結構上的InP/InGaAs/InP雙異質結構之光致發 光強度（PL)之曲線圖，且表體InP研磨60粆’而InP/Si研磨 6〇秒。InP/Si虛擬基板之研磨所具有之提高了的機械強度說 明了所處理之結構的經改良之表面質量。 圖12D為成長於使用通常為外延成長所提供之用於準備 外延InP之次氣酸鈉化學機械研磨方法處理之InP/Sl異質結 構之上的InP/InGaAs/InP雙異質結構之光致發光強度（PL) 之曲線圖，且表體InP研磨5分鐘，而InP/Si研磨30秒。1nP/Si 虚擬基板之研磨所具有之提高了的機械強度說明了所處理 之結構的經改良之表面質量。 98027.doc -26- 200529459 圖12E為在30秒化學機械研磨方 ^ 处里之後的經轉移之Without departing from the spirit of the present invention, the ordinary technicians of this technology can make many changes and απ _, 乜 Han, therefore, it should be understood that the illustrated embodiments are listed only For the sake of example, the β μ exclusive wealth ... and it should not be taken as a limitation of the present invention which has been defined by the application for profit. For example, despite the fact that the elements of the scope of patent application are listed in the following combination of special taiyanming seven rights s, special 尹, it should be clear that the present invention includes other combinations of fewer, more or π elements, such as Elements are not disclosed above or even not initially applied in this combination. 98027.doc -23- 200529459 In this description, the meanings used to describe the present invention and its various practical meanings should also be included in the structure of this specification. „Special definitions of materials or beyond the general definitions. ^ Prime can be understood to include more than one word in the text of this specification ▲: The use in the scope of the declared patent should be understood to belong to all possible meanings supported by the description and the 5 company Hui itself. Q Hui and the following patents within the scope < The definition of element is defined in this specification to include not only a combination of elements stated literally 'but also all equal structures, materials or used to perform substantially the same force month b in a substantially the same way in order to be served The same result as above. Therefore, in this sense, it should be understood that an equivalent substitute of two or more elements can be replaced by: any element in the scope of patent application, or a single element can replace the scope of patent application Two or more of the elements. Although these elements are used as a specific combination and even for the first time as mentioned above, it should be clear that the claimed group One or more elements in a combination may be excluded from the combination in some cases, and the claimed combination may refer to a sub-combination or a variant of a sub-combination ... Substantive changes (now known or made in the future) should be clearly understood as equally falling within the scope of the patent. Therefore, this technology is an obvious substitute known to the ordinary skilled person or later known. Should be defined as within the defined elements. Therefore, the scope of patent application should be understood to include everything specifically illustrated and described above, conceptually equivalent, obviously substitutable, and essentially incorporating the essence of the present invention. [Figure] Simple description of the formula] 98027.doc -24- 200529459 Figure 1 is a block diagram illustrating two alternative virtual substrate manufacturing strategies. Figure 2 is a block diagram illustrating the thin film race for virtual substrates according to the present invention. Figure 3 A and 3B is a diagram illustrating the ion implantation in the device substrate and the resulting structure, respectively. Figures 4A and 4B illustrate the stacking of the device and the processing substrate after ion implantation and initial bonding, respectively. Figures of a wafer combined with a virtual substrate after annealing and layer peeling. Figures 5A and 5B are diagrams illustrating a back-layer transfer device substrate including a near-surface ion implantation damaged layer and an undamaged surface, respectively. The device substrate can be removed by etching to remove the damage. Figures 6A and 6B do not illustrate the modification of the surface of an implanted device substrate using a thin film of any of the same chemical composition as a processing substrate and the use of this technology to demonstrate the device substrate. Figure of wafer-to-substrate stacking. Figure 7 is a graph as a function of the temperature of the strain state of a Ge / Si wafer and a virtual substrate. A function graph. Figure 9 is a graph as a function of the temperature of the strain state of a GaAs / Si wafer combined with a virtual substrate. Fig. 10 is a graph of a wafer bonding temperature-pressure curve as a function of time used in the bonding annealing process. Figures 11A and 11B do not illustrate the wafer-bonded virtual substrate after annealing and layer peeling, and the wafer-bonded virtual substrate after damage removal #etching, grinding, and epitaxial growth on the device 98027.doc -25- 200529459, respectively. Illustration. FIG. 12A is a function of the rms surface roughness of the transferred InP device film as a function of the etching time used for HC1: H3P04: H202 diluted 1: 2: 2, 1: 2: 4 ratio and 1: 2: 5 ratio Graph. FIG. 12B is an InP / Si etched in a wet chemical etchant prepared at a ratio of 1: 2: 2 of HCl: H3P〇4: H2〇2, which is provided for epitaxial (Epi-ready) InP, which is usually provided for epitaxial growth A graph of the photoluminescence intensity (PL) of the InP / InGaAs / InP double heterostructure on the heterostructure, and the surface of the InP is ground for 45 seconds, InP / Si is ground for 45 seconds, and it is transferred as InP, which is transfer in layer The structure is then bonded to the wafer before any surface modification. The improved mechanical strength of the grinding of InP / Si virtual substrates illustrates the improved surface quality of the structure being processed. FIG. 12C is an InP / InGaAs grown on an InP / Si heterostructure in an HC1: H3P04: H202 wet chemical coining agent that is usually provided for epitaxial growth to prepare an epitaxial InP ratio of 1: 2: 4. A graph of the photoluminescence intensity (PL) of the / InP dual heterostructure, and the surface of the body InP was polished 60 粆 'and InP / Si was polished 60 seconds. The improved mechanical strength of the grinding of the InP / Si virtual substrate illustrates the improved surface quality of the structure being processed. FIG. 12D is a photoluminescence intensity of an InP / InGaAs / InP double heterostructure grown on an InP / Sl heterostructure treated with a sodium hypogas chemical chemical mechanical polishing method for preparing epitaxial InP, which is usually provided for epitaxial growth. (PL), and the surface of InP was ground for 5 minutes, and InP / Si was ground for 30 seconds. The improved mechanical strength of the 1nP / Si virtual substrate grinding demonstrates the improved surface quality of the structure being processed. 98027.doc -26- 200529459 Fig. 12E shows the transfer time after 30 seconds of CMP.
InP基板薄膜表面之原子力微影圖片。 圖13A與圖13B為分別說明了已完成之晶圓結合虛擬基 板與具有在裝置薄膜之上製造之外延成長裝置的晶圓結^ 虛擬基板之圖。 圖14展現了成長於晶圓結合虛擬基板之上的光電子結 構，該虛擬基板包含裝置薄膜、結合介面、處理基板及沉 積於基板背面之應變補償層。 藉由參看以上對較佳實施例之詳盡描述可更好地理解本 發明及其各種實施例，該等實施例作為本發明申請專利範 圍中所定義之說明性實例而呈現。應明瞭，如申請專利範 圍中所定義之本發明可以比以上所描述之說明性實施例更 為廣泛。 【主要元件符號說明】 10 裝置基板 11 離子光束 12 薄膜 13 損壞區域/層 14 處理基板 16 虛擬基板 40 沉積表面改質層 42 晶圓結合介面 50 光電子結構 98027.docAtomic force lithography image of InP substrate film surface. FIG. 13A and FIG. 13B are diagrams illustrating a completed wafer bonding virtual substrate and a wafer junction ^ virtual substrate having an epitaxial growth device fabricated on a device film, respectively. Figure 14 shows an optoelectronic structure grown on a wafer-bonded virtual substrate, which includes a device film, a bonding interface, a processing substrate, and a strain compensation layer deposited on the back of the substrate. The invention and its various embodiments can be better understood by referring to the above detailed description of the preferred embodiments, which are presented as illustrative examples as defined in the patentable scope of the invention. It should be understood that the invention as defined in the scope of the patent application may be more extensive than the illustrative embodiments described above. [Description of Symbols of Main Components] 10 Device substrate 11 Ion beam 12 Thin film 13 Damaged area / layer 14 Process substrate 16 Virtual substrate 40 Deposited surface modification layer 42 Wafer bonding interface 50 Optoelectronic structure 98027.doc