TW200524255A - Semiconductor circuit device and data processing system - Google Patents

Semiconductor circuit device and data processing system Download PDF

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Publication number
TW200524255A
TW200524255A TW93128423A TW93128423A TW200524255A TW 200524255 A TW200524255 A TW 200524255A TW 93128423 A TW93128423 A TW 93128423A TW 93128423 A TW93128423 A TW 93128423A TW 200524255 A TW200524255 A TW 200524255A
Authority
TW
Taiwan
Prior art keywords
circuit
capacitor
patent application
item
scope
Prior art date
Application number
TW93128423A
Other languages
Chinese (zh)
Other versions
TWI360283B (en
Inventor
Masashi Horiguchi
Mitsuru Hiraki
Original Assignee
Renesas Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Tech Corp filed Critical Renesas Tech Corp
Publication of TW200524255A publication Critical patent/TW200524255A/en
Application granted granted Critical
Publication of TWI360283B publication Critical patent/TWI360283B/en

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Dc-Dc Converters (AREA)
  • Electronic Switches (AREA)

Abstract

The purpose of this invention is to suppress the noise of power supply. The power supply noise arises during a step-down action at the time of turning on power supply. The resolving method is that: It comprises a step-down unit with a switched capacitor type step-down circuit, and a series regulator type step-down circuit. In addition, the stepped-down voltage output terminals of the step-down circuits are connected in common. By means of this way, it makes parallel driving of both, selective driving of either, or sequential driving of the two. In the aforementioned sequential driving, even though the switched capacitor type step-down circuit is driven after driving the series regulator type step-down circuit first to supply a stepped-down voltage to loads, the switched capacitor type step-down circuit will need only to be compensated for a discharge due to the loads. The peak of a charge current for capacitors can be kept low. When operation of the switched capacitor type step-down circuit is started, no large rush current arises. Eventually, it restrains the noise of power supply.

Description

200524255 ⑴ 九、發明說明 【發明所屬之技術領域】 本發明是有關具有降壓電路的半導體電路裝置，特 別是具有開關電容式降壓電路的半導體電路裝置，更具 有開關電容式降壓電路和串聯穩壓式降壓電路的半導體 電路裝置，例如有關適用於攜帶通信終端裝置的微電腦 和系統、晶載的半導電路裝置（系統LSI )有效的技術。 【先前技術】 半導體電路裝置的晶載降壓電路是屬於串聯穩壓式 降壓電路。串聯穩壓式降壓電路是藉由電晶體的ON電 阻而使電壓下降的緣故，電壓下降部分會造成原有電力 損失。另一方面，電力轉換效率比串聯式電路佳的方式 ’是開關電容式降壓電路（日本專利文獻2的第1圖） 。此乃由於作爲外置零件需要感應器，故在實裝面積及 成本這點上會有問題。不需要感應器且電力轉換效率佳 的降壓電路則有開關電容式降壓電路（日本專利文獻2 的第9圖）。而於日本專利文獻1的第1圖是表示在串 聯穩壓式降壓電路串接開關電容式降壓電路N ,將由串 聯穩壓式降壓電路所輸出的降壓電壓，以接受開關電容 式降壓電路而更爲降壓的電路。 【專利文獻1】日本特開2002— 325431號公報 【專利文獻2】日本特開2 〇 〇 2 - 3 6 9 5 5 2號公報 200524255 (2) 【發明內容】 【發明欲解決的課題】 本發明人乃對作爲適用於攜帶機器LSI等的降壓電 路，不需要感應器且電力轉換效率佳開關電容式降壓電 路。檢討的結果對於開關電容式降壓電路本發明人發現 特別會有所謂電源上升時電源電流（湧入電流）變大的 問題。亦即在開關電容式降壓電路中，由於電力效率良 好故希望極力縮小切換的ON電阻的設計。可是那樣做 的話，電容器充電時會流入較大的電源電流。特別是電 源上升時，由於電容器是從完全未充電的狀態開始，故 會有所謂流入較大的湧入電流的問題。藉此會產生電源 雜訊、EMI (electro magnetic interference:電磁波干擾 )等。 本發明之目的乃在於提供一能減低隨著降壓動作的 電力消耗的半導體電路裝置。 本發明之另一目的乃在於提供一能隨著電源投入時 的降壓動作而產生電源雜訊的抑制或緩和的半導體電路 裝置。 本發明之另一目的乃在於有助於電池驅動的資料處 理系統的低消耗電力。 本發明之前述及其它目的和創新特徵乃由本s羊細說 明書的記述及所附圖面即可明白。 [用以解決課題的手段】 >5- 200524255 (3) 若簡單地說明於本案中所揭示的發明中之代表性發 明的槪要乃如下記所述。 〔半導體電路裝置乃具有令外部電源電壓降壓而 生成降壓電壓的降壓部’前述降壓部乃具有開關電容式 降壓電路和串聯穩壓式降壓電路，各個降壓電路的降壓 電壓輸出端子則被共通連接°雙方的降K電路的降壓電 壓輸出端子則被共通連接，藉此就能進行雙方並列驅動 、選擇驅動、依序驅動。前述依序驅動是先驅動串聯穩 壓式降壓電路並負荷地供給降壓電壓之後’就算驅動開 關電容式降壓電路，開關電容式降壓電路只要補充經由 負荷產生的放電部分即可’對電容器的充電電流峰値很 小。當開始開關電容式降壓電路之動作時，不會產生很 大的湧入電流，能抑制雜訊的產生。 半導體電路裝置乃具有外部電源電壓投入時，先開 始前述串聯穩壓式降壓電路的降壓動作，然後開始開關 電容式降壓電路之降壓動作的起動控制電路，藉此當開 始開關電容式降壓電路之動作時，不會產生很大的湧入 電流，保證能抑制雜訊的產生。 前述起動控制電路乃於開始開關電容式降壓電路之 降壓動作後，停止串聯穩壓式降壓電路的降壓動作爲佳 。光是在開關電容式降壓電路補足電流供給能力的情形 ’就有助、於低消耗電力。 若考慮到以不會藉由開關電容式降壓電路的電容器 連接切換將切換雜訊的頻譜集中（分散）於特定頻率， -6- 200524255 (4) 則開關電容式降壓電路乃於充放電循環中使得切換電容 器連接狀態的計時隨機化爲佳。例如開關電容式降壓電 路乃具有欲使得前述切換計時隨機化的亂數產生電路， 且使用所產生的亂數來選擇切換電容器連接狀態的計時 。總之，電源投入時使串聯穩壓式降壓電路承擔降壓動 作，藉此就能減低峰値電流，電源上升後只要在開關電 容式電路補充經由負荷產生的放電部分即可的緣故，其 峰値電流小，藉由複數分割開關電容式降壓電路，並錯 開各個相位而驅動，電源電流的峰値變更小。 前述開關電容式降壓電路的電容器也可對應於外置 電容器或是晶載電容器的任一個。晶載電容器能以Μ 0 S 電晶體的:閘極絕緣膜、層間絕緣膜等作爲介電質使用所 構成。 本發明的具體性形態，爲具備將降壓電壓供給到半 導體積體電路外部的外部電源供給端子。藉此就能將降 壓電壓運用到其它半導體電路裝置的動作電源。而前述 開關電容式降壓電路乃爲能將降壓電壓可變控制的應用 於老化。 〔2〕半導體電路裝置、具有使得形成在半導體晶片 的外部電源電壓降壓而生成降壓電壓的降壓部、前述降 壓部乃具有開關電容式降壓電路，且將構成開關電容式 降壓電路的開關陣列分割爲複數個而離間配置，在各個 開關陣列個別連接固有的開關電容，平滑電容就會共通 連接。藉由使平滑電容共通化，就能抑制零件數增加。 -7- 200524255 (5) 本發明的具體性形態，爲具有於充放電循環中控制 利用前述開關陣的平滑電容和開關電容之連接切換計時 的降壓控制電路、前述降壓控制電路是針對複數個開關 陣列錯開切換計時而加以控制。有利於使得利用開關陣 列之電容連接切換的開關的.高頻雜訊頻譜分散。總之， 令開關電容式降壓電路的開關陣列做複數分割並錯開各 個相位而驅動，藉此電源電流的峰値變小。 更前述降壓控制電路是對每個開關陣列生成錯開相 位的時脈信號，基於所生成的各個時脈信號而令前述連 接切換計時於每個開關陣列隨機化。以開關陣列單位亦 有利用於令前述高頻雜訊頻譜分散，高頻雜訊的峰値變 得更小。前述降壓控制電路乃具有欲令前述切換計時隨 機化的亂數產生電路，使用所產生的亂數來選擇前述連 接切換計時。 本發明所希望的形態，爲前述開關陣列是被配置在 前述半導體晶片的外部連接電極形成區域的近傍。能縮 短與外置電容元件的距離，可減低因配線電阻和寄生電 容的影響。控制複數個前述開關陣列之開關動作的降壓 控制電路則被複數個前述開關陣列共通化，並自前述開 關陣列被離間配置。降壓控制電路的共通化則有助於降 壓部的小型化。 本發明所希望的形態，爲與前述降壓控制電路一同 具有串聯穩壓式降壓電路，前述開關電容式降壓電路和 串聯穩壓式降壓電路的降壓電壓輸出端子則被共通連接 200524255 (6) 。若先驅動串聯穩壓式降壓電路並負荷地供給降壓電壓 後，驅動開關電容式降壓電路，開關電容式降壓電路只 要補充經由負荷所產生的放電部分即可，對電容器的充 電電流峰値很小。當開始開關電容式降壓電路之動作時 ，就不會產生很大的湧入電流，能抑制雜訊的產生。 藉由具有外部電源電壓投入時，先開始前述串聯穩 壓式降壓電路的降壓動作，然後開始開關電容式降壓電 路之降壓動作的起動控制電路，當開始開關電容式降壓 電路之動作時，就不會產生很大的湧入電流，保證能抑 制雜訊的產生。 〔3〕在電池驅動的資料處理系統採用上述半_ 胃 路裝置。、可減低EMI ’有助於移動體通信終端和攜帶通 信終端之通信性能的提昇。 【發明效果】 若簡單地說明藉由在本案中所揭示的發明ψ自勺Θ ^ 性發明所得到的效果即如下記所述。 亦可能減低隨著降壓動作的電力消耗。 能抑制或緩和隨著電源投入時的降壓動作& _ & $ ^而產生電 源雜訊。 可有助於被電池驅動的資料處理系統的彳氏_ & _二 ^伯耗電力 【實施方式】 -9- 200524255 (7) 【用以實施發明的最佳形態】 第1圖是表示有關本發明的半導體積體電路配備在 晶片內的降壓電路之其中一例。於同圖所示的降壓電路 乃由：基準電壓產生電路1、串聯穩壓式降壓電路（也簡 記爲串.聯穩壓器）2、位準感測器3、開關控制電路4及 開關陣列5_ 1〜5_ η所形成。位準感測器3、開關控制 電路4及開關陣列5_ 1〜5_ η乃與圖示省略的外置電容 器一同構成開關電容式降壓電路6。 前述基準電壓產生電路1會產生不受溫度和電源電 壓影響的安定基準電壓 VREF。例如，利用取出能帶間隙 形電路、MO S電晶體的臨限電壓差的電路等所實現。串 " 聯穩壓器2是藉由電’晶體的ON電阻進行電壓下降而形 成降壓電壓VDD。降壓電壓VDD的位準是被控制成與基 準電壓VREF —致。 前述位準感測器3是比較降壓電壓V D D和基準電壓 而形成開關電容式降壓電路的降壓動作停止信號S Τ Ο P B 。開關控制電路4是基於時脈信號CLK而成生控制開關 陣列5 __ 1〜5 — η的複數條開關控制信號S。開關陣列5 _1〜5_η是屬於欲構成一邊逐次變更接受輸入電壓的電 容器的連接狀態一邊進行電容分割的切換電容器的切換 電路。VDDCPi乃爲輸入電壓端子、VDDi乃爲輸出電壓 端子、V S S i乃爲電路的接地端子、C P i和C M i乃爲欲外 置電容器的端子（ι=〗〜η)。輸出端子VDD1〜VDDn是 在晶片內被連接。接地端子VSS1〜VSSn也是同樣。 -10- 200524255 (8) 開關電容式降壓電路6的輸出和串聯穩壓器2的輸 出是共通連接。即，開關電容式降壓電路6的輸出端子 VDD1〜VDDn是共通連接於串聯穩壓器2的輸出端子。200524255 九 IX. Description of the invention [Technical field to which the invention belongs] The present invention relates to a semiconductor circuit device having a step-down circuit, especially a semiconductor circuit device having a switched-capacitor type step-down circuit. The semiconductor circuit device of the stabilized voltage step-down circuit is, for example, an effective technology related to a microcomputer and a system for carrying a communication terminal device, and a semiconductor semiconductor device (system LSI) mounted on a crystal. [Prior art] A crystal-loaded step-down circuit of a semiconductor circuit device is a series-regulated step-down circuit. The series stabilized voltage step-down circuit uses the ON resistance of the transistor to reduce the voltage. The voltage drop will cause the original power loss. On the other hand, a method that has better power conversion efficiency than a series circuit is a switched-capacitor step-down circuit (Figure 1 of Japanese Patent Document 2). This is because a sensor is required as an external part, so there are problems in terms of mounting area and cost. A step-down circuit with excellent power conversion efficiency that does not require an inductor includes a switched-capacitor step-down circuit (Figure 9 of Japanese Patent Document 2). The first figure in Japanese Patent Document 1 shows that a series-connected step-down circuit is connected in series with a switched-capacitor step-down circuit N, and the step-down voltage output by the series-stabilized step-down circuit is accepted by the switched-capacitor type. Step-down circuit and more step-down circuit. [Patent Document 1] Japanese Patent Laid-Open No. 2002-325431 [Patent Document 2] Japanese Patent Laid-Open No. 2000- 3 6 9 5 5 2 200524255 (2) [Summary of the Invention] [Questions to be Solved by the Invention] This The inventors have proposed a switched-capacitor step-down circuit which is a step-down circuit suitable for portable device LSIs, which does not require an inductor and has a high power conversion efficiency. As a result of the review, the inventors have found that there is a problem in particular that the power supply current (inrush current) becomes larger when the power supply rises. That is, in a switched-capacitor buck circuit, since the power efficiency is good, it is desirable to minimize the design of the ON resistor that is switched. However, if this is done, a large supply current will flow when the capacitor is charged. In particular, when the power supply rises, since the capacitor starts from a completely uncharged state, there is a problem of a so-called large inrush current. This will generate power noise, EMI (electro magnetic interference) and so on. An object of the present invention is to provide a semiconductor circuit device capable of reducing power consumption due to a voltage reduction operation. Another object of the present invention is to provide a semiconductor circuit device capable of suppressing or alleviating power noise caused by a step-down operation when the power is turned on. Another object of the present invention is to contribute to low power consumption of battery-driven data processing systems. The foregoing and other objects and innovative features of the present invention can be understood from the description of the sheep's detailed description and the attached drawings. [Means for solving the problem] > 5- 200524255 (3) The summary of representative inventions among the inventions disclosed in the present case is briefly described as follows. [Semiconductor circuit devices have a step-down section that generates a step-down voltage by stepping down the external power supply voltage. The aforementioned step-down section has a switched-capacitor step-down circuit and a series regulated step-down circuit. The voltage output terminals are connected in common. The step-down voltage output terminals of the K-lowering circuits on both sides are connected in common, thereby enabling parallel driving, selective driving, and sequential driving of both sides. The aforementioned sequential driving is to first drive the series voltage-stabilizing step-down circuit and supply the step-down voltage under load. 'Even if the switched-capacitor step-down circuit is driven, the switched-capacitor step-down circuit only needs to supplement the discharge generated by the load.' The capacitor charging current peak 値 is small. When starting the operation of the switched capacitor buck circuit, no large inrush current will be generated, which can suppress the generation of noise. The semiconductor circuit device is a start-up control circuit that starts the step-down operation of the series voltage-stabilizing step-down circuit first when the external power supply voltage is turned on, and then starts the step-down operation of the switched-capacitor type step-down circuit. During the operation of the step-down circuit, no large inrush current will be generated to ensure that noise can be suppressed. The aforementioned start-up control circuit preferably stops the step-down operation of the series-regulated step-down circuit after starting the step-down operation of the switched-capacitor type step-down circuit. It is helpful to reduce the power consumption simply by supplementing the current supply capability of the switched-capacitor buck circuit. If it is considered that the switching of the capacitor's frequency spectrum will not be concentrated (dispersed) at a specific frequency by switching the capacitor connection of the switched capacitor buck circuit, -6- 200524255 (4), the switched capacitor buck circuit is charged and discharged. It is better to randomize the timing of the switching capacitor connection state in the loop. For example, a switched capacitor type step-down circuit has a random number generating circuit for randomizing the aforementioned switching timing, and uses the generated random number to select the timing of the switching capacitor connection state. In short, when the power is turned on, the series regulated step-down circuit will perform the step-down action, which can reduce the peak current. After the power supply rises, it is only necessary to supplement the switched capacitor circuit with the discharge part generated by the load.値 The current is small. It is driven by staggered switching capacitor-type step-down circuit and shifted from each phase. The peak current change of the power supply current is small. The capacitor of the aforementioned switched capacitor type buck circuit may correspond to either an external capacitor or a crystal capacitor. The wafer capacitor can be composed of M 0 S transistor: gate insulating film, interlayer insulating film, etc. as the dielectric. A specific aspect of the present invention includes an external power supply terminal for supplying a step-down voltage to the outside of the semiconductor volume circuit. This makes it possible to apply the step-down voltage to an operating power source for other semiconductor circuit devices. The aforementioned switched-capacitor step-down circuit is capable of applying variable control of the step-down voltage to aging. [2] A semiconductor circuit device having a step-down section that generates a step-down voltage by stepping down an external power supply voltage formed on a semiconductor wafer. The step-down section has a switched capacitor type step-down circuit and will constitute a switched capacitor type step-down The switch array of the circuit is divided into a plurality and separated from each other, and the inherent switch capacitors are individually connected to each switch array, and the smoothing capacitors are connected in common. By making the smoothing capacitors common, an increase in the number of parts can be suppressed. -7- 200524255 (5) A specific form of the present invention is a step-down control circuit for controlling the timing of switching between the smoothing capacitor and the switching capacitor connection during the charge and discharge cycle. The step-down control circuit is directed to a complex number. The switch arrays are controlled by staggering the switching timing. It is beneficial to disperse the high-frequency noise spectrum of the switches connected by the capacitive connection of the switch array. In short, the switch array of the switched-capacitor buck circuit is plurally divided and driven out of phase, thereby reducing the peak current of the power supply current. Furthermore, the aforementioned step-down control circuit generates a clock signal with phase shift for each switch array, and randomizes the connection switching timing for each switch array based on the generated clock signals. The use of a switch array unit is also advantageous for dispersing the aforementioned high frequency noise spectrum, and the peak chirp of the high frequency noise becomes smaller. The step-down control circuit is a random number generating circuit for randomizing the switching timing, and uses the generated random number to select the connection switching timing. In a desirable aspect of the present invention, the switch array is disposed near an external connection electrode forming region of the semiconductor wafer. It can shorten the distance from external capacitors and reduce the influence of wiring resistance and parasitic capacitance. The step-down control circuit that controls the switching operations of the plurality of switch arrays is commoned by the plurality of switch arrays, and is separated from the switch arrays. The common use of the step-down control circuit contributes to the miniaturization of the step-down section. A desirable form of the present invention is to have a series regulated step-down circuit together with the aforementioned step-down control circuit, and the step-down voltage output terminals of the aforementioned switched capacitor-type step-down circuit and series-regulated step-down circuit are connected in common 200524255 (6). If the series regulator step-down circuit is driven first and the step-down voltage is supplied in a load, then the switched-capacitor step-down circuit is driven. The switched-capacitor step-down circuit only needs to supplement the discharge part generated by the load, and the charging current of the capacitor The peaks are small. When starting the operation of the switched capacitor buck circuit, a large inrush current will not be generated, and the generation of noise can be suppressed. When an external power supply voltage is input, the step-down operation of the series-regulated step-down circuit is started first, and then the start-up control circuit of the step-down operation of the switched-capacitor step-down circuit is started. During the operation, no large inrush current will be generated to ensure that noise can be suppressed. [3] The battery-driven data processing system uses the aforementioned semi-gastric device. It can reduce EMI, and it helps to improve the communication performance of mobile communication terminals and portable communication terminals. [Effects of the Invention] The effects obtained by the invention ψ from the invention disclosed in the present case are briefly described as follows. It is also possible to reduce the power consumption with the step-down operation. It can suppress or mitigate power noise caused by the step-down action & _ & $ ^ when the power is turned on.彳 amp & _2 ^ Power consumption that can contribute to battery-driven data processing systems [Embodiment] -9- 200524255 (7) [Best Mode for Carrying Out the Invention] FIG. 1 shows the relationship between The semiconductor integrated circuit of the present invention is one example of a step-down circuit provided in a wafer. The step-down circuit shown in the same figure is composed of: a reference voltage generating circuit 1, a series regulated step-down circuit (also simply referred to as a string. Cascade regulator) 2, a level sensor 3, a switch control circuit 4 and The switch arrays 5_ 1 to 5_ η are formed. The level sensor 3, the switch control circuit 4, and the switch arrays 5_1 to 5_η constitute a switched capacitor type buck circuit 6 together with an external capacitor (not shown). The aforementioned reference voltage generating circuit 1 generates a stable reference voltage VREF which is not affected by temperature and power supply voltage. For example, it can be realized by taking out a band gap circuit, a circuit that has a threshold voltage difference of a MOS transistor, and the like. The string " voltage regulator 2 is formed by the voltage drop of the ON resistor of the crystal to form a step-down voltage VDD. The level of the step-down voltage VDD is controlled to match the reference voltage VREF. The level sensor 3 compares the step-down voltage V D D with a reference voltage to form a step-down operation stop signal S T 0 P B of the switched capacitor type step-down circuit. The switch control circuit 4 is a plurality of switch control signals S which are generated based on the clock signal CLK to control the switch array 5 __ 1 to 5 — η. The switch arrays 5_1 to 5_η are switching circuits that belong to a switching capacitor that is configured to perform capacitance division while sequentially changing the connection state of the capacitor receiving the input voltage. VDDCPi is the input voltage terminal, VDDi is the output voltage terminal, V S S i is the ground terminal of the circuit, and C P i and C M i are the terminals for external capacitors (ι =〗 ~ η). The output terminals VDD1 to VDDn are connected in the chip. The same applies to the ground terminals VSS1 to VSSn. -10- 200524255 (8) The output of the switched capacitor buck circuit 6 and the output of the series regulator 2 are connected in common. That is, the output terminals VDD1 to VDDn of the switched capacitor buck circuit 6 are output terminals connected in common to the series regulator 2.

於第2A圖舉例表示開關陣列5_ 1〜5_ η內的其中 之一。開關陣列5 1〜5__ η乃具有相同構成，代表上亦記 爲開關陣列5_ η。第1圖的開關控制信號S在此乃爲S A ，S B，S C之三條開關控制信號。第2 A圖的切換電路乃 可等效式地構成第28圖的切換電容器電路。P通道MOS 電晶體MP1乃相當於第28圖的開關SW1、N通道MOS 電晶體MN1乃相當於第28圖的開關SW2、N通道MOS 電晶體MN2乃相當於第28圖的開關SW3、N通道MOS 電晶體MN3乃相當於第28圖的開關SW4。如第2B圖舉 例所示，開關控制信號S B和S C不會同時成爲低位準， 開關控制信號SA乃爲開關控制信號SB的反轉信號。An example of one of the switch arrays 5_1 to 5_n is shown in FIG. 2A. The switch arrays 5 1 to 5__η have the same structure, which is also referred to as the switch array 5_η. The switch control signal S in FIG. 1 is three switch control signals S A, S B and S C here. The switching circuit of Fig. 2A is equivalent to the switched capacitor circuit of Fig. 28. P-channel MOS transistor MP1 is equivalent to switch SW1 in FIG. 28, and N-channel MOS transistor MN1 is equivalent to switch SW2 in FIG. 28. N-channel MOS transistor MN2 is equivalent to switch SW3 and N-channel in FIG. 28. The MOS transistor MN3 is equivalent to the switch SW4 in FIG. 28. As shown in the example of FIG. 2B, the switch control signals S B and S C do not go to the low level at the same time, and the switch control signal SA is an inverted signal of the switch control signal SB.

於第2A圖的電路中，第28圖的電容器Cl(開關電 容）是連接於端子CM，CP ’電容器C0 (平滑電容）是 外置於電路的接地端子和輸出端子VDD之間。若跟隨第 2B圖的開關控制計時’開關SW1和SW3會被ON，SW2 和 SW4會被 OFF，而電容器 C0和C1會被串接，以 VCCP充電。其次，SW1和SW3會被OFF，SW2和SW4 會被ON，而電容器C0和C1會被並聯。輸出電壓VDD 若無視於開關的ON電阻，大致上會成爲V C C P / 2。如 此一來，藉由切換兩個電容器C 0和C 1的結線’令輸入 電壓VCCP降壓而生成輸出電壓VDD。例如對輸入電壓 -11 - 200524255 (9) 端子V C C P施加2.8 V的話，於輸出電壓端子v D D則輸 出 1.4V。 於第2A圖中，MOS電晶體的通道寬幅/通道長度 例J 如爲 MP 1 = 3 200 / 0.4 、 MN1 = 2 8 00 / 0.4 、 MN2 = 280 0 /0.4、ΜΝ3=1200/0·4(單位 //m) 。MN1、MN2 乃爲In the circuit of Fig. 2A, the capacitor Cl (switching capacitor) of Fig. 28 is connected to the terminal CM, and the CP 'capacitor C0 (smoothing capacitor) is externally connected between the ground terminal of the circuit and the output terminal VDD. If following the switch control timing in Figure 2B, the switches SW1 and SW3 will be turned on, SW2 and SW4 will be turned off, and capacitors C0 and C1 will be connected in series to charge with VCCP. Secondly, SW1 and SW3 will be turned off, SW2 and SW4 will be turned on, and capacitors C0 and C1 will be connected in parallel. If the output voltage VDD is ignored depending on the ON resistance of the switch, it will become V C C P / 2 roughly. As such, the input voltage VCCP is stepped down by switching the junctions of the two capacitors C 0 and C 1 to generate an output voltage VDD. For example, if 2.8 V is applied to the input voltage -11-200524255 (9) terminal V C C P, 1.4 V is output to the output voltage terminal v D D. In Figure 2A, for example, the channel width / channel length of a MOS transistor is MP 1 = 3 200 / 0.4, MN1 = 2 8 00 / 0.4, MN2 = 280 0 /0.4, and MN3 = 1200/0 · 4. (Unit // m). MN1, MN2 are

尺寸比MN3還大。此乃閘極、源極間電壓與 VCCP — V D D —樣小，而施加基板偏壓（一 V D D )的緣故，欲減 低ON電阻加大通道寬幅。It is larger than MN3. This is because the voltage between the gate and source is as small as VCCP — V D D — and the substrate bias (one V D D) is applied. It is necessary to reduce the ON resistance and increase the channel width.

MOS電晶體MP1、MN1、MN2乃爲低臨限値電壓、 MOS電晶體MN3乃爲高臨限値電壓。以 MOS電晶體 MP1、MN1、MN2作爲低臨限値電壓的理由乃爲欲減低 ON電阻。以MOS電晶體MN3作爲高臨限値電壓的理由 乃爲欲減低動作停止時的洩放電流。於動作停止時 S A二 高位準、SB =低位準、SC =高位準。即，MOS電晶體 MP1和 MN2會被 ON、MOS電晶體 MN1和 MN3會被 OFF。以MOS電晶體MN3作爲低臨限値電壓的話，因於 汲極、源極間施加 VDD，則有流入次閾値洩放電流的可 能性。MOS電晶體MN1的汲極、源極間電壓乃爲VCCP - VDD，但施加基板偏壓的緣故，實效臨限値電壓高， 洩放電流小。 在開關陣列 5_ η中不光是開關用的 MOS電晶體 Μ Ρ 1，Μ Ν 1〜Μ Ν 3，也包括驅動該閘極的反相器 IΝ V 1〜 IN V3，乃將前述開關控制電路4和開關陣歹IJ 5— 1〜5— η 分離而配置，欲減輕配線電阻的影響。 -12 - 200524255 (10)The MOS transistors MP1, MN1, and MN2 are low threshold voltages, and the MOS transistors MN3 are high threshold voltages. The reason for using MOS transistors MP1, MN1, and MN2 as low threshold voltages is to reduce the ON resistance. The reason for using the MOS transistor MN3 as a high threshold voltage is to reduce the leakage current when the operation is stopped. When the action stops, S A 2 high level, SB = low level, SC = high level. That is, the MOS transistors MP1 and MN2 are turned on, and the MOS transistors MN1 and MN3 are turned off. When the MOS transistor MN3 is used as the low threshold voltage, there is a possibility that a sub-threshold threshold current may flow because VDD is applied between the drain and source. The voltage between the drain and source of the MOS transistor MN1 is VCCP-VDD. However, due to the application of the substrate bias voltage, the effective threshold voltage is high and the leakage current is small. In the switch array 5_η, not only the switching MOS transistors MP1, MN1 ~ ΜΝ3, but also the inverters INV1 ~ INV3 that drive the gates are included. The aforementioned switch control circuit 4 Separate from the switch array 歹 IJ 5—1 ～ 5— η, and reduce the influence of wiring resistance. -12-200524255 (10)

於第3圖舉例表示串聯式降壓電路2的詳細電路。 該降壓電路2是經由差動放大器DFAMP1來比較基準電 壓VREF和電壓VDD，以控制輸出MOS電晶體MP10。 前述輸出MOS電晶體MP10乃爲P通道型，通道寬幅/ 通道長度例如如5 00 / 0.4 (單位// m )。尺寸比開關陣列 的MOS電晶體MP1還小。欲減低電源上升時的電源電流 峰値。VCCA乃爲輸入電壓端子，電壓位準乃與VCCP相 同。EN2乃爲串聯式降壓電路2的允許信號，EN2二高位 準時即允許、低位準時即禁止。A detailed circuit of the series step-down circuit 2 is shown in FIG. 3 by way of example. The step-down circuit 2 compares the reference voltage VREF and the voltage VDD via a differential amplifier DFAMP1 to control the output MOS transistor MP10. The aforementioned output MOS transistor MP10 is a P-channel type, and the channel width / channel length is, for example, 5 00 / 0.4 (unit // m). It is smaller than the MOS transistor MP1 of the switch array. To reduce the peak power supply current when the power supply rises. VCCA is the input voltage terminal and the voltage level is the same as VCCP. EN2 is the enable signal of the series step-down circuit 2. EN2 is allowed at the high level and disabled at the low level.

於第4圖舉例表示前述位準感測器3的詳細電路。 差動放大器DFAMP2乃比較電壓VIDD和基準電壓VREF ，生成停止信號STOPB。當電壓VDD比基準電壓VREF 更低時，STOPB=高位準，當電壓 VIDD比基準電壓 VREF更高時，STOPB =低位準。EN1乃爲開關電容式降 壓電路的允許信號，ΕΝ 1二高位準時即指示允許、低位準 時即指示禁止。當 EN1=低位準時，STOPB不會因電 壓VDD成爲低位準。 於第5圖舉例表示第1圖的開關控制電路4的詳細 邏輯電路。具有由時脈CLK成生內部時脈ICLK的電路 41和由內部時脈ICLK生成開關控制信號 SA、SB、SC 的電路42。INV乃爲反相器、NAND乃爲反及閘、AND 乃爲及閘、NOR乃爲反或閘、D1乃爲延遲電路。CLK乃 爲時脈輸入端子、STOPB乃爲停止信號、FRUN乃爲測 試用自發信號 。 -13- 200524255 (11) 普通動作時F RUN =低位準。此時若s Τ Ο P B二高位 準，內部ICLK會追隨時脈CLK。若STOPB=低位準， 則內部時脈IC L K =低位準。但內部時脈I C L K =高位準 的期間，即使停止信號 S Τ Ο P B由高位準遷移至低位準， 內部時脈I C L K不會立刻變成低位準，接著時脈c L K變 成低位準時，才成爲低位準。 若FRUN =高位準，內部時脈ICLK不會施加於停止 信號STOPB，會追隨時脈CLK。延遲電路D1乃爲於図2 中信號SB和SC會同時成爲低位準，欲防止流入貫通電 流所設置。 於第6圖舉例表示第1圖的降壓電路的電源上升時 的動作波形。由時刻t 0至11，電源VCCP會上升。由於 串聯式降壓電路允許信號EN 2 = V C C P，串聯式降壓電路 2就會動作。藉此VDD會上升。此時由於ΕΝ 1 =低位準 ，開關電容式降壓電路6尙未動作。由時刻t2輸入時脈 ，於時刻t3中，若ΕΝ 1 =高位準的話，開關電容式降壓 電路6就會開始動作。而且時脈輸入和ΕΝ 1的順序也可 相反進行。 ICCP乃爲流入電源VCCP的電流。t0至t3中’欲令 VDD上升故流入大電流，但因動作僅爲串聯式降壓電路 2，如波形60所示，電流波形很流暢。此乃通過0N電 阻較大的MOS電晶體（第3圖的MP I 〇 )而流入電流的 原因。開關電容式降壓電路6開始動作的話’ ON電阻較 小的開關MOS電晶體會ON的緣故，電流波形乃如6 1所 200524255 (12) 示變尖銳。此時因爲VDD已經上升之後，只要供姶經由 負荷所產生的放電部分即可，其峰値很小。總之，先驅 動串聯穩壓器2並負荷地供給降壓電壓之後，即使驅動 開關電容式降壓電路6，開關電容式降壓電路6只要補充 經由負荷所產生的放電部分即可，對電容器的充電電流 尖峰很小。開始開關電容式降壓電路6的動作時不會產 生很大的湧入電流，可抑制或緩和雜訊的產生。 而且電源上升之後，EN2 =低位準使串聯式降壓電路 2的動作停止亦可。而對應於動作模式使串聯式降壓電路 2動作或停止亦可。例如以消耗電流較多的動作模式使串 聯式降壓電路2和開關電容式降壓電路6之兩者動作會 增加電流供給能力，以消耗電流較少的動作模式只令開 關電容式降壓電路6動作，可使電力轉換效率變佳。 於第7圖舉例表示第1圖的降壓電路的L SI晶片內 配置的例子。1 0乃爲半導體積體電路的晶片（L S I晶片 )、11乃爲接合墊。特別是VCCP1〜VCCP4乃爲輸入電 壓VCCP用接合墊、VDD1〜VDD4乃爲輸出電壓VDD用 接合墊、VSS1〜VSS4乃爲接地用接合墊。CP1〜CP4、 CM1〜CM4乃爲電容器外置用接合墊。於LSI晶片10中 ，以1 2所示的區域乃爲磁心電路部，屬於配置半導體積 體電路之主要部的區域。以1 3所示的區域乃爲I / 〇區 域，主要是屬於配置輸出入電路的區域。 於配置在磁心電路部1 2的電路區域1 4，乃配置前述 基準電壓產生電路1、串聯式降壓電路2、位準感測器3 -15 - 200524255 (13) 、及開關控制電路4。在該電路區域1 4乃當作動作電源 而供給電源VCCA。對電路區域14供給動作電源VCCA 的電源銲墊，乃欲防止電源雜訊，即使電壓位準相同， 亦希望與開關陣列用的電源銲墊VCCP1〜VCCP4分開。 且希望接地電壓配線也與磁心電路部1 2內的數位電路分A detailed circuit of the level sensor 3 is shown in FIG. 4 by way of example. The differential amplifier DFAMP2 compares the voltage VIDD and the reference voltage VREF to generate a stop signal STOPB. When the voltage VDD is lower than the reference voltage VREF, STOPB = high level, and when the voltage VIDD is higher than the reference voltage VREF, STOPB = low level. EN1 is the enable signal of the switched capacitor buck circuit. EN 1 indicates the permission when the high level is on, and the prohibition when the low level is on. When EN1 = low level, STOPB does not go low due to voltage VDD. Fig. 5 shows a detailed logic circuit of the switch control circuit 4 of Fig. 1 by way of example. There is a circuit 41 that generates the internal clock ICLK from the clock CLK, and a circuit 42 that generates the switch control signals SA, SB, and SC from the internal clock ICLK. INV is the inverter, NAND is the inverse AND gate, AND is the AND gate, NOR is the inverse OR gate, and D1 is the delay circuit. CLK is a clock input terminal, STOPB is a stop signal, and FRUN is a test spontaneous signal. -13- 200524255 (11) F RUN = Low level during normal operation. At this time, if s Τ Ο P B high level, the internal ICLK will follow the clock CLK. If STOPB = low level, the internal clock IC L K = low level. However, during the period when the internal clock ICLK = high level, even if the stop signal S Τ PB shifts from the high level to the low level, the internal clock ICLK does not immediately become the low level, and then the clock c LK becomes the low level before it becomes the low level . If FRUN = high level, the internal clock ICLK will not be applied to the stop signal STOPB, and will follow the clock CLK. The delay circuit D1 is set so that the signals SB and SC will go to the low level at the same time in 図 2 to prevent the inrush current from flowing. Fig. 6 shows an example of an operation waveform when the power of the step-down circuit of Fig. 1 is increased. From time t 0 to 11, the power supply VCCP will rise. Since the serial step-down circuit enable signal EN 2 = V C C P, the series step-down circuit 2 will operate. As a result, VDD will rise. At this time, because EN 1 = low level, the switched-capacitor buck circuit 6 电路 does not operate. The clock is input at time t2. At time t3, if ENE 1 = high level, the switched capacitor buck circuit 6 will start to operate. And the order of clock input and EN 1 can be reversed. ICCP is the current flowing into the power supply VCCP. From t0 to t3 ', a large current flows in to increase VDD, but the operation is only a series buck circuit 2. As shown in waveform 60, the current waveform is smooth. This is the reason why a current flows through the MOS transistor (MP I 0 in FIG. 3) having a large resistance of 0N. When the switched-capacitor step-down circuit 6 starts to operate, the switching MOS transistor with a smaller ON resistance will turn on. The current waveform will be sharp as shown in 2005 2005255 (12). At this time, after VDD has risen, it only needs to supply the discharge part generated by the load, and its peak value is small. In short, after driving the series regulator 2 and supplying the step-down voltage under load, even if the switched-capacitor step-down circuit 6 is driven, the switched-capacitor step-down circuit 6 only needs to supplement the discharge part generated by the load. The charging current spike is small. When the operation of the switched capacitor buck circuit 6 is started, a large inrush current is not generated, and the generation of noise can be suppressed or mitigated. In addition, after power-up, EN2 = low level can stop the operation of the series buck circuit 2. The series step-down circuit 2 may be operated or stopped according to the operation mode. For example, operating both the series buck circuit 2 and the switched capacitor buck circuit 6 in an operation mode with a large current consumption will increase the current supply capability, and only the switched capacitor buck circuit in an operation mode with a low current consumption. 6 actions can make the power conversion efficiency better. An example of the arrangement in the L SI chip of the step-down circuit of Fig. 1 is shown in Fig. 7 as an example. 10 is a wafer of a semiconductor integrated circuit (L S I wafer), and 11 is a bonding pad. In particular, VCCP1 to VCCP4 are bonding pads for input voltage VCCP, VDD1 to VDD4 are bonding pads for output voltage VDD, and VSS1 to VSS4 are bonding pads for ground. CP1 to CP4 and CM1 to CM4 are bonding pads for external capacitors. In the LSI wafer 10, a region shown by 12 is a core circuit portion, and belongs to a region where a main portion of a semiconductor integrated circuit is arranged. The area shown by 13 is the I / 0 area, which is mainly the area where the input / output circuits are arranged. In the circuit area 14 arranged in the magnetic core circuit section 12, the aforementioned reference voltage generating circuit 1, series step-down circuit 2, level sensor 3 -15-200524255 (13), and switch control circuit 4 are arranged. The power supply VCCA is supplied to the circuit area 14 as an operation power supply. The power supply pads for supplying the operating power VCCA to the circuit area 14 are intended to prevent power noise. Even if the voltage levels are the same, it is desirable to separate them from the power supply pads VCCP1 to VCCP4 for the switch array. It is desirable that the ground voltage wiring is also separated from the digital circuits in the core circuit section 12.

15— 1、15 2、15一 3、15— 4乃屬於配置著位在I / 0區域1 3內的開關陣列、欲防止破壞靜電的保護元件 的區域。 圖示省略，但開關控制信號 S A、S B、S C乃從電路 區域1 4開始配線到電路區域1 5 — 1、1 5 — 2、1 5 — 3、1 5 _ 4。而電源電壓VDD乃作爲磁心電路部1 2的動作電源 而網格狀配線於L S I晶片1 0內。 配置著開關陣列之區域1 5_ 1〜1 5_ 4乃配置於位在 所對應的接合墊1 1近傍的I / 0區域，能縮小經由配線 產生的寄生電容/寄生電阻。而因基準電壓產生電路1 和位準感測器3的電源VCCA、開關陣列的電源VCCP是 被分開，故能防止經由開關動作產生的電源雜訊使基準 電壓產生電路1和位準感測器3受到不良影響。 於第8圖舉例表示將搭載第1圖的降壓電路的半導 體積體電路實裝於配線基板的狀態。2 0乃爲配線基板（ board) 、21乃爲半導體積體電路的封裝（LSI封裝）， 第7圖的L SI晶片被密封。2 2乃爲半導體積體電路的外 部端子，23_ 0乃爲如晶片電容器的電容器，電容例如爲 -16 - 200524255 (14) 1//F，相當於第28圖的容量CO。23一 1〜23 一 4乃爲如 晶片電容器的電容器，電容例如爲〇 · 1 // F，相當於第2 8 圖的C 1。2 4乃爲基板上電源V C C配線、2 5乃爲基板上 接地電位V S S配線、2 6乃爲基板上降壓電壓V D D配線 〇 開關電容式降壓電路6乃將第1圖的電路構成四組 設置於LSI晶片上，對應於此而實裝四個電容器23_ 1〜 23_4。平滑用電容器23— 0乃共通於四組電路地僅實裝 一個。藉由共通化就能減低成本、實裝面積。電容器23 _1〜23_4乃欲減低寄生電阻 寄生電感，希望儘量實 施在端子附近。 於第 9圖舉例表示有關本發明的半.導體積體電路配 備於晶片內的降壓電路的第2例。於同圖所示的降壓電 路乃爲開關控制電路7與第1圖不同。即，與第1圖的 不同點爲將複數個（在此爲四個）開關陣列5 _ 1〜5 _ 4 以各個相位不同的控制信號S 1〜S 4來驅動。控制信號 S1實際上如第1〇圖所示，由S1A、SIB、S1C之三條信 號所形成。S 2〜S 4也是同樣的。藉此能減低電源電流的 峰値。像這樣即有助於減低利用欲對複數個開關陣列5 _ 1〜5_ 4的電容連接之切換的開關的高頻雜訊。換言之就 能複數分割開關電容式降壓電路的開關陣列並錯開各個 相位而驅動，藉此電源電流的峰値變小。 於第1 0圖舉例表示第9圖的開關控制電路7的詳細 電路。4 1 — 1〜4 1 — 4乃爲與第5圖之4 1的電路相同，由 -17 - 200524255 (15) 所對應的時脈C L K i生成內部時脈i c L K i ( i = 1〜4 )。 42一 1〜42一 4乃爲與第5圖之42的電路相同，由各個所 對應的內部時脈I C L K i生成開關控制信號s丨a、S i B、 S i C ( ;i二1〜4 )。以7 1所示的電路乃爲分頻電路，令時 脈CLK分頻而生成時脈CLK1〜CLK4。FF1、FF2乃爲以 時脈輸入（C K )的前緣進行動作的D正反器。C L K1、 CLK2、CLK3、CLK4係周期爲時脈CLK的兩倍，並成爲 每9 0度錯開相位的時脈。波形乃於第3 0圖舉例表示經 此所形成的時脈CLK1〜CLK4。 於第 30圖中，CLK1乃以 CLK的上升做變化。 CLK2乃以CLK的下降做變化。CLK3乃爲CLK1的反轉 信號。CLK4乃爲CLK2的反轉信號。在初期狀態係信號 STOPB爲低位準，ICLK1〜ICLK4則全爲低位準。在時 亥！J tl，信號STOPB爲高位準的話，分別由時脈CLK1生 成時脈ICLK1，由時脈CLK2生成時脈ICLK2，由時脈 CLK3生成時脈ICLK3，由時脈CLK4生成時脈ICLK4。 在時刻t2，即使信號STOPB爲低位準，在此時點屬於高 位準的時脈 ICLK1不會立刻成爲低位準，接著時脈 CLK1成爲時才變成低位準。時脈ICLK2也是同樣的。 時脈ICLK3和時脈ICLK4因在時刻t2爲低位準，故依 然保持低位準狀態。 於第U圖表示有關本發明的半導體積體電路配備於 晶片內的降壓電路的第3例。與第9圖的不同點在於追 加相位隨機化電路8的這點。相位隨機化電路8乃爲生 -18- 200524255 (16) 成隨機地錯移時脈 CLK的上升、下降之計時的時脈 RCLK，以此作爲開關控制電路7的輸入。藉此就可得到 能令雜訊的高頻成份之頻譜分散的優點。特別是應用於 攜帶電話機等之攜帶無線機器的情形，因干擾電波的頻 譜會被分散故很有效。 於第1 2圖舉例表示相位隨機化電路8的邏輯構成。15-1, 15-2, 15-1, and 3-15-4 belong to the area where the switch array located in the I / 0 area 1 and 3, and the protection element to prevent the destruction of static electricity. The illustration is omitted, but the switch control signals S A, S B, and S C are wired from the circuit area 14 to the circuit area 1 5 — 1, 1 5 — 2, 1 5 — 3, 1 5 _ 4. The power supply voltage VDD serves as an operating power source for the magnetic core circuit section 12 and the grid-shaped wiring is inside the L S I chip 10. The area 1 5_ 1 ~ 1 5_ 4 where the switch array is arranged is located in the I / 0 area near the corresponding bonding pad 11, which can reduce the parasitic capacitance / parasitic resistance generated through the wiring. Since the power supply VCCA of the reference voltage generation circuit 1 and the level sensor 3 and the power supply VCCP of the switch array are separated, it is possible to prevent the power supply noise generated by the switching operation from causing the reference voltage generation circuit 1 and the level sensor. 3 Affected adversely. Fig. 8 shows an example of a state in which a semiconductor volume body circuit incorporating the step-down circuit of Fig. 1 is mounted on a wiring board. 20 is a wiring board (board), 21 is a semiconductor integrated circuit package (LSI package), and the L SI chip in FIG. 7 is sealed. 2 2 is an external terminal of a semiconductor integrated circuit, and 23_ 0 is a capacitor such as a chip capacitor. The capacitance is, for example, -16-200524255 (14) 1 // F, which is equivalent to the capacity CO shown in FIG. 28. 23 ~ 1 ~ 23 ~ 4 are capacitors such as chip capacitors. The capacitance is, for example, 0 · 1 // F, which is equivalent to C 1. in Figure 28. 2 4 is the power supply VCC wiring on the substrate, and 2 5 is the substrate. The upper ground potential VSS wiring and 26 are the step-down voltage VDD wiring on the substrate. The switched-capacitor step-down circuit 6 consists of four sets of the circuit structure shown in Figure 1 on the LSI chip. Four capacitors are installed correspondingly to this. 23_ 1 ~ 23_4. The smoothing capacitors 23-0 have only one common ground for the four sets of circuits. Commonization can reduce cost and installation area. Capacitors 23_1 ~ 23_4 are intended to reduce parasitic resistance and parasitic inductance, and they are preferably implemented near the terminals. A second example of the step-down circuit in which the semi-conducting volume circuit of the present invention is provided in a chip is shown in FIG. 9 as an example. The step-down circuit shown in the same figure is different from the switch control circuit 7 in the first figure. That is, the difference from FIG. 1 is that a plurality of (here, four) switch arrays 5 _ 1 to 5 _ 4 are driven by control signals S 1 to S 4 having different phases. The control signal S1 is actually formed by three signals of S1A, SIB, and S1C, as shown in FIG. The same applies to S 2 to S 4. This reduces the peak current of the power supply. In this way, it is possible to reduce the high-frequency noise of the switches that are used to switch the capacitive connection of the plurality of switch arrays 5_1 to 5_4. In other words, the switch array of the switched-capacitor buck circuit can be divided in plural and driven by staggering the phases, thereby reducing the peak current of the power supply current. The detailed circuit of the switch control circuit 7 of Fig. 9 is shown in Fig. 10 by way of example. 4 1 — 1 to 4 1 — 4 is the same as the circuit of 4 1 in Figure 5, and the internal clock ic LK i (i = 1 to 4 is generated from the clock CLK i corresponding to -17-200524255 (15) ). 42-1 ~ 42-4 is the same circuit as 42 in FIG. 5, and the corresponding internal clock ICLK i generates the switch control signals s 丨 a, S i B, S i C (; i 2 1 ~ 4). The circuit shown by 7 1 is a frequency dividing circuit. The clock CLK is divided to generate clocks CLK1 to CLK4. FF1 and FF2 are D flip-flops that operate with the leading edge of the clock input (C K). C L K1, CLK2, CLK3, and CLK4 have a cycle that is twice the clock CLK and become a clock that is out of phase every 90 degrees. The waveforms in Figure 30 show the clocks CLK1 to CLK4 formed by this example. In Figure 30, CLK1 changes with the rise of CLK. CLK2 changes with the falling of CLK. CLK3 is the inverted signal of CLK1. CLK4 is the inverted signal of CLK2. In the initial state, the signal STOPB is at the low level, and ICLK1 to ICLK4 are all at the low level. At the time! J tl, if the signal STOPB is high, clock ICLK1 is generated by clock CLK1, clock ICLK2 is generated by clock CLK2, clock ICLK3 is generated by clock CLK3, and clock ICLK4 is generated by clock CLK4. At time t2, even if the signal STOPB is at the low level, the clock ICLK1 belonging to the high level at this point will not immediately become the low level, and then the clock CLK1 will become the low level when it becomes the low level. The same is true for the clock ICLK2. The clock ICLK3 and clock ICLK4 are at the low level at time t2, so they remain at the low level. Fig. U shows a third example of the step-down circuit in which the semiconductor integrated circuit of the present invention is incorporated in a chip. The difference from FIG. 9 lies in the point that the phase randomization circuit 8 is added. The phase randomization circuit 8 is used to generate a clock RCLK that randomly shifts the timing of the rise and fall of the clock CLK, as an input to the switch control circuit 7. This can obtain the advantage of being able to disperse the spectrum of the high frequency components of the noise. It is particularly effective when applied to portable wireless devices such as mobile phones, because the frequency spectrum of interference radio waves is scattered. The logical structure of the phase randomization circuit 8 is shown by way of example in FIG. 12.

8 0乃爲僞亂數產生電路、8 1乃爲單發脈衝產生電路、8 2 _ 1〜8 2_ 4乃爲閂鎖電路。閂鎖的信號R、F乃爲複數 位元的緣故，實際上前述閂鎖電路82_ 1〜82_ 4乃分別 由複數個閂鎖所形成。8 3 _ 1〜8 3 _ 4乃爲可變延遲電路 。延遲時間係以控制信號Rl、R2、F2、R3、R4、F4所 決定。84、乃爲時脈合成電路。 R、F乃爲僞亂數。實際上乃分別由複數位元（例如 5位元）所形成。F乃爲半循環比R還快的信號。 P 1乃爲在時脈C LK的奇數循環的前緣僅所計時間成 爲高位準的單發脈衝。P2乃爲在時脈CLK的奇數循環的 拖後緣僅所計時間成爲高位準的單發脈衝。P3乃爲在時 脈CLK的偶數循環的前緣僅所計時間成爲高位準的單發 脈衝。P4乃爲在時脈CLK的偶數循環的拖後緣僅所計時 間成爲高位準的單發脈衝。P1D、P2D、P3D、P4D乃爲 分別將PI、P2、P3、P4以可變延遲電路所延遲的信號。 具有第1 2圖構成的相位隨機化電路8是利用單發脈 衝產生電路8 1取出時脈CLK的前緣/拖後緣，且將各 個連通於可變延遲電路8 3 — 1〜8 3 _ 4，藉此就能獨立地 -19 - 200524255 (17) 控制各循環的上升、拖後緣的延遲量。總之，p 1、P3乃 利用時脈CLK的上升同步而被脈衝變化，P2、P4乃利用 時脈CLK的下降同步而被脈衝變化，閂鎖82— 1〜82— 4 乃利用P 1〜P 4之對應信號的脈衝變化而閂鎖亂數R、F ，可變延遲電路83— 1〜83—4乃將P1〜P4之對應信號 的脈衝變化應對於亂數R、F而延遲並形成PD1〜PD4而 輸出，時脈合成電路84乃與PD1、PD3的脈衝變化同步 並將時脈RCLK變爲高位準，與PD2、PD4的脈衝變化 同步並將時脈RCLK變爲低位準。藉此時脈RCLK乃對 時脈CLK而隨機化。 於第1 3圖舉例表示第1 2圖的僞亂數產生電路8 0的 邏輯構成。FFl〇〜FF18乃爲在時脈輸入（CK )的前緣進 行動作的D正反器。L4〜L 8乃爲閂鎖，允許輸入（E ) 爲高位準時實行通過、爲低位準時實行閂鎖動作。EOR 乃爲排他的邏輯和（exclusive OR)閘極。RST乃爲重置 信號。以重置信號RST作爲高位準，藉此D正反器FF1 〇的輸出設定爲高位準、D正反器FF1 1〜FF1 8的輸出設 定爲低位準、閂鎖L4〜L 8的輸出設定爲低位準。利用D 正反器FF11〜FF18及EOR的邏輯構成乃爲僞亂數產生 電路的一般構成。閂鎖L4〜L8乃比正反器FF14〜FF18 還要快一時脈C L K的半循環D，且與此一同輸入加以閂 鎖。 R〔 4〕〜R〔 8〕乃爲僞亂數輸出。於九個正反器的 輸出生成周期2 9 = 5 1 1的僞亂數。僞亂數僅採用9位 200524255 (18) 元中的5位元r〔4〕〜r〔8〕〇F〔4〕〜F〔8〕乃爲半 循環比各個R〔 4〕〜R〔 8〕還快的信號。 於第1 4圖舉例表示第1 2圖的單發脈衝產生電路8 1 的邏輯構成。FF21、FF22乃爲以時脈輸入（CK )的前緣 進行動作的D正反器。D21、D22乃爲延遲電路。PI、P2 、P3、p4乃爲輸出信號。P1乃爲在時脈CLK的奇數循 環的前緣、P2乃爲在時脈CLK的奇數循環的拖後緣、P3 乃爲在時脈CLK的偶數循環的前緣、P4乃爲在時脈CLK 的偶數循環的拖後緣分別僅特定時間（D21、D22的延遲 時間）成爲高位準。 於第15圖舉例表示第12圖的可變延遲電路83_ 2 的邏輯構成。其它可變延遲電路 83—1、83—3、83__4 亦具備同樣的構成。A乃爲加算電路、D 3 — 1〜D 3 — m乃 爲單位延遲電路、S1乃爲選擇器、R2、F2乃分別爲複數 位元的控制信號。將輸入信號P2通過m個單位延遲電路 D 3 — 1〜D 3 — m所得到的信號中的第（R + F )以選擇器 S1做選擇，形成輸出P2D。延遲時間乃爲td ( R + F )。 td乃爲單位延遲電路的延遲時間的意思。 供給到選擇器S 1的前述第（R + F )的選擇信號乃生 成加算電路A。P2、P4乃規定時脈RCLK的下降，由於 該下降不會比規定P1、P3之上升更前面的計時出現， P2D ( P4D )對P2(P4)而言，使用R2及其半循環前之 値的F2之和（實質上爲平均）作爲選擇器S 1的選擇信 號。P 1、P3乃因不需要規定時脈RCLK之上升那樣的考 200524255 (19) 慮，在加算電路A使用R1+Rl (R3+R3)之値作爲選 擇器S 1的選擇信號。總之’有關8 3 — 1 ' 8 3 — 3的可變 · 延遲電路即使不設加算電路A ’兩組控制信號仍爲相同 、 信號，故能簡單的以1位元移位做處理。 於第1 6圖舉例表示第1 2圖的時脈合成電路8 4的邏 輯構成。S2乃爲選擇器、RNDM乃爲相位隨機化允許信 號。RNDM=高位準時，輸出RCLK乃以P1D爲高位準 的計時成爲高位準，以P2D爲高位準的計時成爲低位準 φ ，以P 3 D爲高位準的計時成爲高位準，以P 4 D爲高位準 的計時成爲低位準。RNI ) M =低位準時，輸入時脈CLK 仍然爲輸出時脈RCLK。g卩，不實行相位隨機化。 於第1 7圖舉例表示第].2圖的相位隨機化電路8的 動作波形。於每於時脈CLK的前緣（tl、t3、t5....... )生成新的僞亂數R ( r 1、r 2、l. 3.......)。僞亂數F乃 半循環比此還要快，亦即以C L K的拖後緣進行變化。 單發脈衝P 1乃爲在時脈CLK的奇數循環的前緣（t ] φ 、t5....... ) 、P2乃爲在時脈CLK的奇數循環的拖後緣 (t2、t6....... ) 、P3乃爲在時脈CLK的偶數循環的前 緣（ί3、η....... ) 、P4乃爲在時脈CLK的偶數循環的 拖後緣（t4、t8.......)分別僅所計時間成爲高位準。 閂鎖電路82一 1的輸出R1乃P]變化爲高位準。亦 即，分別在時刻tl變爲rl，在t5變爲r3等。閂鎖電路 · 82一 2的輸出R2、F2乃P2分別變爲高位準。亦即，在 ♦ 時刻t2分別變爲r 1、r2，在t6分別變爲r3、r4等。問 -22- 200524255 (20) 鎖電路82—3的輸出R3乃P3變爲高位準。亦即，在時 刻t3變爲r2，在t7變爲r4等。閂鎖電路82— 4的輸出 R 4、F 4乃P 4分別變爲高位準。亦即，在時刻14分別變 爲ι·2、r3，在t8分別變爲r4、r5等。 可變延遲電路83_1的輸出P1D乃爲P1僅延遲td (2 R1)的脈衝。可變延遲電路83_2的輸出P2D乃 爲P2僅延遲td ( R2 + F2 )的脈衝。可變延遲電路83_ 3 的輸出P3D乃爲P3僅延遲td ( 2 R3 )的脈衝。可變延 遲電路83—4的輸出P4D乃爲P2僅延遲td(R4+F4) 的脈衝。 輸出RCLK乃以P1D成爲高位準的計時變爲高位準 ，以P2D成爲高位準的計時變爲低位準，以P3D成爲高 位準的計時變爲高位準，以P4D成爲高位準的計時變爲 低位準。因而，CLK之時刻11的前緣僅延遲td ( 2 r 1 )，t2的拖後緣僅延遲td ( r 1 + r2 ) ，t3的前緣僅延遲 td ( 2 r2 ) ，t4的拖後緣僅延遲td ( t2 + t3 )。 若藉由相位隨機化電路8 ’拖後緣的延遲時間乃變爲 其前後之前緣的延遲時間的平均値。因而’就算延遲時 間的最大値設定的相當大，R C L K的高位準期間不變，或 者低位準期間不變。理論上延遲時間的最大値等於C L Κ 的周期。 於第1 8圖舉例表示第】2圖的可變延遲電路8 3 — 2 ( 8 3 — 1、8 3 — 3、8 3 — 4 )的另一例。於第1 8圖中’ D 4乃 爲延遲電路、90一 1乃爲單位可變延遲電路。該電路乃具 -23- 200524255 (21) 有兩個單位延遲電路D5_ 1、D5__ 2。當控制信號R2〔 4 〕、F2〔 4〕同爲低位準時，輸入信號P2D0不會通過單 位延遲電路會被輸出。僅R2〔 4〕 、F2〔 4〕中的其中一8 0 is a pseudo random number generating circuit, 8 1 is a single-shot pulse generating circuit, and 8 2 _ 1 to 8 2_ 4 are latch circuits. The latched signals R and F are for a plurality of bits. In fact, the aforementioned latch circuits 82_ 1 to 82_ 4 are respectively formed by a plurality of latches. 8 3 _ 1 to 8 3 _ 4 are variable delay circuits. The delay time is determined by the control signals R1, R2, F2, R3, R4, F4. 84. It is a clock synthesizing circuit. R and F are pseudo-random numbers. They are actually formed by plural bits (such as 5 bits). F is a signal that the half cycle is faster than R. P 1 is a single-shot pulse with only a high time counted at the leading edge of the odd-numbered cycle of the clock C LK. P2 is a single-shot pulse with the trailing edge of the odd-numbered cycle of the clock CLK only reaching the high level in the counted time. P3 is a single-shot pulse with only the counted time reaching the high level at the leading edge of the even-numbered cycle of the clock CLK. P4 is a single-shot pulse that becomes high only during the trailing edge of the even cycle of the clock CLK. P1D, P2D, P3D, and P4D are signals delayed by PI, P2, P3, and P4 with variable delay circuits, respectively. The phase randomization circuit 8 having the structure shown in FIG. 12 uses a single-shot pulse generating circuit 8 1 to take out the leading edge / trailing edge of the clock CLK and connect each to the variable delay circuit 8 3 — 1 ~ 8 3 _ 4, so that you can independently -19-200524255 (17) Control the amount of delay of the rising and trailing edges of each cycle. In short, p1 and P3 are pulsed using the rising synchronization of the clock CLK, and P2 and P4 are pulsed using the falling synchronization of the clock CLK. Latches 82-1 to 82-4 are made using P1 to P The random number R, F is latched by the pulse change of the corresponding signal of 4. The variable delay circuits 83-1 to 83-4 delay the pulse change of the corresponding signal of P1 to P4 and form PD1 for the random numbers R, F ~ PD4 is output, and the clock synthesizing circuit 84 synchronizes with the pulse changes of PD1 and PD3 and sets the clock RCLK to a high level, synchronizes with the pulse changes of PD2 and PD4 and sets the clock RCLK to a low level. With this, the clock RCLK is randomized to the clock CLK. Fig. 13 shows an example of the logical configuration of the pseudo-number generating circuit 80 of Fig. 12. FF10 to FF18 are D flip-flops that operate on the leading edge of the clock input (CK). L4 ~ L 8 are latches, allowing the input (E) to pass when the high level is on, and latch when the low level is on. EOR is an exclusive OR gate. RST is a reset signal. The reset signal RST is used as the high level, whereby the output of the D flip-flop FF1 〇 is set to the high level, the outputs of the D flip-flops FF1 1 to FF1 8 are set to the low level, and the outputs of the latches L4 to L 8 are set to Low level. The logic configuration using D flip-flops FF11 to FF18 and EOR is a general configuration of a pseudo random number generating circuit. The latches L4 to L8 are half cycle D of clock C L K faster than the flip-flops FF14 to FF18, and are input and latched together. R [4] ~ R [8] are output for pseudo-random numbers. The output of the nine flip-flops is a spurious number with a period of 2 9 = 5 1 1. The pseudo-random number uses only 9 digits. 200524255 (18) 5 digits r [4] ~ r [8] 〇F [4] ~ F [8] are half-cycle ratios than each of R [4] ~ R [8 〕 Fast signals. The logical configuration of the single-shot pulse generating circuit 8 1 of FIG. 12 is shown in FIG. 14 as an example. FF21 and FF22 are D flip-flops that operate with the leading edge of the clock input (CK). D21 and D22 are delay circuits. PI, P2, P3, p4 are output signals. P1 is the leading edge of the odd-numbered cycle of the clock CLK, P2 is the trailing edge of the odd-numbered cycle of the clock CLK, P3 is the leading edge of the even-numbered cycle of the clock CLK, and P4 is the clock CLK The trailing edges of the even-numbered cycles become high only at specific times (delay times of D21 and D22). FIG. 15 shows an example of the logical configuration of the variable delay circuit 83_ 2 of FIG. 12. The other variable delay circuits 83-1, 83-3, and 83__4 also have the same structure. A is an adding circuit, D 3 — 1 to D 3 — m is a unit delay circuit, S1 is a selector, and R2 and F2 are control signals of complex bits, respectively. The input signal P2 passes through the m unit delay circuits D 3 — 1 to D 3 — m, and the (R + F) th of the signals obtained is selected by the selector S1 to form an output P2D. The delay time is td (R + F). td means the delay time of the unit delay circuit. The aforementioned (R + F) selection signal supplied to the selector S 1 generates an addition circuit A. P2 and P4 are the declines of the specified clock RCLK. Since the decline will not occur earlier than the rise of the prescribed P1 and P3, P2D (P4D) For P2 (P4), use R2 and its half cycle before. The sum of F2 (substantially average) is used as the selection signal of the selector S1. P1 and P3 are considered because the rise of the clock RCLK does not need to be specified. 200524255 (19) Consider that in the addition circuit A, one of R1 + Rl (R3 + R3) is used as the selection signal of the selector S1. In short ‘8 3 — 1 '8 3 — 3 is variable. • Even if the delay circuit is not provided with the addition circuit A, the two sets of control signals are the same signal, so it can be simply processed by a 1-bit shift. The logical configuration of the clock synthesizing circuit 84 of Fig. 12 is shown in Fig. 16 as an example. S2 is a selector and RNDM is a phase randomization enable signal. When RNDM = high level, the output RCLK is the high level with P1D as the high level, the P2D high level as the low level φ, and the P 3 D high level as the high level and P 4 D as the high level. The accurate timing becomes the low level. RNI) M = low level, the input clock CLK is still the output clock RCLK. g 卩, phase randomization is not implemented. Fig. 17 shows an example of operation waveforms of the phase randomization circuit 8 in Fig. 2. A new spurious number R (r 1, r 2, l. 3 ....) is generated for each leading edge (tl, t3, t5, ...) of the clock CLK. The pseudo-random number F is half-cycle faster than this, that is, the trailing edge of C L K changes. The single-shot pulse P 1 is the leading edge of the odd-numbered cycle of the clock CLK (t) φ, t5 ........., and P2 is the trailing edge of the odd-numbered cycle of the clock CLK (t2, t6). .......), P3 is the leading edge of the even-numbered cycle of the clock CLK (ί3, η ...), and P4 is the trailing edge of the even-numbered cycle of the clock CLK ( t4, t8 .......) Only the counted time becomes high. The output R1 of the latch circuit 82-1 is changed to a high level. That is, it becomes rl at time t1, and it becomes r3 at t5, and so on. Latch circuit • The outputs R2, F2 and P2 of 82-1 are set to high levels, respectively. That is, at time t2, it becomes r1, r2, and at t6, it becomes r3, r4, and so on. Question -22- 200524255 (20) The output R3 but P3 of the lock circuit 82-3 goes high. That is, t3 becomes r2 at time, r4 becomes t4, and so on. The outputs R 4, F 4 and P 4 of the latch circuits 82-4 go to high levels, respectively. That is, it becomes ι · 2, r3 at time 14 and r4, r5, etc. at t8, respectively. The output P1D of the variable delay circuit 83_1 is a pulse in which P1 delays only td (2 R1). The output P2D of the variable delay circuit 83_2 is a pulse in which P2 delays only td (R2 + F2). The output P3D of the variable delay circuit 83_ 3 is a pulse in which P3 delays only td (2 R3). The output P4D of the variable delay circuit 83-4 is a pulse in which P2 delays only td (R4 + F4). The output RCLK is changed to a high level when P1D becomes a high level, a timing when P2D becomes a high level becomes a low level, a timing when P3D becomes a high level becomes a high level, and a timing when P4D becomes a high level becomes a low level. . Therefore, the leading edge of time 11 at CLK is delayed only by td (2 r 1), the trailing edge of t2 is delayed by only td (r 1 + r2), the leading edge of t3 is delayed by only td (2 r2), and the trailing edge of t4 Delay only td (t2 + t3). If the delay time of the trailing edge is delayed by the phase randomization circuit 8 ', it becomes the average delay time of the leading edges of the leading and trailing edges. Therefore, even if the maximum value of the delay time is set to be quite large, the high level period of R C L K does not change, or the low level period does not change. The theoretical maximum delay time 値 is equal to the period of C L K. Fig. 18 shows another example of the variable delay circuit 8 3-2 (8 3-1, 8 3-3, 8 3-4) of Fig. 2 as an example. In Fig. 18, D4 is a delay circuit, and 90-1 is a unit variable delay circuit. This circuit has -23- 200524255 (21) There are two unit delay circuits D5_ 1, D5__ 2. When the control signals R2 [4] and F2 [4] are both at the low level, the input signal P2D0 will not be output through the unit delay circuit. Only one of R2 [4] and F2 [4]

方爲高位準時，只通過D5— 1，而當R2〔 4〕、F2〔 4〕 同爲高位準時會通過D5_l和D5_2之兩方而輸出。90 —2、90— 3、90— 4、90— 5亦爲具備與90— 1同樣之電 路構成的單位可變延遲電路。藉此，於各個5位元的R2 和F2根據各對應的每一 2位元的邏輯値的組合爲（高位 準，高位準）、（高位準，低位準）、（低位準，低位 準）的任何組合，從三種延遲時間選擇一種延遲時間， 結果從3 2種延遲時間選擇一種延遲時間，即可對P2生 成P2D。而且單位延遲電路的延遲時間在 90_ 2設定爲 90— 1的兩倍，在90— 3設定置四倍，在90_ 4設定爲八 倍、在90_ 5設定在十六倍。When the square is at the high level, only D5-1 is passed, and when both R2 [4] and F2 [4] are at the high level, it will be output through both of D5_1 and D5_2. 90-2, 90-3, 90-4, 90-5 are unit variable delay circuits with the same circuit configuration as 90-1. Therefore, the combination of R2 and F2 in each 5 bits is (high level, high level), (high level, low level), (low level, low level) according to the combination of each corresponding two bit logical 値. For any combination of, choose one delay time from three delay times. As a result, choose one delay time from 32 delay times, and P2D can be generated for P2. Moreover, the delay time of the unit delay circuit is set to 90 times 2 in 90_2, four times in 90-3, eight times in 90_4, and sixteen times in 90_5.

如果從輸入P2至輸出P2D的延遲時間無視於邏輯閘 極的延遲時間，即以td { ( R2〔 4〕+ F2〔 4〕)+2( R2〔 5〕+ F2〔 5〕) + 4 ( R2〔 6〕+ F2〔 6〕) + 8 ( R2 〔7〕 + F2〔7〕 ) +16(R2〔8〕 + F2〔8〕 ) } + td4 表 現。Td爲單位延遲電路D5— 1、D5— 2的延遲時間，td4 爲延遲電路D 4的延遲時間。 延遲電路D4的作用乃在於利用控制信號R〔 4〕〜R 〔8〕、F〔 4〕〜F〔 8〕的延遲時間之設定完成後，將輸 入脈衝P 2通過單位可變延遲電路。 第1 8圖的電路構成與第1 5圖的電路相比，不需加 -24 - 200524255 (22) 算電路A的緣故，具有電路規模較小的優點。 於第19圖舉例表示第12圖的可變延遲電路83—2 ( 8 3 一 1、8 3 — 3、8 3 — 4 )的更另一例。A乃爲加算電路、 S3乃爲選擇器、91— 1、91 2乃爲可變延遲電路。屬於 將單位延遲電路複數個級聯連接的電路，但各單位延遲 電路的延遲時間乃根據改變偏壓電壓Vbi as進行控制。 9 2乃爲充電閥電路，依照上升信號UP、下降信號d 0 WN 的指示，令V b i a s上升或下降。9 3乃爲相位比較電路， 比較P2和將此通過可變延遲電路91— 1、92 _ 2的信號 P 2 F的相位。P 2 F對P 2而言延遲的話，輸出信號u P並 令Vbi as上升，縮短可變延遲電路91— 1、92— 2的延遲 時間。P 2 F對‘ P 2而言前進的話，輸出信號d Ο W N並令 Vbias下降，加長可變延遲電路91— 1、92_2的延遲時 間。 可變延遲電路91一 1、91— 2、充電閥92、及相位比 較電路93例如可利用與類比D1L ( delay — locked loop ) 電路所使用者同樣的電路構成而實現。 第1 9圖的電路動作原理乃爲與第1 5圖的電路同樣 的。但利用 Vbias控制延遲時間的這點並不同。利用第 1 9圖的電路構成的優點，乃爲就算時脈CLK的周期和電 壓、溫度產生變化，或者過程發生誤差，都可將輸入P2 至輸出P2D的延遲時間的最大値設定成等於CLK的周期 。P 2和P 2 F的相位同等的話，9 ] — 1、9 2 一 2的延遲時間 之合計乃等於CLK之周期的兩倍。因而，P2至P2D的 200524255 (23) 延遲時間的最大値即9 1 _ 1的延遲時間乃等於C L K的周 期。 可變延遲電路91—2、充電閥92、及相位比較電路 93乃爲設置供測定時脈CLK之周期的電路，故可在第 12圖的四個可變延遲電路83— 1〜83—4 —起共用。所產 生的偏壓電壓Vbias分配於可變延遲電路83_1〜83_4 即可。If the delay time from input P2 to output P2D is ignored regardless of the delay time of the logic gate, then td {(R2 [4] + F2 [4]) + 2 (R2 [5] + F2 [5]) + 4 ( R2 [6] + F2 [6]) + 8 (R2 [7] + F2 [7]) +16 (R2 [8] + F2 [8])} + td4. Td is the delay time of the unit delay circuits D5-1, D5-2, and td4 is the delay time of the delay circuit D4. The function of the delay circuit D4 is to use the control signals R [4] ~ R [8], F [4] ~ F [8] to set the delay time, and then pass the input pulse P2 through the unit variable delay circuit. Compared with the circuit of FIG. 15, the circuit configuration of FIG. 18 does not need to be added -24-200524255 (22). Because of the circuit A, it has the advantage of smaller circuit scale. Fig. 19 shows another example of the variable delay circuit 83-2 (8 3-1, 8 3-3, 8 3-4) of Fig. 12 by way of example. A is an adding circuit, S3 is a selector, and 91-1, 91 2 are variable delay circuits. It belongs to a circuit in which a plurality of unit delay circuits are connected in cascade. However, the delay time of each unit delay circuit is controlled by changing the bias voltage Vbi as. 9 2 is a charging valve circuit, which makes V b i a s rise or fall according to the instructions of the rising signal UP and the falling signal d 0 WN. 9 3 is a phase comparison circuit that compares P2 with the phase of the signal P 2 F that passes through the variable delay circuits 91-1 and 92 _ 2. If P 2 F is delayed for P 2, the output signal u P increases Vbi as and shortens the delay time of the variable delay circuits 91-1 and 92-2. If P 2 F advances to ‘P 2, the output signal d 0 W N is output and Vbias is decreased, which delays the delay time of the variable delay circuits 91-1, 92_2. The variable delay circuits 91-1, 91-2, the charging valve 92, and the phase comparison circuit 93 can be implemented by, for example, the same circuit configuration as that of a user of an analog D1L (delay-locked loop) circuit. The operating principle of the circuit of Fig. 19 is the same as that of the circuit of Fig. 15. But using Vbias to control the delay time is different. The advantage of the circuit configuration in Figure 19 is that even if the period of the clock CLK, the voltage and temperature changes, or the process error occurs, the maximum delay time 输入 from input P2 to output P2D can be set equal to CLK. cycle. If the phases of P 2 and P 2 F are equal, the sum of the delay times of 9] — 1, 9 2 — 2 is equal to twice the period of CLK. Therefore, the maximum delay time of 200524255 (23) for P2 to P2D, that is, the delay time of 9 1 _ 1 is equal to the period of C L K. The variable delay circuits 91-2, the charging valve 92, and the phase comparison circuit 93 are circuits for measuring the period of the clock CLK. Therefore, the four variable delay circuits 83-1 to 83-4 shown in FIG. 12 can be used. — From sharing. The bias voltage Vbias generated may be distributed to the variable delay circuits 83_1 to 83_4.

於第2 0圖舉例表示第1 2圖的僞亂數產生電路8 0的 另一例。8 5乃爲僞亂數產生電路，利用與第1 3圖同樣的 電路而實現。但不需要F〔 4〕〜F〔 8〕輸出，因而也不 需要L4〜L8。Μ乃爲乘法電路、86— 1及86— 2乃爲閂 鎖電路。D3_ 1〜D3_ m乃爲單位延遲電路，屬於與第 1.5圖的D 3 — 1〜D 3 — m相同的。8 7乃爲相位比較電路， 將脈衝P1與利用D3— 1〜D3— m所延遲的各信號和P3 的相位做比較。8 8乃爲編碼器，將相位比較電路的輸出 加以編碼並形成編碼c 0 d e而輸出。編碼C 〇 d e實際上是 由複數位元所形成。 位位元者爲Mill。Mul乃是否爲k以下之値的僞亂 數。輸出將此閂鎖的信號R、F。 P 1與k個通過單位延遲電路的信號和P 3屬同相位 的情形，C 〇 d e二k。總之’ P 1和P 3乃因時脈錯開1周期 部分。Code = k和僞亂數PR相乘，僅取其上 若根據第2 0圖的電路構成，與第1 9圖的電路同樣 的，就能時脈CLK的周期和電壓、溫度產生變化’或過 -26- 200524255 (24) 程有誤差’都可將延遲時間的最大値設定爲等於CLK的 周期。原因在於C 〇 d e二k是指P 1和P 3的相位差即C L K 的周期等於單位延遲電路k個部分，第1 2圖的可變延遲 _路83一1〜83_4的延遲時間的最大値乃爲單位延遲時 間k個部分即c L K的周期。 於第21圖舉例表示第20圖的僞亂數產生電路80的 動作波形。電路85乃於每個時脈CLK的前緣（tl、t3、Fig. 20 shows another example of the pseudo-number generating circuit 80 of Fig. 12 as an example. 8 5 is a pseudo random number generating circuit, which is realized by the same circuit as in Fig. 13. However, F [4] ~ F [8] outputs are not needed, so L4 ~ L8 are not needed. M is a multiplication circuit, and 86-1 and 86-2 are latch circuits. D3_ 1 to D3_ m are unit delay circuits, and belong to the same as D 3 — 1 to D 3 — m in Fig. 1.5. 8 7 is a phase comparison circuit that compares the pulse P1 with the phase of each signal delayed by D3-1 to D3-m and the phase of P3. 8 8 is an encoder that encodes the output of the phase comparison circuit to form a code c 0 d e and outputs it. The code C 0 d e is actually formed by the complex bits. The bit is Mill. Mul is a pseudo-random number that is below k. The signals R and F which latch this are output. In the case where P 1 and k signals passing through the unit delay circuit and P 3 are in phase, Co d e 2 k. In short, 'P 1 and P 3 are shifted by one cycle due to the clock. Code = k is multiplied by the pseudo-random number PR. If only the circuit configuration shown in FIG. 20 is used, the same as the circuit shown in FIG. 19 can change the period, voltage, and temperature of the clock CLK. After -26- 200524255 (24) if there is an error ', the maximum delay time can be set to a period equal to CLK. The reason is that C ode k refers to the phase difference between P 1 and P 3, that is, the period of CLK is equal to k parts of the unit delay circuit. The delay time of the variable delay _ road 83 1 ~ 83_4 in Fig. 12 is the largest. It is the cycle of k parts per unit delay time, which is c LK. Fig. 21 shows an example of an operation waveform of the spurious number generating circuit 80 of Fig. 20. Circuit 85 is at the leading edge (tl, t3,

t5.......)生成新的僞亂數 PR ( rl、r2、r3.......)。 另一方面，編碼器的輸出Code則每當脈衝P3變爲高位 準時即產生變化（C 1 ' C 2.......)。乘法電路的輸出 M u 1乃以11、13、15.......產生變化。輸出F乃將此以 CLK的拖後緣（t2、t4、t6.......）做閂鎖，輸出R乃更 將此以CLK的前緣（t3、t5、t7.......)做閂鎖。 若根據第2 0圖的僞亂數產生電路8 0，即具有對時脈 CLK的周期和電壓、溫度的變化之應答較快的優點。顯 示時脈CLK周期的信號Code乃每兩個循環即被更新。 於第2 2圖舉例表示第I 1圖的相位隨機化電路8的 另一例。在該例中，沒有時脈輸入，在內部經由自激振 盪製作時脈。即，藉由以m個單位延遲電路D 3 一 1〜D 3 —m和反及閘N AN D所構成的環形振盪器產生時脈。以 選擇器S 1隨機的選出m個輸出中的一個，藉此令時脈的 相位隨機化。EN乃爲允許信號’以此爲高位準’藉此產 生自激振盪。 於第2 3 A圖及第2 3 B圖乃表不將晶載有關本發明的 -27> 200524255 (25) 降壓電路的半導體積體電路與電容器一同密封於同一封 裝的例子。在與第7圖、第8圖相同，或相當的電路部 分附加同一參考符號。第2 3 A圖乃使L S I晶片1 0和電容 器2 3相鄰接而配置，且其間利用銲接線〗〇3連接。第 23 B圖乃於設置在LSI晶片1〇上的銲墊1〇5上中介著銲 球106而載置電容器23。23乃爲第8圖的電容器23— 0 〜2 3— 4的總稱。1 〇〇乃爲多層配線基板等的配線基板、 1 〇 1乃爲模組樹脂。藉由採用於同圖所示的密封構造，不 需將電容器實裝於基板2 0上，能減低基板2 0上的實裝 面積。密封於封裝的電容器23不需要全部的電容器23_ 0〜23— 4。例如可以只要23— 1〜23— 4。 於第24A圖、第24B圖表示在引線端子之上搭載電 容器的例子。第24A圖是表示縱斷面圖、第24B圖是表 示平面圖。在此降壓電路乃具有兩個開關陣列5 _ 1、5 _ 2。23 — 1、23— 2乃爲連接於如第7圖所示的銲墊CPi、 C M i的電容器。1 0 7乃爲絕緣帶、1 1 0乃爲引線。即使根 據此種構成還是可減低基板20上的實裝面積。採用第 2 4 A圖、第2 4 B圖之構成的情形，希望鄰接欲外置電容 器的接合墊CPi、CMi。藉由鄰接，不但實裝很容易，也 能減低寄生電感。 前述開關電容式降壓電路的電容器對LSI晶片1〇而 言並不限於外置電容器2 3 ( 2 3 — 1，23〜2)。特別是雖 然圖未表示，但也可爲LSI晶片10的晶載電容器。晶載 電容器乃以MOS電晶體的閘極電極作爲其中一方的電容 -28- 200524255 (26) 電極，也能利用以共通源極、汲極作爲另一方的電容電 極的MO S容量，或是以多結晶矽等作爲電極的電容所構 成。 於第2 5圖舉例表示使用具有利用本發明的降壓電路 的半導體積體電路的攜帶電話機的邏輯構成。於應用處 理器250及基頻部240搭載降壓電路241、251。200乃 爲天線、210乃爲發送/接收切換電路、220乃爲發送用 放大器（high power amplifier) 、23 0 乃爲高頻部、240 乃爲基頻部、250乃爲應用處理器。241乃爲內裝於基頻 部240的降壓電路、251乃爲內裝於應用處理器250的降 壓電路。2 6 0乃爲液晶顯示部、2 7 0乃爲鋰電池、2 8 0乃 爲電源1C。電源IC2 80乃以例如串聯式降壓電路所構成 。290乃爲DC/ DC換流器、3 0 0乃爲時脈發生器、310 及3 20乃爲記億體例如快閃記憶體和SRAM。 以時脈發生器3 0 0所發生的系統時脈S C L K乃形成 系統時脈供給到RF部2 3 0、基頻部240、及應用處理器 2 5 0。搭載於應用處理器2 5 0的降壓電路2 5 1乃利用這個 使開關電容式降壓電路動作。即，降壓電路2 5〗則利用 基頻和與應用處理器相同的頻率進行動作。藉此，經由 降壓電路2 5 1之動作所產生的雜訊因成爲與基頻和應用 處理器所產生的雜訊相同的頻率，故特別亦可施行如第 1 1圖的時脈的相位隨機化。 當應用處理器停止時，時脈SCLK的供給也會停止 。藉此開關電容式降壓電路雖不會產生動作，但輸出電 -29- 200524255 (27) 壓可經由並聯的串聯式降壓電路被保持。有關搭載於基 頻部的降壓電路24 1也是同樣的。 說明有關電池2 7 0至降壓電路2 5 1的輸出的電力轉 換效率和電池壽命的計算例。先做以下的假定。鋰電池 270 的輸出二3.7V、鋰電池的電容= 600mAb、電源 IC280的輸出= 2.8V、降壓電路251的輸出=1·〇ν、應用 處理器的消耗電流=20 0mA、其它的LSI爲待機狀態（ 消耗電流〜0 )。 不採用本發明只採用串聯式降壓電路的情形，電力 轉換效率=1 ·0/ 3.7 = 27%、電池的輸出電流=200mA、 電池命=3小時。 採用本1發明的情形（開關電容式電路的效率假定爲 90%)，電力轉換效率=1.0/3.7x2x90% = 49%、電 池的輸出電流= 200/2/90% = 111mA、電池壽命=5.4 小時。藉由採用本發明，電池的壽命可延長1 . 8倍。 第2A圖的例子乃爲降壓比大約爲2 : 1。除此以外 的例子，第26圖乃表示降壓比爲3 : 1、第27圖乃表示 降壓比爲3 : 2時的開關陣列的電路圖。c P 1 1、C Μ 1 ' CP 1 2、CM 1 2乃爲欲外置電容器（開關電容）的端子。控 制信號SA、SC、SB的動作波形乃爲與第2B圖相同。特 別是雖然圖未表示，但於第2 6圖中，降壓比爲1 / 3時 ，串聯兩個開關電容和一個平滑電容並充電，然後並聯 三個電容亦可。於第27圖中，降壓比爲2/3時，如第 3 3圖舉例所示，最初並聯開關電容c 1和C 2，將此串聯 -30- 200524255 (28) 於平滑電容C0並充電，然後串聯開關電容c 1和C2 ,於 此並聯平滑電容C 0亦可。 於第29圖詳細舉例表示第25圖的應用處理器250。 251乃爲利用本發明的降壓電路。252乃爲應用處理器 2 5 0的磁心電路，以降壓電源VDD作爲動作電源並產生 動作。253乃爲輸出入電路，以輸出入電路用的電源 VCCQ作爲動作電源並產生動作。輸出入電路用的電源 VCCQ乃爲電壓位準與VCCP、VCCA相同，但爲了防止 在輸出電路所發生的電源雜訊傳遞到其它電路部分，故 電源與其它分開。輸出入電路253乃包括系統時脈SCLK 的輸入電路。與所輸入的系統時脈S C L K同步並輸出磁 心電路，25 2用的時脈CCLK(電壓位準乃爲 VDD)、及 降壓電路251用的時脈CLK(電壓位準乃爲VCCQ)。 輸出入電路253當然也具備其它信號用的輸入電路及輸 出電路但在此省略記載。2 5 4乃爲檢測電源電壓投入的電 源Ο N檢測電路。此乃檢測電源VCCA的上升，且生成 磁心電路2 5 2的重置信號RS T及降壓電路2 5 1的允許信 號EN2。允許信號EN2乃藉由以延遲電路延遲而生成允 許信號EN1。 有關半導體積體電路之燒上時，輸出電壓VDD比普 通還高的手法而示之。爲了實現這個，基準電壓 VREF 亦可於燒上時升高。實現手法乃爲如第3 1 A圖和第3 1 B 圖之兩圖所示。於各圖中，N乃爲普通動作時的動作點 (VCC-VCC1 > VREF-VREF1) ，B乃爲燒上時的動作 200524255 (29) 點（VCC 二 VCC2、VREF = VREF2 )。動作點 N、B 均比 VREF = VCC / 2的直線（圖中的中心線）還要下面即可 〇 第1實現方法乃爲普通動作時，VREF對VCC而言 形成安定化，VCC比普通還高的話，VREF也隨著變高 。此即可應用日本特許第 2 6 8 5 469號所記載的技術而實 現。第2實現方法亦能以普通動作模式和燒上模式切換 VREF的位準。 於第32圖舉例表示欲實現第31B圖之手法的基準電 壓產生電路1。3 0乃爲能帶間隙電路，產生不依賴溫度 和電源電壓的安定電壓V B Gr。3 i乃爲電壓位準轉換電 路，由差動放大器 32、P'通道“〇3電晶體1^30、電阻 Rl、R2、R3及切換開關33所形成，電壓VBGR同時產 生基準電壓 VREF。根據模式切換信號Mode，改變取出 基準電壓VREF的最高位置。 以上根據本發明人所創作的發明基於實施形態做具 體說明，但本發明並不限於此，當然在不脫離其主旨的 範圍內可做各種變更。 例如在L S I上搭載複數開關電容式電路的情形’根 據動作模式只使其中一部分動作亦可。對應於動作模式 就能更加減低消耗電流。或者對應於動作模式而令消耗 電流最適化。 於系統所用的複數個L S I中的一個搭載降壓電路’ 且亦可將在此所產生的電壓供給到其它L S I。特別是如果 200524255 (30) 適用於在一個封裝內密封複數個L S I晶片的多晶片模組 (MCM)具有很大效果。 本發明不光是僅與電路模組一同集積形式的半導體 積體電路，也適用於像如單獨的電壓轉換I C的半導體裝 置。 【圖式簡單說明】 【第1圖】舉例表示有關本發明的半導體積體電路 配備於晶片內的降壓電路的方塊圖。 【第2A圖】包含於降壓電路的開關陣列的電路圖。 【第2B圖】表示第2A圖針對開關陣列的開關控制 計時的計時圖。 【第 3圖】舉例表示串聯式降壓電路的詳細電路圖 〇 【第4圖】舉例表示位準感測器的詳細電路圖。 【第5圖】舉例表示開關控制電路的詳細邏輯電路 圖。 [第6圖】舉例表示降壓電路的電源上升時的動作 波形的計時圖。 【第7圖】舉例表示降壓電路的LSI晶片內配置的 佈置圖。 【第8圖】舉例表示搭載降壓電路的半導體積體電 路實裝於配線基板狀態的平面圖。 【第9圖】表示有關本發明的半導體積體電路配備 - 33- 200524255 (31) 於晶片內的降壓電路的第2例的方塊圖。 【第1 0圖】舉例表示第9圖的開關控制電路的詳細 邏輯電路圖。 [第1 1圖】表示有關本發明的半導體積體電路配備 於晶片內的降壓電路的第3例的方塊圖。 【第1 2圖】舉例表示相位隨機化電路的邏輯構成的 邏輯電路圖。 【第1 3圖】舉例表示第1 2圖的僞亂數產生電路的 邏輯構成的邏輯電路圖。 【第1 4圖】舉例表示第1 2圖的單發脈衝產生電路 的邏輯構成的邏輯電路圖。 【第15圖】·舉例表示第12圖的可變延遲電路的邏 輯橇成的邏輯電路圖。 【第1 6圖】舉例表示第1 2圖的時脈合成電路的邏輯構 成的邏輯電路圖。 【第1 7圖】舉例表示第1 2圖的相位隨機化電路的 1力作波形的計時圖。 【第18圖】表示第12圖的可變延遲電路的另一例 的邏輯電路圖。 【第19圖】表示第12圖的可變延遲電路的更另一 例的邏輯電路圖。 【第20圖】表示第12圖的僞亂數產生電路的另一 例的邏輯電路圖。 【第2 1圖】舉例表不第2 0圖的僞亂數產生電路的 -34 - 200524255 (32) 動作波形的計時圖。 【第22圖】表示第1 1圖的相位隨機化電路的另一 例的邏輯電路圖。 【第2 3 A圖】表示將晶載有關本發明的降壓電路的 半導體積體電路與電容器一同密封於同一封裝的第1例 的縱斷面圖。 【第2 3 B圖】表示將晶載有關本發明的降壓電路的 半導體積體電路與電容器一同密封於同一封裝的第2例 的縱斷面圖。 【第24A圖】與晶載有關本發明的降壓電路的半導 體積體電路一同在引線端子之上搭載電容器而樹脂密封 之例的縱斷面圖。 , 【第24B圖】爲第24A圖的平面圖。 【第2 5圖】舉例表示使用具有利用本發明的降壓電 路的半導體積體電路的攜帶電話機的邏輯構成方塊圖。 【第2 6圖〕表示降壓比爲3 ·· 1時的開關陣列的構 成電路圖。 【第2 7圖】表示降壓比爲3 : 2時的開關陣列的構 成電路圖。 【第28圖】等效地表示第2A圖的切換電路的說明 圖。 【第2 9圖】舉例表示第2 5圖的應用處理器2 5 0的 詳細方塊圖。 【第3 0圖】舉例表示第1 〇圖的開關控制電路的動 -35- 200524255 (33) 作波形的計時圖。 [第31A圖】電源電壓比普通還高的話，基準電壓 也會隨著升高而使基準電壓對應於燒上時的高電壓時的 方式說明圖。 【第3 1 B圖】以普通動作模式和燒上模式切換基準 電壓之位準，並令基準電壓對應於燒上時的高電壓時之 方式說明圖。 【第32圖】舉例表示欲實現第31B圖之方法的基準 電壓產生電路的電路圖。 【第33圖】表示於第27圖中形成降壓比2/ 3時的 電容連接形態的等效電路圖。 【主要元件符號說明】 1 基準電壓產生電路 2 串聯式降壓電路 3 位準感測器 4 開關控制電路 5 — 1〜5 — η 開關陣列 6 開關電容式降壓電路 8 相位隨機化電路 VCCP 輸入電壓 VDD 降壓電壓 V S S 接地電壓 CP、CM 電容器連接用外部端子 200524255 (34) ΕΝ 1 開關電容式降壓電路允許信號 ΕΝ2 串聯式降壓電路允許信號 CLK 時脈 STOPB 停止信號 10 L S I晶片 11 接合墊 VCCP1〜VCCP4 輸入電壓VCCP用接合墊 VDD1〜VDD4 降壓電壓用接合墊 VSS1〜VSS4 接地電壓用接合墊 12 磁心電路部 13 I/O區域 14 基準電壓產生電路、串聯式，降壓電路、位準感測器 及開關控制電路的配置區域。 20 基板 2 1 L S I封裝 2 2 L S I端子 23— 0〜23—4 電容器 2 4 基板上V C C配線 25 基板上接地配線 26 基板上VDD配線 100 基板 101 模組樹脂 102 ^ 103 銲接線 10 4 端子 -37 - 200524255 (35) 1 05 銲墊 1 0 6 銲球 110 引線 2 0 0 天線 210 發送/接收切換電路 220 發送用放大器 23 0 高頻部t5 .......) generates a new pseudo-random number PR (rl, r2, r3 ...). On the other hand, the output Code of the encoder changes every time the pulse P3 goes high (C 1 'C 2 .......). The output M u 1 of the multiplication circuit is changed by 11, 13, 15,... The output F is latched by the trailing edges of CLK (t2, t4, t6 ...), and the output R is further latched by the leading edges of CLK (t3, t5, t7 ... ...) do the latch. If the pseudo-random number generating circuit 80 according to FIG. 20 is used, it has the advantage that the response to the period of the clock CLK and the changes in voltage and temperature is fast. The signal code showing the clock CLK cycle is updated every two cycles. Fig. 22 shows another example of the phase randomization circuit 8 of Fig. 11 as an example. In this example, there is no clock input, and the clock is generated internally via self-excited oscillation. That is, a clock is generated by a ring oscillator composed of m unit delay circuits D 3-1 to D 3 -m and a reverse gate N AN D. The selector S 1 randomly selects one of the m outputs, thereby randomizing the phase of the clock. EN is to allow the signal ‘to this high level’ to generate self-excited oscillation. Figures 2A and 2B are examples in which the semiconductor integrated circuit of the step-down circuit and the capacitor are sealed together in the same package with -27 > 200524255 (25). The same reference numerals are given to the same or equivalent circuit parts as those in Figs. 7 and 8. Figure 2 3A shows that the L S I chip 10 and the capacitor 23 are arranged adjacent to each other, and the bonding wires are connected between them. FIG. 23B is a general term for capacitors 23-0 to 23-4 in FIG. 8 with capacitors 23 interposed on solder pads 105 provided on the LSI wafer 10 with the solder balls 106 interposed therebetween. 100 is a wiring board such as a multilayer wiring board, and 101 is a module resin. By adopting the sealing structure shown in the figure, the capacitor does not need to be mounted on the substrate 20, and the mounting area on the substrate 20 can be reduced. The capacitors 23 sealed in the package do not need all the capacitors 23_ 0 to 23-4. For example, 23-1 to 23-4 may be required. Figures 24A and 24B show an example in which a capacitor is mounted on a lead terminal. Fig. 24A is a longitudinal sectional view, and Fig. 24B is a plan view. Here, the step-down circuit has two switch arrays 5 _ 1, 5 _ 2. 23 — 1, 23 — 2 are capacitors connected to the pads CPi and C M i as shown in FIG. 7. 1 0 7 is an insulating tape, and 1 10 is a lead. Even with this configuration, the mounting area on the substrate 20 can be reduced. In the case of the structure shown in Figs. 24A and 24B, it is desirable to adjoin the bonding pads CPi and CMi of the capacitor to be externally mounted. Adjacent not only makes it easy to install, but also reduces parasitic inductance. The capacitor to the LSI chip 10 of the aforementioned switched capacitor buck circuit is not limited to the external capacitor 2 3 (2 3-1, 23 to 2). In particular, although it is not shown in the figure, it may be a chip capacitor on the LSI chip 10. The chip capacitor uses the gate electrode of the MOS transistor as one of the capacitors. 28- 200524255 (26) electrode, can also use the MOS capacity with a common source and drain as the other capacitor electrode, or Polycrystalline silicon and other capacitors. Fig. 25 shows an example of a logical configuration of a mobile phone using a semiconductor integrated circuit using a step-down circuit of the present invention. The application processor 250 and the baseband unit 240 are equipped with step-down circuits 241 and 251. 200 is an antenna, 210 is a transmission / reception switching circuit, 220 is a high power amplifier for transmission, and 23 0 is a high frequency The unit, 240 is the baseband unit, and the 250 is the application processor. 241 is a step-down circuit built into the baseband section 240, and 251 is a step-down circuit built into the application processor 250. 2 6 0 is a liquid crystal display, 2 7 0 is a lithium battery, and 2 8 0 is a power source 1C. The power supply IC2 80 is constituted by, for example, a series step-down circuit. 290 is a DC / DC converter, 300 is a clock generator, and 310 and 320 are billions of memory such as flash memory and SRAM. The system clock S C L K generated by the clock generator 3 0 is a system clock which is supplied to the RF section 230, the fundamental frequency section 240, and the application processor 250. The step-down circuit 2 51 installed in the application processor 2 50 uses this to operate a switched capacitor type step-down circuit. That is, the step-down circuit 25 operates using the base frequency and the same frequency as the application processor. As a result, the noise generated by the operation of the step-down circuit 2 51 is the same frequency as the noise generated by the base frequency and the application processor. Therefore, the phase of the clock as shown in FIG. 11 can also be implemented. Randomize. When the application processor stops, the supply of the clock SCLK will also stop. Thus, although the switched-capacitor step-down circuit does not operate, the output voltage can be maintained through a parallel series-type step-down circuit. The same applies to the step-down circuit 241 provided in the baseband section. A calculation example of the power conversion efficiency and battery life of the output from the battery 270 to the step-down circuit 251 will be described. Make the following assumptions. The output of the lithium battery 270 is 3.7V, the capacity of the lithium battery = 600mAb, the output of the power supply IC280 = 2.8V, the output of the step-down circuit 251 = 1 · 〇ν, the current consumption of the application processor = 200mA, and other LSIs are Standby state (current consumption ~ 0). In the case where the present invention is not adopted and only a series step-down circuit is adopted, the power conversion efficiency = 1 · 0 / 3.7 = 27%, the battery output current = 200mA, and the battery life = 3 hours. In the case of the invention 1 (the efficiency of the switched capacitor circuit is assumed to be 90%), the power conversion efficiency = 1.0 / 3.7x2x90% = 49%, the output current of the battery = 200/2/90% = 111mA, and the battery life = 5.4 hour. By using the present invention, the battery life can be extended by 1.8 times. The example in Figure 2A is a step-down ratio of approximately 2: 1. In other examples, Fig. 26 is a circuit diagram of a switch array when the step-down ratio is 3: 1, and Fig. 27 is a step-down ratio of 3: 2. c P 1 1, C M 1 'CP 1 2, CM 1 2 are terminals for external capacitors (switched capacitors). The operation waveforms of the control signals SA, SC, and SB are the same as those in FIG. 2B. In particular, although not shown in the figure, when the step-down ratio is 1/3 in Figure 26, two switched capacitors and one smoothing capacitor are connected in series and charged, and then three capacitors can be connected in parallel. In Figure 27, when the step-down ratio is 2/3, as shown in the example in Figure 33, the switching capacitors c 1 and C 2 are initially connected in parallel, and this is connected in series -30- 200524255 (28) in the smoothing capacitor C0 and charged. , And then switch capacitors c 1 and C2 in series, and a parallel smoothing capacitor C 0 may also be connected in parallel here. The application processor 250 of FIG. 25 is illustrated in detail in FIG. 29. 251 is a step-down circuit using the present invention. 252 is a magnetic core circuit of the application processor 250, which uses a step-down power supply VDD as an operating power source and generates an action. 253 is an input / output circuit, and a power source VCCQ for the input / output circuit is used as an operation power source to generate an operation. The power supply for the input and output circuits VCCQ has the same voltage level as VCCP and VCCA. However, in order to prevent the power noise generated in the output circuit from being transmitted to other circuit parts, the power supply is separated from the others. The input / output circuit 253 is an input circuit including a system clock SCLK. It is synchronized with the input system clock S C L K and outputs the core circuit. The clock CCLK (the voltage level is VDD) for 25 2 and the clock CLK (the voltage level is VCCQ) for the step-down circuit 251. Of course, the input / output circuit 253 also includes input circuits and output circuits for other signals, but the description is omitted here. 2 5 4 is a power source 0 N detection circuit for detecting the power supply voltage. This is to detect the rise of the power supply VCCA and generate a reset signal RST of the core circuit 2 5 2 and an enable signal EN2 of the step-down circuit 2 5 1. The enable signal EN2 generates the enable signal EN1 by being delayed by a delay circuit. When the semiconductor integrated circuit is burned, the output voltage VDD is higher than the conventional method. To achieve this, the reference voltage VREF can also be raised during burn-in. The implementation method is as shown in the two diagrams of Figure 31A and Figure 31B. In each figure, N is the action point during normal operation (VCC-VCC1 > VREF-VREF1), and B is the action during burn-in 200524255 (29) points (VCC2 VCC2, VREF = VREF2). Both the operating points N and B can be lower than the straight line of VREF = VCC / 2 (the center line in the figure). When the first implementation method is a normal action, VREF becomes stable for VCC, and VCC is more stable than normal. If it is high, VREF also goes high. This can be achieved by applying the technology described in Japanese Patent No. 2 6 8 5 469. The second implementation method can also switch the level of VREF in normal operation mode and burn-in mode. Fig. 32 shows an example of a reference voltage generating circuit 1.30 which is a method for realizing the method shown in Fig. 31B. The band gap circuit 30 generates a stable voltage V B Gr independent of temperature and power supply voltage. 3 i is a voltage level conversion circuit, which is formed by the differential amplifier 32, the P ′ channel “〇3 transistor 1 ^ 30, the resistors R1, R2, R3, and the switch 33, and the voltage VBGR also generates a reference voltage VREF. According to The mode switching signal Mode changes the highest position for taking out the reference voltage VREF. The invention according to the invention created by the present inventors has been specifically described based on the embodiment, but the present invention is not limited thereto, and of course, various kinds can be made without departing from the scope of the invention Change. For example, when multiple switched capacitor circuits are mounted on an LSI, 'only a part of them may be operated depending on the operation mode. The current consumption can be further reduced according to the operation mode. Or the current consumption can be optimized according to the operation mode. One of the plurality of LSIs used in the system is equipped with a step-down circuit, and the voltage generated here can also be supplied to other LSIs. Especially if 200524255 (30) is suitable for a multi-chip that seals a plurality of LSI chips in one package The module (MCM) has a great effect. The present invention is not only a semiconductor integrated circuit which is integrated only with a circuit module It is also suitable for a semiconductor device such as a separate voltage conversion IC. [Brief Description of the Drawings] [Figure 1] A block diagram showing a step-down circuit in which a semiconductor integrated circuit of the present invention is provided in a chip. [Section 2A Figure] A circuit diagram of a switch array included in a step-down circuit. [Figure 2B] shows the timing chart for switching control timing of the switch array in Figure 2A. [Figure 3] A detailed circuit diagram of a series buck circuit is shown as an example. Fig. 4 shows an example of a detailed circuit diagram of a level sensor. [Fig. 5] shows an example of a detailed logic circuit diagram of a switch control circuit. [Fig. 6] An example of a timing chart showing the operation waveform of a step-down circuit when the power supply is rising. [Figure 7] An example of the layout of a step-down circuit in an LSI chip. [Figure 8] An example of a plan view showing a state where a semiconductor integrated circuit equipped with a step-down circuit is mounted on a wiring board. [Figure 9] -33- 200524255 (31) A block diagram showing a second example of a step-down circuit provided in a chip in the semiconductor integrated circuit of the present invention. [Fig. 10] An example showing the ninth The detailed logic circuit diagram of the switch control circuit shown in the figure. [Figure 11] A block diagram showing a third example of the step-down circuit in which the semiconductor integrated circuit of the present invention is provided in a chip. [Figure 12] An example showing a phase Logic circuit diagram of the logic structure of the randomization circuit. [Figure 13] A logic circuit diagram showing the logic structure of the pseudo-random number generating circuit of Figure 12 [Figure 14] shows a single shot of Figure 12 as an example. Logic circuit diagram of the logic structure of the pulse generating circuit. [Fig. 15] · An example of a logic circuit diagram of the variable delay circuit of Fig. 12 [Fig. 16] An example of the clock synthesis of Fig. 12 A logical circuit diagram of the logic of a circuit. [Fig. 17] An example of a timing chart of one-force waveform of the phase randomization circuit of Fig. 12 is shown. [Fig. 18] A logic circuit diagram showing another example of the variable delay circuit of Fig. 12. [Fig. [Fig. 19] A logic circuit diagram showing still another example of the variable delay circuit of Fig. 12. [Figure 20] A logic circuit diagram showing another example of the pseudo-random number generating circuit shown in Figure 12. [Figure 21] -34-200524255 (32) Timing chart of the operation waveform of the spurious number generating circuit in Figure 20 is shown as an example. [Fig. 22] A logic circuit diagram showing another example of the phase randomization circuit of Fig. 11. [Figure 2A] A longitudinal sectional view showing a first example in which a semiconductor integrated circuit on which a step-down circuit according to the present invention is mounted on a chip is sealed together with a capacitor in the same package. [Fig. 2 3B] A longitudinal sectional view showing a second example in which a semiconductor integrated circuit on which a step-down circuit according to the present invention is mounted on a chip is sealed together with a capacitor in the same package. [Fig. 24A] A longitudinal sectional view of an example in which a capacitor is mounted on a lead terminal and a resin is sealed together with a semiconducting bulk body circuit related to the step-down circuit of the present invention on a wafer. [Figure 24B] is a plan view of Figure 24A. [Figure 25] A block diagram showing a logical configuration of a mobile phone using a semiconductor integrated circuit using a step-down circuit of the present invention. [Fig. 26] A circuit diagram showing the structure of a switch array when the step-down ratio is 3 ·· 1. [Fig. 27] A circuit diagram showing the structure of a switch array when the step-down ratio is 3: 2. [Fig. 28] An explanatory diagram equivalently showing the switching circuit of Fig. 2A. [Fig. 29] A detailed block diagram of the application processor 250 in Fig. 25 is shown as an example. [Fig. 30] An example showing the timing of the switch control circuit in Fig. 10 -35- 200524255 (33). [Fig. 31A] If the power supply voltage is higher than normal, the reference voltage will also increase and the reference voltage will correspond to the high-voltage mode at the time of burning. [Fig. 3 1B] An explanatory diagram of the method of switching the reference voltage level in the normal operation mode and the burn-in mode, and making the reference voltage correspond to the high voltage when burned. [Fig. 32] An example circuit diagram of a reference voltage generating circuit for implementing the method of Fig. 31B. [Fig. 33] An equivalent circuit diagram showing a capacitor connection form when a step-down ratio of 2/3 is formed in Fig. 27. [Description of main component symbols] 1 Reference voltage generation circuit 2 Series voltage step-down circuit 3 Level sensor 4 Switch control circuit 5 — 1 ~ 5 — η Switch array 6 Switched capacitor step-down circuit 8 Phase randomization circuit VCCP input Voltage VDD Step-down voltage VSS Ground voltage CP, CM External terminal for capacitor connection 200524255 (34) ENE 1 Switched-capacitor step-down circuit enable signal EN 2 Series-type step-down circuit enable signal CLK Clock STOPB Stop signal 10 LSI chip 11 Bonding pad VCCP1 to VCCP4 Input voltage VCCP bonding pads VDD1 to VDD4 Step-down voltage bonding pads VSS1 to VSS4 Ground voltage bonding pads 12 Core circuit section 13 I / O area 14 Reference voltage generation circuit, series type, step-down circuit, level Configuration area for sensors and switch control circuits. 20 Substrate 2 1 LSI package 2 2 LSI terminal 23-0 ~ 23-4 Capacitor 2 4 VCC wiring on the substrate 25 Ground wiring on the substrate 26 VDD wiring on the substrate 100 Substrate 101 Module resin 102 ^ 103 Welding wire 10 4 Terminal-37 -200524255 (35) 1 05 Pad 1 0 6 Solder ball 110 Lead 2 0 0 Antenna 210 Transmit / receive switching circuit 220 Transmit amplifier 23 0 High-frequency section

24 0 基頻部 25 0 應用處理器 241、 251 降壓電路 2 5 2 處理器的磁心電路部 2 5 3 輸出入電路 2.5 4 電源ON檢測電路 2.5 0 液晶顯不部 27 0 _電池24 0 Fundamental frequency section 25 0 Application processor 241, 251 Step-down circuit 2 5 2 Core circuit section of processor 2 5 3 I / O circuit 2.5 4 Power ON detection circuit 2.5 0 LCD display section 27 0 _Battery

3 0 0 時脈發生器 3 10' 3 2 0 記憶體 -38-3 0 0 Clock generator 3 10 '3 2 0 Memory -38-

Claims (1)

(1) (1)200524255 十、申請專利範圍 1. 一種半導體電路裝置，其特徵爲： . 具有使外部電源電壓降壓而生成降壓電壓的降壓部 . ，且前述降壓部具有：開關電容式降壓電路及串聯穩壓 式降壓電路’各個降壓電路的降壓電壓輸出端子則共通 連接。 2 ·如申請專利範圍第1項所記載的半導體電路裝置 ’其中’具有外部電源電壓投入時，先開始前述串聯穩 · 壓式降壓電路的降壓動作，然後開始開關電容式降壓電 路之降壓動作的起動控制電路。 3 ·如申請專利範圍第2項所記載的半導體電路裝釐 ’其中，前述起動控制電路開f始開關電容式降壓電路之 降壓動作後，即停止串聯穩壓式降壓電路的降壓動作。 4 ·如申請專利範圍第1項所記載的半導體電路裝置 ’其中，開關電容式降壓電路乃於充放電循環中使得切 換電容器連接狀態的計時隨機化。 0 5 ·如申請專利範圍第4項所記載的半導體電路裝置 ’其中，開關電容式降壓電路乃具有欲使得前述切換計 時隨機化的亂數產生電路，且使用所產生的亂數來選擇 切換電容器連接狀態的計時。 6 ·如申請專利範圍第1項所記載的半導體電路裝置 * ’其中，開關電容式降壓電路的電容器是屬於外置電容 器。 # 7 .如申請專利範圍第1項所記載的半導體電路裝置 -39- 200524255 (2) ，其中，開關電容式降壓電路的電容器是屬於晶載電容 器。 8 .如申請專利範圍第1項所記載的半導體電路裝置 ，其中，具有將降壓電壓供給到半導體積體電路外部的 外部電源供給端子。 9 ·如申請專利範圍第1項所記載的半導體電路裝置 ，其中， 前述開關電容式降壓電路乃爲能將降壓電壓可變j空 制的應用於老化。 10·—種半導體電路裝置，其特徵爲： 具有使得形成在半導體晶片的外部電源電壓降壓而 生成降壓電壓的降壓部.，前述降壓部乃具有開關電容式 降壓電路，且將構成開關電容式降壓電路的開關陣列分 割爲複數個而離間配置，在各個開關陣列個別連接固有 的開關電容，平滑電容就會共通連接。 η .如申請專利範圍第1 〇項所記載的半導體電路裝 置’其中’前述開關電容和平滑電容是被外置在半導體 晶片。 1 2 .如申請專利範圍第1 〇項所記載的半導體電路裝 置，其中，前述開關電容和平滑電容是被晶載在半導轉 晶片。 1 3 ·如申請專利範圍第丨〇項所記載的半導體電路裝 置，其中，具有於充放電循環中控制利用前述開關陣的 平滑電容和開關電容之連接切換計時的降壓控制電路， -40 - 200524255 (3) 前述降壓控制電路是針對複數個開關陣列錯開切換計時 而加以控制。 1 4 .如申請專利範圍第1 3項所記載的半導體電路裝 置，其中，前述降壓控制電路是對每個開關陣列生成錯 開相位的時脈信號，基於所生成的各個時脈信號而令前 述連接切換計時於每個開關陣列隨機化。 1 5 .如申請專利範圍第1 4項所記載的半導體電路裝 置，其中，前述降壓控制電路乃具有欲令前述切換計時 隨機化的亂數產生電路，使用所產生的亂數來選擇前述 連接切換計時。 1 6 ·如申請專利範圍第1 〇項所記載的半導體電路裝 置，其中，前述，開關陣列是被配置在前述半導體晶片的 外部連接電極形成區域的近傍。 1 7 .如申請專利範圍第丨6項所記載的半導體電路裝 置，其中，控制複數個前述開關陣列之開關動作的降壓 控制電路則被複數個前述開關陣列共通化，並自前述開 關陣列被離間配置。 1 8 ·如申請專利範圍第1 3項所記載的半導體電路裝 置，其中，與前述降壓控制電路一同具有串聯穩壓式降 壓電路，前述開關電容式降壓電路和串聯穩壓式降壓電 路的降壓電壓輸出端子則被共通連接。 1 9 .如申請專利範圍第1 8項所記載的半導體電路裝 置，其中，具有外部電源電壓投入時，先開始前述串聯 穩壓式降壓電路的降壓動作，然後開始開關電容式降壓 -41 - 200524255 (4) 電路之降壓動作的起動控制電路。 2 0.—種資料處理系統，其特徵爲： 搭載申請專利範圍第1項所記載的半導體電路裝置 ，被電池驅動。(1) (1) 200524255 X. Patent application scope 1. A semiconductor circuit device, characterized in that:. It has a step-down section that generates a step-down voltage by stepping down the external power supply voltage, and the step-down section has: a switch Capacitive step-down circuit and series regulated step-down circuit. The step-down voltage output terminals of each step-down circuit are connected in common. 2 · When the semiconductor circuit device 'where' has the external power supply voltage input as described in item 1 of the scope of the patent application, the aforementioned step-down operation of the series stable-voltage step-down circuit is started, and then the switching capacitor-type step-down circuit is started. Step-down start control circuit. 3 · The semiconductor circuit device described in item 2 of the scope of the patent application, wherein the start-up control circuit starts the step-down operation of the switched-capacitor step-down circuit, and then stops the step-down of the series-regulated step-down circuit. action. 4 · The semiconductor circuit device described in item 1 of the scope of the patent application ′, wherein the switched capacitor step-down circuit randomizes the timing of the connection state of the switching capacitor during the charge and discharge cycle. 0 5 · The semiconductor circuit device described in item 4 of the scope of the patent application, wherein the switched-capacitor step-down circuit has a random number generating circuit that randomizes the aforementioned switching timing, and uses the generated random number to select switching Timing of capacitor connection status. 6 · The semiconductor circuit device described in item 1 of the patent application scope * ′, wherein the capacitor of the switched capacitor type buck circuit is an external capacitor. # 7. The semiconductor circuit device described in item 1 of the scope of patent application -39- 200524255 (2), wherein the capacitor of the switched capacitor step-down circuit is a crystal capacitor. 8. The semiconductor circuit device according to item 1 of the patent application scope, further comprising an external power supply terminal for supplying a step-down voltage to the outside of the semiconductor integrated circuit. 9. The semiconductor circuit device according to item 1 of the scope of the patent application, wherein the aforementioned switched capacitor type buck circuit is used for aging by applying a variable step-down voltage j blanking. 10 · A semiconductor circuit device, comprising: a step-down section for generating a step-down voltage by stepping down an external power supply voltage formed on a semiconductor wafer; The switch array constituting the switched-capacitor buck circuit is divided into a plurality of spaced-apart arrays, and each switch array is individually connected with an inherent switch capacitor, and the smoothing capacitors are connected in common. η. The semiconductor circuit device described in item 10 of the scope of patent application, wherein the aforementioned switching capacitor and smoothing capacitor are externally mounted on a semiconductor chip. 12. The semiconductor circuit device as described in item 10 of the scope of patent application, wherein the aforementioned switched capacitor and smoothing capacitor are mounted on a semiconductor chip. 1 3 · The semiconductor circuit device described in item No. 丨 0 of the scope of patent application, which has a step-down control circuit that controls the timing of switching between the smoothing capacitor and the switching capacitor connection of the switching matrix during the charge and discharge cycle, -40- 200524255 (3) The aforementioned step-down control circuit is controlled for staggering the switching timing of the plurality of switch arrays. 14. The semiconductor circuit device described in item 13 of the scope of patent application, wherein the step-down control circuit generates a clock signal with a phase shift for each switch array, and makes the aforementioned clock signals based on the generated clock signals. Connection switching timing is randomized at each switch array. 15. The semiconductor circuit device described in item 14 of the scope of the patent application, wherein the step-down control circuit has a random number generating circuit that randomizes the switching timing, and uses the generated random number to select the connection. Switch timing. [16] The semiconductor circuit device according to item 10 of the scope of patent application, wherein the switch array is disposed near an external connection electrode forming region of the semiconductor wafer. 17. The semiconductor circuit device described in item 6 of the scope of the patent application, wherein the step-down control circuit that controls the switching operations of the plurality of switch arrays is common to the plurality of switch arrays, and Isolated configuration. 1 8 · The semiconductor circuit device described in item 13 of the scope of patent application, wherein the step-down control circuit includes a series-regulated step-down circuit, the aforementioned switched capacitor-type step-down circuit and a series-regulated step-down circuit. The step-down voltage output terminals of the circuit are connected in common. 19. The semiconductor circuit device described in item 18 of the scope of patent application, wherein when an external power supply voltage is applied, the step-down operation of the aforementioned series regulator step-down circuit is started first, and then the switched capacitor type step-down is started- 41-200524255 (4) Start control circuit for step-down operation of the circuit. 2 0. A data processing system, characterized in that: it is equipped with the semiconductor circuit device described in item 1 of the scope of patent application, and is driven by a battery. -42 --42-
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US20050088158A1 (en) 2005-04-28
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US7876589B2 (en) 2011-01-25
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US20080290737A1 (en) 2008-11-27
US8085566B2 (en) 2011-12-27

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