TW200421955A - Structure design and manufacturing method of embedded polymer capacitor and metal film capacitor - Google Patents

Abstract

The present invention provides a singulated structure to replace the current planar structure of common capacitor. In the design of general device module, the distribution of capacitance value usually exceeds several orders of magnitude. Since the planar capacitor has a single capacitor layer only, if the capacitance is adjusted by the area of the electrode at the upper/lower end, usually the electrode areas of the large and small capacitors differ too much, which increases the difficulty and variation in the process. Therefore, the present invention associates the inorganic thin film capacitor with high capacitance and polymer thick film capacitor with lower capacitance, so as to form a distributed coplanar structure of embedded capacitor, the said problem can thereby be solved by using a general printed circuit board process.

Description

200421955 五、發明說明 【發明所 本發明係 造方法， 料（如高 電容結構 【先前技 由於電子 ’利用植 面積以及 目前常用 層介電薄 中之植入 上下層之 端電極1 1 稱之為平 上述之電 介電常數 此層高介 時間延遲 (1) 屬之技術領域】 有關一種半導體印刷電路板之結構設計與製 尤指一種在印刷電路板植入不同介電常數材 分子厚膜單片電容與無機薄膜平面電容）之 設計與製造方法。 術】 產品輕薄短小之趨勢，加上功能之不斷增多 入式（embedded)被動元件，以節省基板表面 提高電氣特性成為目前元件購裝技術的主流。 之植入式電容結構設計，乃是在基板丨〇以一 層（Sheet)13’上下各壓合鋼箔以形成如圖一 式電容結構。此種電容結構一般在連結電容 金屬層上’分別精由顯影、餘刻，形成電容 ’ 12，由於共用一層完整片狀電容層13，故 面式（Planar)電容結構。 容結構’由於所有植入式電容皆共用一層高 之電谷層’在電谷附近之傳輪線1 4會常經過 電常數之電谷層’此傳輸線1 4由於電阻—電容 (RC Time Delay)效應，無法滿足高頻高速之200421955 V. Description of the invention [The invention of the invention is a manufacturing method, materials (such as high-capacitance structures [prior art due to the use of electrons' planting area and the current commonly used layer dielectric thin film of the upper and lower end electrodes 1 1 are called The above-mentioned dielectric constant of this layer has a high dielectric time delay. (1) The technical field is related to the structural design and manufacturing of a semiconductor printed circuit board, especially a kind of thick-film molecular implanted with different dielectric constant materials on the printed circuit board. Chip capacitors and inorganic thin film planar capacitors) design and manufacturing methods. [Technology] The trend of thin, thin and short products, combined with the increasing number of embedded passive components to save substrate surface and improve electrical characteristics has become the mainstream of current component purchase technology. The implanted capacitor structure is designed by laminating steel foils on the substrate with a layer of 13 'to form a capacitor structure as shown in Figure 1. Such a capacitor structure is generally formed on the connection capacitor metal layer ′ by developing and engraving to form a capacitor ′ 12. Since a complete chip capacitor layer 13 is shared, a planar capacitor structure is used. Capacitive structure 'Because all implanted capacitors share a high electric valley layer' The transmission line near the electric valley 1 4 will often pass through the electric valley layer of constant electric constant 'This transmission line 1 4 is due to the resistance-capacitance (RC Time Delay ) Effect, can not meet the high frequency and high speed

200421955 五、發明說明（2) 需求。尤有甚者，因其在非電容處未有接地戒遮蔽層 ，使得該結構之電磁場非常複雜，容易造成嚴重之電 磁干擾（Electromagnetic Interference)。 而在一般元件模組設計中，電容值分布情形往往超過 數個數量級。如果以平面式電容僅具有之單一電容層 ，利用上下端電極之面積大小調整電容值，往往會造 成大小電容端電極面積尺寸相差過大，增加製程困難 與變異。 再者，由於平面結構需將整板（Ful 1 Panel)塗佈電容 膠，亦造成昂貴之電容膠塗佈於不需要之處，既浪費 ，又造成嚴重之電性不完整問題。 【發明内容】 基於上述習知技術之缺失，本發明提供一種單片式 (Si ngul ated)結構來代替現有共用電容之平面結構， 將可大幅解決上述之問題。如前所述，在一般元件模 组設計中，電容值分布情形往往超過數個數量級。如 果以平面式電容僅具有之單一電容層，利用上下端電 極之面積大小調整電容值，往往會造成大小電容端電 極面積尺寸相差過大，增加製程困難與變異。故本發 明結合具有高電容值之無機薄膜電容與較低電容值之200421955 V. Description of Invention (2) Demand. In particular, because there is no ground or shielding layer at the non-capacitance, the electromagnetic field of the structure is very complicated, and it is easy to cause serious electromagnetic interference (Electromagnetic Interference). In general component module designs, the distribution of capacitance values often exceeds orders of magnitude. If a flat capacitor has only a single capacitor layer, adjusting the capacitor value by using the area of the upper and lower electrodes often results in a large difference in the size of the electrode areas of the large and small capacitors, which increases process difficulty and variation. In addition, because the planar structure needs to coat the entire panel (Ful 1 Panel) with capacitor adhesive, it also causes expensive capacitor adhesive to be applied where it is not needed, which is wasteful and causes serious electrical incompleteness. [Summary of the Invention] Based on the lack of the conventional technology, the present invention provides a monolithic structure instead of the planar structure of the existing common capacitor, which can greatly solve the above problems. As mentioned earlier, in general component module designs, the distribution of capacitance values often exceeds orders of magnitude. If a planar capacitor has only a single capacitor layer, adjusting the capacitor value by using the area of the upper and lower electrodes often results in a large difference in the size of the electrode areas of the small and large capacitors, increasing process difficulty and variation. Therefore, the present invention combines an inorganic thin film capacitor with a high capacitance value with a low capacitance value.

200421955 五、發明說明（3) 高分子厚膜電容，以形成分散式共平面（Cop lanar)植 入電容結構，即可以應用一般印刷電路板製程技術來 解決上述問題。 然而’欲形成早片式植入電容結構’必須具有可分散 塗佈之電容膠或是可減除（Subtracted)的薄膜平面電 容層，以及直接相對應的上層導電性端電極（Upper Conductive Terminal)。傳統壓合銅箔或是事先置備 樹脂塗佈銅H (Resin Coated Copper)皆不易形成上 述結構。200421955 V. Description of the invention (3) Polymer thick film capacitors to form a distributed coplanar (Coplanar) implanted capacitor structure, that is, general printed circuit board process technology can be applied to solve the above problems. However, 'to form an early chip implanted capacitor structure' must have a dispersible coating of capacitive glue or a subtractable thin film planar capacitor layer, and a directly corresponding upper conductive terminal electrode (Upper Conductive Terminal) . The conventional laminated copper foil or resin-coated copper H (Resin Coated Copper) prepared in advance is not easy to form the above structure.

因此本發明可利用傳統雷射切割、網版印刷塗佈方式 ，結合各種直接金屬化的製成，即可完成具有單片式 之混成電容結構。 種在印刷電路板植人高分子厚膜電容 4 π ί ΐ 容（MFC)之結構設計與製造方法 可達成以下之目的： 1 ·改善現有平面電容結構之 提高高頻與高速電路系統之 Integrity)。 佈線與設計彈性，同使可 訊號完整性（SignalTherefore, the present invention can use traditional laser cutting and screen printing coating methods, combined with a variety of direct metallization, to complete a monolithic hybrid capacitor structure. The structure design and manufacturing method of polymer thick film capacitors (4 π ί) embedded in printed circuit boards can achieve the following purposes: 1 · Improve the existing planar capacitor structure and improve the integration of high frequency and high speed circuit systems) . Wiring and design flexibility, as well as signal integrity

2·由於多數之植入式電容層 柯料内並未有如玻璃纖維2 · Because most of the implanted capacitor layers are not like glass fiber

200421955 五、發明說明（4) 等之補強材料，故製作RCC型態之薄膜 戊人％八雷 層厚度之變異往往過大，本發明 田守[a後7丨電 製程公差。 +知月不使用壓合製程以減低 3·利用不同介電常數之材料， 高…值之設計，降低基板以 及提高製程良率。 以降低製作成本以 為其能對本於日月夕a ^ , ιινΛΛν . 錄羋了貫轭例併配合圖示說明如後· 實施方式] 圖-一為本發明之_ 與金屬薄膜電容：刷電路板植入高分子厚膜電容 板20上塗佈有—:Ϊ S又計之剖面圖。如圖二所示，在基 機薄膜平面電六二"、、機薄膜平面電容層21。由於該層無 、雷射切割、=9 2 1非常薄，因此可以輕易以濕式蝕刻 以網版印刷方^電漿蝕刻等方式形成所設計之圖案。再 膜平面電容層f ’將高分子厚膜電容膠22塗佈於無機薄 值之共平面^構所切割出之空位上，即可形成高低電容 在完成圖案製作 以形成雷交 之作為電容用之介電層上’有上電極23 °此有上電極23之形成包括二步驟：介電層200421955 V. Description of the invention (4) and other reinforcing materials, so the RCC type film is made. The variation of the thickness of the layer is often too large. The present invention Tian Shou [a 后 7 丨 Electrical process tolerance. + Zhiyue does not use a lamination process to reduce 3 · Using materials with different dielectric constants, high-value design, lowering the substrate and improving the process yield. In order to reduce the production cost, it can be used on the sun and the moon a ^, ιινΛΛν. The example of the yoke is recorded and illustrated with the illustration as follows. Implementation] Figure-One of the present invention _ and metal film capacitors: brush circuit boards The implanted polymer thick film capacitor plate 20 is coated with a cross-sectional view of ΪS. As shown in FIG. 2, the base film plane capacitor layer 21 is formed on the base film plane. Since this layer is very thin, laser-cut, and = 9 2 1, the designed pattern can be easily formed by wet etching, screen printing, plasma etching, etc. Then, the planar capacitor layer f 'is coated with the polymer thick film capacitor glue 22 on the vacancies cut by the inorganic thin coplanar structure, and the high and low capacitance can be formed. The pattern is completed to form a lightning cross as a capacitor. There is an upper electrode 23 on the dielectric layer. The formation of the upper electrode 23 includes two steps: the dielectric layer.

第8頁 200421955 五、發明說明（5) 之表面粗化前處理，係將該介電層之表面 ，以及金屬化程序，係將該粗化後之介電屑仃粗化處理 化，以形成導電性之上電極2 3。 q之表面金屬 植入電容層完成後，即可接續進行後續之姆 完成其他層次之線路。 日㈢製程，以 各與 本發明更提供一種在印刷電路板植入高分 金屬薄膜電容之製造方法，包含： 予膜電 (a) ·提供一基板， (b) ·形成一薄膜平面電容層，於該基板上方 · (c) ·形成第一種電容值圖案，於該薄膜平面雷〜 成一圖案，其中該薄膜層之圖案可由蝕刻、谷層上形 電漿鍅除等技術，製作而成之高電容值圖案射修勿、 (d) ·沈積一不同介電常數之材料於該薄膜& 案之切空處，其中該不同介電常數之材料可 ，^層圖 厚膜電容材料，例如高分子電容膠，以網版印:高，子 沈積等技術沈積而成，沈積材料與該無機薄膜 ^， 層形成共平面結構， 、曲電容 (e )·形成一上層導體端電極，係將該電容層表面金屬 松 化而成，其中該電容層表面金屬化程序更包含： (1 )介電層表面粗化前處理程序，可為傳統去膠渣之高錳 酸鉀溶液或置於真空電漿環境將表面粗化，以及Page 8 200421955 V. Description of the invention (5) The surface pre-roughing treatment refers to the surface of the dielectric layer and the metallization process. The roughened dielectric chip is roughened to form Conductive upper electrode 2 3. After the surface metal of the Q is implanted into the capacitor layer, it can be followed up to complete other layers of circuits. In the sundial manufacturing process, the present invention further provides a manufacturing method for implanting a high-scoring metal thin film capacitor in a printed circuit board, including: pre-filming electricity (a) · providing a substrate, (b) · forming a thin film planar capacitor layer On the substrate, (c) The first capacitance value pattern is formed, and a pattern is formed on the plane of the thin film. The pattern of the thin film layer can be made by etching, plasma plasma erasing, and other techniques. (D) · deposit a material with a different dielectric constant in the cutout of the thin film & case, where the material with a different dielectric constant can be a thick film capacitor material, For example, polymer capacitor adhesive is deposited by screen printing: high, sub-deposition and other techniques. The deposited material and the inorganic thin film are formed into a coplanar structure, and the curved capacitor (e) forms an upper-layer conductor terminal electrode. The capacitor metal surface is loosened, and the capacitor layer surface metallization procedure further includes: (1) the dielectric layer surface roughening pre-treatment procedure, which can be a conventional potassium permanganate solution for removing glue residue or put Vacuum plasma environment roughens the surface ,as well as

第9頁 200421955 五、發明說明（6) (i i )金屬化程序，可為以化學銅、直接鍍銅或是真空濺 鍍方法形成所需之上層導體端電極。 與本發明類似之現有技術之缺點： 1. 由於電阻-電容時間延遲（RC Time Del ay)效應，無法 滿足南頻南速電路之傳輸需求。 2. 在非電容處未置有接地或遮蔽層，容易造成嚴重之電 磁干擾。 3. 僅具有單一電容層，利用上下端電極之面積大小調整 電容值，往往會造成大小電容端電極面積尺寸相差過大 ，增加製程困難與變異。 4. 昂貴之電容膠塗佈於非電容處，造成浪費材料，導致 生產成本提高。 5. 壓合銅箔形成之金屬導體層，會導致介電層厚度之變 異過大。 經由以上本發明之一實施例與現有之習知技術 比較，本發明有以下之優點： 1. 單片式之植入電容設計可大幅提高電路設計之彈性， 此結構更可經由事先設計（D e s i g η - i η )的線路佈局，大幅 提高電氣訊號之完整性。 2. 在同一層次内即可設計出電容值大小差異數個數量級 之電容，而不需增加額外之電容層，如此可節省製程成 本，並提高製程良率。Page 9 200421955 V. Description of the invention (6) (i i) The metallization process can be to form the required upper conductor terminal electrode by chemical copper, direct copper plating or vacuum sputtering. Disadvantages of the prior art similar to the present invention: 1. Due to the resistance-capacitance time delay (RC Time Del ay) effect, it cannot meet the transmission requirements of the South-Frequency South-Speed circuit. 2. There is no grounding or shielding layer at the non-capacitance place, which may cause serious electromagnetic interference. 3. There is only a single capacitor layer, and the capacitance value is adjusted by the area of the upper and lower electrodes, which often results in a large difference in the size of the electrode areas of the small and large capacitors, which increases the difficulty and variation of the process. 4. Expensive capacitor glue is applied to non-capacitors, causing waste of materials and increasing production costs. 5. The metal conductor layer formed by laminating copper foil will cause the thickness of the dielectric layer to vary too much. By comparing one embodiment of the present invention with the prior art, the present invention has the following advantages: 1. The monolithic implanted capacitor design can greatly improve the flexibility of circuit design, and this structure can be designed in advance (D esig η-i η), greatly improving the integrity of electrical signals. 2. Capacitors with several orders of magnitude difference in capacitance value can be designed at the same level, without the need to add additional capacitor layers. This can save process costs and improve process yield.

第10頁 200421955Page 10 200421955

五、發明說明（7) 3·在單片式電容層上製作金屬導體方式中，由下而上 (Bottom-Up)之直接金屬化程序相較整面屋合銅箔經由钱 刻製作線路之減除法具有更高之製程準確度與選擇性。 因此，本發明之一 金屬薄膜電容之結 藝，達到所預期之 進步性與產業利用 種在印刷電路板植入 構設計與製造方法， 目的與功欢，符合發 性之要件。 高分子厚膜電容與 確能藉所揭露之技 明專利之新穎性， 僅為本發明之較佳實施例 苑:大凡熟悉該項技藝之 之變化或修飾，皆應涵蓋V. Description of the invention (7) 3. In the method of making a metal conductor on a monolithic capacitor layer, the direct metallization process from bottom to top (Bottom-Up) is compared to the process of making a line through the entire surface of the copper foil through the inscription Subtraction has higher process accuracy and selectivity. Therefore, the metal thin film capacitor technology of the present invention achieves the expected progress and industrial utilization. The method of designing and manufacturing implanted structures in printed circuit boards meets the requirements of development. Polymer thick film capacitors and the novelty of the technology patents that can indeed be disclosed are only preferred embodiments of the present invention. Yuan: Anyone familiar with changes or modifications to this technology should cover

惟’以上所揭露之圖示及說明， 而已’非為用以限定本發明之實 人士其所依本發明之精神，所作 在以下本案之申請專利範圍内。However, the above-mentioned illustrations and descriptions are not intended to limit the persons of the present invention to the spirit of the present invention, and are within the scope of the following patent applications.

200421955 圖式簡單說明 圖一為習知之平面式植入電容結構設計之剖面圖。 圖二為本發明之單片式植入電容結構設計之剖面圖。 【元件符號簡單說明】 基板1 0 上金屬層11 介電層1 2 下金屬層1 3 傳輸線1 4 基板20 薄膜平面電容層21 高分子厚膜電容膠22 上層導體端電極23200421955 Brief description of the diagram Figure 1 is a cross-sectional view of the conventional planar implanted capacitor structure design. FIG. 2 is a sectional view of a monolithic implanted capacitor structure design of the present invention. [Simple description of element symbols] Substrate 1 0 Upper metal layer 11 Dielectric layer 1 2 Lower metal layer 1 3 Transmission line 1 4 Substrate 20 Thin film plane capacitor layer 21 Polymer thick film capacitor glue 22 Upper conductor terminal electrode 23

第12頁Page 12

Claims (1)

200421955 六、申請專利範圍 1.一種植入高分子厚膜電容與金屬薄膜電容之結構，包 括： 一基板； 一薄膜平面電容層，位於該基板上方，並於其表面形成 一圖案，在於該圖案之所切割出之空位上，沈積有不同 介電常數之材料，並與該薄膜平面電容層形成共平面結 構；以及 一上電極，位於該電容層上方，係由該電容層表面經金 屬化程序而成。 2 .如申請專利範圍第1項所述之結構，其中該無機薄膜平 面電容層之圖案係由蝕刻、雷射修剪、電漿蝕除等技術 ，製作而成之高電容值圖案。 3 .如申請專利範圍第1項所述之結構，其中該薄膜平面電 容層係為無機或有機南分子材料，如南分子厚膜材料、 金屬氧化物或陶瓷電容材料。 4.如申請專利範圍第1項所述之結構，其中該薄膜平面電 容層之圖案的形成，係以網版印刷、薄膜沈積等直接加 成法或預先形成全平面介電層再以#刻、雷射修剪、電 漿蝕除等減除法完成之。200421955 VI. Scope of patent application 1. A structure for implanting polymer thick film capacitors and metal thin film capacitors, including: a substrate; a thin film planar capacitor layer located above the substrate, and forming a pattern on the surface of the pattern; On the cut-out space, materials with different dielectric constants are deposited and form a coplanar structure with the thin film planar capacitor layer; and an upper electrode is located above the capacitor layer, and the surface of the capacitor layer undergoes a metallization process. Made. 2. The structure described in item 1 of the scope of the patent application, wherein the pattern of the flat capacitor layer of the inorganic thin film is a high-capacitance pattern made by techniques such as etching, laser trimming, and plasma etching. 3. The structure described in item 1 of the scope of the patent application, wherein the thin film planar capacitor layer is an inorganic or organic south molecular material, such as a south molecular thick film material, a metal oxide, or a ceramic capacitor material. 4. The structure described in item 1 of the scope of the patent application, wherein the pattern of the thin film planar capacitor layer is formed by a direct addition method such as screen printing, thin film deposition, or a full-plane dielectric layer is formed in advance and then engraved with , Laser trimming, plasma erosion and other subtraction methods are completed. 第13頁 200421955 六、申請專利範圍 5 .如申請專利範圍第1項所述之結構，其中該不同介電常 數之材料係為一高分子厚膜電容材料，例如高分子電容 膠。 6 .如申請專利範圍第1項所述之結構，其中該不同介電常 數之材料之沈積係以網版印刷、薄膜沈積等技術沈積而 成，沈積材料與該薄膜平面電容層形成共平面結構。 7 製之 之料 構材 結數 之常 容電 膜同 薄不 屬入 金植 與板 容路 ^¾ 膜刷 厚印 子在 分： 高含構 入包結 植，之 種法層 一方容 ，造電 a b Γν /ι\ 板 基 - 供 提 板 基 該 於 層 容 電 面 平 膜 薄 之 數 常 介 種 一 第 成 方 上 案 圖 之 層 容 rpBr 面 平 膜 薄 該 成 形·，形 之容 層電 容面 ^¾ >1 面膜 平薄 膜該 薄與 該料 於材 料積 材沈 之， 數上 常位 電空 介之 同出 不割 一切 積所 沈中 ).案 d Γν 圖 及 以 構 結 面 平 共 成 形 層 極 端 體 導 層 上 1 成 形 端 上 層 容 電 於 8 .如申請專利範圍第7項所述之製造方法，其中該薄膜平 面電容層之圖案係由蝕刻、雷射修剪、電漿蝕除等技術， 製作而成之第一種介電常數之薄膜平面電容層圖案。Page 13 200421955 6. Scope of patent application 5. The structure described in item 1 of the scope of patent application, wherein the material with different dielectric constant is a polymer thick film capacitor material, such as a polymer capacitor glue. 6. The structure according to item 1 of the scope of patent application, wherein the deposition of the materials with different dielectric constants is performed by screen printing, thin film deposition and other techniques, and the deposited material forms a coplanar structure with the thin film planar capacitor layer. . The 7-capacity constant-capacity film with the same structure and material is not included in the gold plant and the board capacity. ^ ¾ The thickness of the film brush is divided into the following points: The high-content structure is incorporated into the package, and the method is one-sided to create electricity. ab Γν / ι \ Board base-The number of flat base films on the surface of the capacitor layer for thin layer capacitors is often described in the first figure. Face ^ ¾ > 1 The thin film of the mask is the same as the material in the material, Shen Zhi, and the number of constant electrical air dielectrics is the same as the one that does not cut everything (Shen Zhong). Case d Γν Figure and the structure plane flat The co-formed layer is on the extreme body conductive layer. The upper end of the formed end is charged at 8. The manufacturing method as described in item 7 of the scope of patent application, wherein the pattern of the thin film planar capacitor layer is etched, laser trimmed, and plasma-etched And other technologies, the first dielectric constant thin film planar capacitor layer pattern is fabricated. 第14頁 200421955 六、申請專利範圍 9 .如申請專利範圍第7項所述之製造方法，其中該不同介 電常數之材料係為一高分子厚膜電容材料，例如高分子電 容膠。 1 0 .如申請專利範圍第7項所述之製造方法，其中該不同介 電常數之材料之沈積係以網版印刷、薄膜沈積等技術沈積 而成，沈積材料與該薄膜平面電容層形成共平面結構。 1 1.如申請專利範圍第7項所述之製造方法，其中該形成 一上層導體端電極步驟係將該電容層表面金屬化而成。 1 2 .如申請專利範圍第1 1項所述之製造方法，其中該電容 層表面金屬化程序更包含： (i )介電層表面粗化前處理程序；以及 (i i )金屬化程序。 1 3.如申請專利範圍第1 2項所述之製造方法，其中該介電 層表面粗化前處理程序係為傳統去膠渣之高錳酸鉀溶液 或置於真空電漿環境將表面粗化。 1 4.如申請專利範圍第1 2項所述之製造方法，其中該金屬 化程序係為以化學銅、直接鍍銅或是真空濺鍍方法形成 所需之上層導體端電極。Page 14 200421955 6. Scope of patent application 9. The manufacturing method described in item 7 of the scope of patent application, wherein the material with different dielectric constant is a polymer thick film capacitor material, such as a polymer capacitor. 10. The manufacturing method as described in item 7 of the scope of the patent application, wherein the deposition of the materials with different dielectric constants is performed by screen printing, thin film deposition and other techniques, and the deposited material forms a common with the thin film planar capacitor layer. Flat structure. 1 1. The manufacturing method as described in item 7 of the scope of patent application, wherein the step of forming an upper conductor terminal electrode is made by metalizing the surface of the capacitor layer. 12. The manufacturing method as described in item 11 of the scope of patent application, wherein the surface metallization process of the capacitor layer further comprises: (i) a pre-treatment process for roughening the surface of the dielectric layer; and (i i) a metallization process. 1 3. The manufacturing method as described in item 12 of the scope of patent application, wherein the surface roughening process of the dielectric layer is a conventional potassium permanganate solution for removing glue residue or placing the surface in a vacuum plasma environment to roughen the surface. Into. 1 4. The manufacturing method as described in item 12 of the scope of the patent application, wherein the metallization process is to form the required upper conductor terminal electrode by chemical copper, direct copper plating or vacuum sputtering. 第15頁Page 15