200301009 玖、發明議麗 本發明在民國90年11月27日提出申請臨時 申請案第 6 0 / 3 3 3，6 8 6號的優先權，標題爲提供 靜電排放用的聚合物薄膜***模塑，其係在此 以引用的方式倂入本文。 發明領域= 本發明一般係關於薄膜***模塑，而且更特 別地關於在半導體元件處理器或載體期間內， 將一薄傳導性聚合物薄膜***模塑，以提供靜 電排放，離開該半導體元件。 發明背景= 習知的薄膜***模塑技術一般係使用於製造 製程，以增加各種消費產品中的美學吸引力。 亦β卩，裝飾性花樣、指令、商標、以及其它視 覺上的圖案係印在薄透明聚合物薄膜的一表面 上，以使用於***模塑製程。稍後的發展則擴 充薄膜之使用，以將譬如條碼的功能性特徵永 久地固定到該產品。在兩種情形之中，在注入 可塑性材料之前，可將該薄膜放置於模子的一 部份內。這種情形會產生薄膜與接合部份之間 的接合，以致使可將價錢低廉的裝飾或指標選 擇性地放置於該部份上，而卻同時在複雜輪廓 的四週以及困難達到的位置上將指標之使用簡 化。相同地，藉由消除令該指標受到蝕刻或成 形爲模子本身之實際表面的需求，此薄膜*** 200301009 模塑或裝飾性的模塑會簡化該製造過程。這種 情形增加了設計與製造彈性，以及可包括在最 後產品中的細節程度。 半導體工業將獨特且非常規的純淨與抗髒的 需求條件引入於產品設計與製造方法的發展與 實施內。最重要地，在元件與組件的製造、儲 存、與運輸中，材料的挑選是必要的。例如， 種種聚合物材料，譬如聚醚醯亞胺（P E )、聚碳 酸酯 （PC)、聚四氟乙烯樹脂 （PFA)、聚芳醚 酮（PEEK)與類似物，其係一般使用於包含在 架構晶圓載體與晶片盤之元件與結構的製造 中 〇 晶圓載體= 將晶圓圓盤加工處理成積體電路晶片之製程 通常包含許多步驟，在此，圓盤係重複地予以 加工、儲存與運輸。由於圓盤的易碎特性以及 它們的極値，適當地在此整個過程將它們保護 係爲必要的。晶圓載體的一目的乃在提供此種 保護。此外，因爲晶圓圓盤的加工處理一般爲 自動化，所以就有必要將圓盤相關於自動移除 與***晶圓用之處理裝置地精確地放置。晶圓 載體的第二目的乃在於運輸期間內牢固地固持 住晶圓圓盤。 載體一般被架構來將晶圓或圓盤軸向地排列 在架或槽中，並且藉由或靠近周圍邊緣而支撐 7 200301009 該晶圓或圓盤。習知地，在徑方向上，可向上 或水平地將晶圓或圓盤從載體移除。載體可具 有額外的頂部遮蓋物、底部遮蓋物、或將晶圓 或圓盤密封的外殼。有許多的材料特徵，其係 對晶圓載體有用以及有利，其係取決於載體的 型態以及載體的特別部份。 由於半導體晶圓或磁圓盤的加工處理，微粒 物質之存在與產生呈現出非常明顯的污染問 題。污染係被認爲是在半導體工業中產量耗損 的單獨最大原因。因爲已經連續地將積體電路 的尺寸縮小，所以可污染積體電路的顆粒尺寸 則同樣變得更小，其係使得污染物的縮小化更 爲重要。成顆粒型式的污染物，其係可由磨損 所產生，譬如載體與晶圓或圓盤、與載體蓋子 或外殼、與儲存網架、與其它載體、或與其它 製程裝置的磨擦或切削。載體最令人希望的特 徵因此則是在塑膠成形材料之磨損、磨擦、或 切削上具有對抗顆粒的產生的效果。美國專利 第 5，7 8 0，1 2 7號揭露出有關此種用於晶圓載體 之材料之適宜性的種種塑膠特性，其係在此以 引用的方式倂入本文。 載體材料應該同樣具有揮發性元件的最小漏 氣，.當它們可能離開薄膜時，其係同樣地構成 可傷害晶圓與圓盤的污染。當負載載體時，該 載體材料必須具有足夠的尺寸穩定度，亦即是 200301009 剛度。就預防對晶圓或圓盤之損壞以及將晶圓 或圓盤在載體內之移動最小化來說，尺寸的穩 定度是必要的。固持晶圓與圓盤之槽的容差基 本上非常地小，而且載體的任何變形可直接地 傷害高度易碎的晶圓或增加磨損，以及在將晶 圓或圓盤移入時，將產生來自載體或其內的顆 粒。當在某方向上負載載體時，例如當將載體 於裝載期間堆疊時，或當載體與處理裝置結合 時，尺寸的穩定度則同樣極其重要。在儲存或 淸潔期間內可遇到的高溫之下，載體材料應該 亦可維持其尺寸穩定度。 使用於半導體工業中的習知載體可發展並保 留靜電充電。當將一充電塑膠部份接觸一電子 裝置或製程裝置時，它則可以被認爲是靜電排 放 （E S D )的傷害現象來排放。此外，靜電充 電的載體可吸引並保留住顆粒，特別是在空中 傳播的顆粒。同樣地，載體上的靜電建立可導 致半導體製程裝置自動地關閉。結果，最令人 希望的則是擁有具有靜電排放特性的載體，以 排放 E S D並且避免吸引粒子。 密封容器內的晶圓可見度乃高度地令人希望 並且爲終端使用者所需要。適合此容器的透明 塑膠，譬如聚碳酸酯，其係在此塑膠成本很低 但此塑膠不具有天生的靜電排放特徵與希望抗 磨性之情形中令人希望。 200301009 其它重要的考量包括載體材料之成本與將該 材料成形之容易度。載體典型地由注入成形塑 料所形成，譬如 p c (聚碳酸酯）、A B S (丙烯腈 -丁二烯-苯乙烯共聚物）、PP(聚丙烯）、PE (聚 醚醯亞胺）、PFA (聚四氟乙烯樹脂）、PEEK (聚 芳醚酮）以及類似材料。 特定專門聚合物，譬如 PEEK，的一主要好處 是它們的抗磨特性。典型價錢低廉的習知塑膠 在磨損或甚至在對著其它材料或物體摩擦時， 會將微小的顆粒釋入到空氣中。雖然這些顆粒 對肉眼來說基本上是不可見的，但是他們卻導 致可附著到予以加工之半導體元件的潛在傷害 性污染的引入，並且引入到必須加以控制的環 境內。不過，特定的熱塑性聚合物比習知聚合 物還更顯著地昂貴。事實上，各種的特定熱塑 性聚合物本身有巨幅地差異，亦即，P E E K (聚 芳醚酮）比 PC (聚碳酸酯）還更貴。 除了它們的抗磨特性之外，熱塑性聚合物可 具有添加物，譬如添加以產生傳導特性的碳纖 維或粉末塡充物。已經添加到注入成形塑膠， 以用於靜電排放的塡充物，包括碳粉或碳纖 維、金屬纖維、鍍上金屬的石墨、以及有機（以 胺爲基底）添加物。因此，具有此添加物的熱 塑膠可使用於半導體元件處理器的材料架構 中，以促進 E S D。 10 200301009 習知的實施中包括利用一種材料，譬如 PEEK 或其它相容材料來構成一整體的晶圓載體/處 理器元件，以促進 E S D。不過，如所述，特別 材料之製造與使用則明顯地更昂貴，而且將該 材料使用於大型處理器元件的架構中則經常不 是所希望的，甚至不可實施。此外，以製造此 半導體處理器所需要的方式來操作與將譬如 PEEK(聚芳醚酮）之材料模塑是困難的。現在， 晶圓載體的製造商被迫在傳導熱塑性塑膠之 E S D特性的好處以及製造該材料的所有或實質 一部份產物的成本之間做一決定。雖然促進 E S D之材料僅可於載體之那些接觸表面的特別 應用上令人需要，該載體係碰觸到易碎的半導 體元件或處理裝置，但是全部或部份的處理器 則典型地由促進 ESD的聚合物所構成，以避免 靜電對元件造成的傷害。例如，日本專利申請 案 JP62205616、 JP8293536、 JP3012949、 JP9036216以及 JP9162273揭露將出自具有傳 導特性之熱塑性塑膠之晶圓載體之所有元件成 形的各種方法，其中該傳導性特徵係經由譬如 碳塡充物、樹脂、以及類似物的傳導性添加物 而獲得。再者，日本專利申請案 JP1013717與 J P 6 2 2 8 7 6 3 8揭露出晶圓載體本體，其係具有沿 著晶圓載體之表面而蔓延的傳導棒或佈線，以 提供接地路徑。這些在 E S D上的各習知試驗先 11 200301009 天上就因爲製造的無效率與成本而有問題。此 外，在晶圓載體之架構中傳導金屬物的採用可 引來污染並導致令人無法接受的元件磨耗。 結果，在半導體工業中，就對實質減少不必 要的製造過程並允許傳導性材料之目標與局部 化實施的製造技術來說，提供靜電排放則是需 要的。此一創新將藉由容許希望但卻經常昂貴 之熱塑性聚合物的選擇性使用，而來大幅度地 降低製造與設計成本。 發明槪述= 本發明一般係關於在半導體製程工業中所利 用之處理器、運輸器、載具、盤與類似裝置之 模塑製程中，包含一薄且可導電的聚合物薄 膜，譬如充塡碳聚合物用的系統與方法。將預 定尺寸與形狀的傳導薄膜沿著模穴中的成形表 面而選擇性地放置，以用來對齊可塑性材料的 希望目標表面。該成形製程導致該薄膜的表面 接合到可塑性材料的接觸表面，以便將該薄膜 永久地黏附到可塑性材料。結果，相容性傳導 聚合物則可選擇性地僅接合到需要E S D的那些 目標表面'。例如，半導體晶圓載體支撐結構可 包括沿著至少一部份的此傳導性聚合物薄膜， 以提供一路徑來導引靜電遠離可接收可牢固的 晶圓。再者，E S D薄膜可包括額外的薄膜層， 以包含薄膜疊層，以接合到半導體元件處理裝 12 200301009 置，並且增力□具有其它功能特徵的聚合物層， 譬如抗磨性、耐熱性、阻礙吸收保護、抗化性 以及無數個其它功能性特徵。 本發明之特定具體實施例之目的與特徵乃在 於它能提供選擇性地利用希望聚合物以及聚合 物之對應功能性特徵的成本節約方法，其中比 需要者還利用更多的聚合物則並非必要。 本發明之特定具體實施例之另一目的與特徵 乃在於可將傳導性熱塑性薄膜接合到接觸敏感 部件、元件、或處理裝置的一部份晶圓載體、 晶片盤、或其它半導體組件處理器或輸送器， 以提供用於 E S D。此外，該排放會將吸引不希 望之污染顆粒的環境靜電電荷降到最小。 本發明之特定具體實施例的進一步目標與特 徵乃在於使用於半導體工業之部件上較佳抗磨 性聚合物薄膜的選擇性使用。就其本身而論， E S D與希望的抗磨性兩功能可在使用單一聚合 物薄膜或薄膜疊層的目標表面上有所進展。 本發明之特定具體實施例的仍另一目標與特 徵乃在形成具有透明或半透明之聚合物薄膜表 面區域的半導體組件處理裝置。此一處理裝置 乃藉由將一足夠薄的材料層形成於該裝置的被 選定目標結構上，以及在有或沒有中間層的情 形下，將該結構重疊注塑到譬如 P C(聚碳酸酯） 材料所構成之實質透明裝置的體部而來形成。 13 200301009 本發明特定具體實施例之仍另一目標與特徵 乃在於可將至少一傳導薄膜***模塑到該半導 體處理裝置的種種部件，以促進與相同裝置之 其它部件的不光澤對準，或者實質相等裝置的 可堆疊不光澤部件，以沿著一般接地路徑而來 提供傳導性互連。 較佳具體實施例之詳細說明： 參考圖1 - 9，本發明包括將一傳導性靜電排 放熱塑性薄膜1 〇***模塑到使用一模塑單元 20之半導體元件處理裝置 12的選出目標表面。 E S D薄膜 至少一傳導性或 E S D薄膜 1 0是具有傳導率 之可測量程度的熱塑性聚合物。該薄膜 1 〇至少 部份地由有限的厚度水平界定出。例如，厚度 等於或小於大約.〇 4 0英吋（千分之四十）的單 一薄膜層是令人展望的。較佳地，單一薄膜層 小於或等於大約.〇 3 0英吋（千分之三十）。當 然，多層堆疊之實施將改變關鍵性的較佳厚 度。應該注意的是，在此申請案中，傳導性用 語乃包括各種傳導率程度以及/或者 E S D。一般 而言，表面電阻率或歐姆每平方，界定出物質 的傳導率。爲了此申請案之目的，傳導率將包 括抗靜電、靜電排放、與傳導特性。本發明可 接受的電阻率範圍大約大於或小於 1 X 1 0 1 2歐 姆/每平方，或在 1χ10_5歐姆/每平方至 1χ101: 14 200301009 歐姆/每平方之間。此範圍是示範性的，並且提 供爲熟諳該技藝者所理解的可接受範圍。任何 相容的材料可使用於薄膜 1 〇，假定它具有有效 的傳導特性的話。例如，聚酯、聚亞烯胺 (Polyimide，PI)、聚醚醯亞胺（Polyether Iniide， PEI)、聚芳醚酮（Poly Ether Ether Ketone ， PEEK)、聚四氟乙烯樹脂（Perfluoroalkoxy Resin, PFA)、乙烯丙烯氟化物（Fluorinated Ethylene Propylene ，FEP)、聚氟化亞乙條 (Polyvinylidene Fluoride, PVDF)、聚甲基丙 烯酸甲酯（Polymethyl Methacrylate, PMMA)、 聚醚砸（Polyether Sulfone， PES)、聚苯乙烯 (Polystyrene ，PS)、聚伸苯基硫 (Polyphenylene Sulfide，PPS)、以及無數個其 它相容性聚合物是有用的。一具體實施例將包 括一熱塑性材料，其係具有添加以產生傳導特 性之譬如碳纖維或粉末塡充物的添力D物，以促 進 ESD。這些添加物包括碳粉末或纖維、金屬 纖維、鍍上金屬的石墨、有機（以胺爲基底） 添加物、以及類似物。提升熱塑性塑膠之傳導 特性的其它聚合物與添加物，其係可同樣地爲 那些熟諳該技藝者所熟知，並且可在不背離本 發明之精神與範圍的情形下使用。如在此所說 明者，薄膜 1 〇的 E S D功能可提供接地路徑， 並可從有關的半導體元件移除電荷，以降低顆 15 200301009 粒與其它污染物之吸引作用。由本申請人所擁 有而且標題爲”具有功能性薄膜的半導體元件 處理裝置”之審理中的美國申請案第_ 號，其係在此以引用的方式倂入本文。 爲了在半導體元件處理裝置12之製造中應 用該傳導薄膜1 〇，薄膜i 〇 —般依據接合應用 的特別需要而切割成預定的形狀與尺寸。在切 割之後，可隨後將薄膜 1 0加熱成形。薄膜1 0 一般很薄而且像薄片，以較佳地促進可塑性， 並且在該材料的透明或半透明特性上利用。 除了將單一傳導薄膜 1 0***模塑以外，可將 複數個薄膜 1 0疊層，以包含合成薄膜結構，可 塑性地接合到半導體元件處理裝置 1 2。例如， 種種薄膜層可包括不同的傳導強度。在一具體 實施例中，接合到處理器1 2表面的薄膜疊層可 具有比外層還高的傳導率，以增力卩傳導路徑的 有效程度，並將來自靜電的潛在傷害降到最 小。仍另一具體實施例可結合其它的薄膜層與 傳導薄膜 1 0，以增加抗磨、抗化、抗溫度、吸 收阻礙、漏氣阻礙以及類似特性到可模塑地接 收薄膜堆疊之處理裝置 1 2的部份或表面。將熟 諳該薄膜疊層技藝者所已知的種種薄膜疊層技 術想像成與本發明一起使用。例如，美國專利 案編號第 3, 660, 200、4, 605,591、5, 194, 327、 5，3 4 4，7 0 3、與 5 , 8 1 1，1 9 7號揭露出熱塑性疊層 16 200301009 技術而且在此以引用的方式倂入本文。 E S D薄膜***成形 主要地參考圖1 - 7，模塑單元 2 0 —般包括模 穴 2 2、遮蓋部份 2 4、以及至少一注入通道部份 2 8。該至少一注入通道 2 8可以流體而與模穴 22互通。模穴 22可包括在模塑製程期間內， 設計以將注入可塑性材料3 0與/或薄膜1 0模塑 的一成形表面 2 6或多個表面。遮蓋部份 2 4選 擇性地結合或遮罩住該模穴 22。模塑單元 20 的種種具體實施例可進一歩地包括與模穴 22 以及/或者成形表面 26互連的至少一真空通道 2 9，以在將譬如薄膜 1 0之物質固定到模穴 2 2 時引入真空吸力。可固定地使薄膜1 〇符合於穴 2 2內，並應用靜態固定與強迫性結合而將表面 2 6成形之其它已知技術亦同樣地令人想像成 與本發明一起使用。應該注意的是，好幾個圖 將薄膜 1 〇描繪成與相對應處理裝置相較之下 之不成比例的大，其係僅爲了說明之目的，而 卻不打算代表本發明用的真實比例。 在一具體實施例中，遮蓋部份 24可移動地固 定到模穴 2 2，以助於薄膜1 0之***以及完成 後之處理裝置部份或部件 32的移動。模塑部件 3 2 —般小於完成的處理裝置1 2。例如，將邊牆 ***物與晶圓載體架分開模塑並且常常以相較 於該載體本體的不同塑料來模塑則是常見的。 17 200301009 種種的注入與***成形技術對那些熟諳該技藝 者而言是已知的，而且其係可在不偏離本發明 之精神與範圍的情形下實施。 可塑性材料 3 0較佳地爲實質非傳導性的熱 塑性材料，其係一般使用於半導體製程工業中 所使用的模塑部件中。此外，材料 3 0可以是 PFA (聚四氟乙烯樹脂）、PE (聚醚醯亞胺）、 PC (聚碳酸酯）與類似物。更明確地，可塑性 材料 3 0可以是習知用來架構晶圓載體、晶片 盤、以及其元件與部件的材料。 當操作時，可將傳導薄膜1 〇切割成預定的形 狀，隨後並加熱成形成需要的形式。將受到加 熱成形的薄膜1 〇放置於模塑單元 2 0內，以致 使該薄膜 1 〇以表面與模穴 2 2之至少一成形表 面 2 6的至少一部份接觸。如在此所指出的，可 將譬如真空、靜態、與強迫性固定的各種技術 實施，以助於將薄膜 1 〇正確地放置於穴 2 2或 成形表面 2 6。隨後可將遮蓋部份 2 4密封，以 準備材料 3 0之注入。在此製程的階段中，可塑 性材料 3 0會經由至少一注入通道 2 8而以實質 熔化的狀態注入到穴內。在等待一不可或缺的 冷卻時期以後，模塑單元 2 0內的可塑性材料 3 0會冷卻，以形成實質凝固的模塑部件 3 2。與 冷卻製程合倂的熔化注入，其係在至少一薄膜 1 〇與模塑部件3 2之間形成永久的黏附接合。 18 200301009 在模塑製程完成之後，可將模塑部件 3 2從模 塑單元 3 2排出，而部件 3 2的傳導薄膜 1 0則永 久地接合到選出的目標表面。爲那些熟諳該技 藝者所已知的習知加工、技術、與實施，其係 可使用於材料 3 0之注入與部件 3 2之排出。 晶圓處理器/載體 各種習知的晶圓處理裝置 3 4以及裝置 3 4元 件或部件係顯示於圖 4 - 7中。可將傳導薄膜 1 0 或薄膜疊層以在此所說的薄膜***成形製程而 來接合到該晶圓處理裝置 3 4 (亦即，晶圓載體） 之挑選出的元件與/或部份。晶圓處理器 3 4 — 般係由至少兩不同的熔化可加工材料所形成。 結果，一旦已經如說明地將晶圓處理器 3 4之部 件 3 2注入模塑的話，稍後則經常必須將部件 3 2放置於第二模穴中，以用於以晶圓處理器 3 4 的另一模塑部件或元件而來重疊注塑。這是爲 什麼必須使薄膜 1 〇由持久性聚合物塑料製成 的另一原因。重複地暴露於模塑製程中的剪力 與高溫需要較佳熱塑性聚合物之使用。由本申 請人所擁有之審理中的美國專利申請案第 0 9 / 3 1 7，9 8 9號揭露出了重疊注塑以製造晶圓載 體之使用，其係並且在此以引用的方式倂入本 文。此外，美國專利第 6，4 3 9，9 8 4號揭露出晶 圓載體用的模塑技術，其係同樣地在此以引用 的方式倂入本文。 19 200301009 美國專利案第 6, 428, 729、 6, 039, 186、 5，4 8 5，0 9 4與 5，9 4 4，1 9 4號揭露出構成晶圓處理 裝置 3 4用的特別架構與製程，其係在此以引用 的方式倂入本文。在一具體實施例中，晶圓處 理器 3 4包括至少一體部 3 8以及具有複數個軸 向支撐架 42的一支撐結構 40，該支撐架能夠 藉著或靠近它們的周圍外圍而可接收地支撐該 晶圓或盤狀物。在架子 42上，該晶圓或盤狀物 係可習知地沿著徑方向向上或水平地從載體 3 4移除。架子 4 2用作晶圓與載體 3 4之間的主 要接觸點。結果，本發明之一具體實施例包括 將 E S D薄膜 1 0***模塑到至少一部份的此支 撐架構 40以及/或者支撐架 42。可將 ESD薄膜 1 0選擇性地放置於模塑單元 2 0的模穴 2 2內， 以致使它能遮蓋模塑部件的所有表面或邊側， 其中該模塑部件 32係爲支撐 40、支撐架 42、 架 42的有限預先界定部份、或各種其它的結 合。再者，可將薄膜 1 〇明確地接合，以對齊接 地路徑，譬如體部上的對應薄膜 1 〇，或晶圓處 理器 2 3的任何其它鄰近與可毗連元件，以提供 沿著晶圓處理器 3 4的延伸接地路徑。藉由促進 薄膜 1 〇之選擇性的可接合放置到靠近晶圓處 理器 3 4之任何表面或元件表面，可在沒有採用 將傳導性材料之各可接觸元件完全模塑之習知 技術的情形下，將接觸處理器 3 4元件引入到 20 200301009 E S D互連 。 在本發明的另一具體實施例中，晶圓處理器 3 4可包括沿著處理器體部 3 8之外面部份的凸 緣 4 4 (圖 6 )，以助於運輸，包括在半導體製程 期間內經由自動裝置的結合。這些凸緣 44可同 樣地包括***模塑的傳導薄膜 1 〇，以提供 E S D 優點。就其本身而論，體部 3 8的剩餘部份與表 面可由較無傳導性的聚合物所構成。圖 6進一 步說明到處理裝置 3 4之接地元件的各種重疊 注塑路徑，該處理裝置可引入與至少一傳導薄 膜 1 〇之選擇性佈置接觸，以致使組合的傳導性 互連在重疊注塑與***模塑薄膜與部件之間有 可能。仍進一步的具體實施例可包括於動態耦 合結構 4 6之被選定表面上的模塑薄膜 1 0，其 中動態耦合 4 6 (圖 7 )適於促進與處理裝置 3 4 的裝置結合，如美國專利案第 6，0 1 0，0 0 8號所 述。 在某些場合中，***模塑的功能性薄膜1 〇 不能足夠地黏附於其它的聚合物。例如，PEEK (聚芳醚酮）（亦即，薄膜1〇)無法在所有的 情形中黏附到重疊注塑的 P C (亦即，譬如體部 3 8的晶圓處理器 3 4元件）。參考圖 5，中間薄 膜或連結層，譬如 PEI (聚醚醯亞胺）被發現 可黏附到 PEEK (聚芳醚酮）與 PC (聚碳酸酯） 兩物質。因此，在注入 PC材料，而中間薄膜放 21 200301009 置於薄膜 1 〇與熔化可成形 P C材料 3 0中間之 前，可將至少兩聚合物薄膜的薄膜疊層 1 〇個別 地***於一模子裡，以作爲疊層。不然的話， 可將兩薄膜彼此黏附，其係譬如藉由在此所說 明的真空模塑、疊層製程，或者藉由其它的方 法，其中將兩層或薄膜在***與放置於模塑單 元 2 0內之前接合。其它的材料亦可利用，以促 進黏著以及可實施的模塑製程。 由於至少一傳導薄膜1 〇的此種選擇性接 合，所以可將表面-到-地面的互連建立，以導 引靜電電荷離開敏感元件或裝置。例如在這些 接觸點上，傳導性的 E S D薄膜 1 0提供對地面 的連續傳導性互連，藉此，而將任何電荷導引 離開敏感性半導體元件或裝置，以將代價高的 損害降到最小。部件 3 2上（亦即，載體內的架 子）之有限目標位置上之此薄膜 1 〇的使用，其 係允許終端使用者獲得 E S D的全部利益，而同 時亦能夠架構出剩下的部份、或整體的體部、 或其它較佳聚合物。此希望或者必要的薄膜1 0 材料可非常地不同於建構晶圓載體 3 4之剩下 部分，甚至其特定部件 3 2時所需要者。 晶片處理器/盤 在另一具體實施例中，處理裝置丨2是一晶片 盤 3 6，其係包括適於固定複數片之晶片的複數 個放置凹處或凹處組件 5 0，以及周圍邊牆 5 2， 22 200301009 如圖 8 - 9所示。美國專利第 5，4 8 4 , 0 6 2號與第 6，0 7 9 , 5 6 5號揭露出此種晶片盤，其係並且以引 用的方式倂入本文。由於在此所說之晶圓處理 器 3 4用的製程與材料，提供一 E S D路徑以引 導靜電電荷離開可接受晶片與/或製程裝置是 有益的。習知技術則典型地針對具有傳導特性 之聚合物之全部晶片盤 3 6的成形。如所述，此 習知技術是昂貴、無效、且經常令人不希望的。 本發明之一具體實施例包括將傳導薄膜 1 〇 ***模塑到晶片盤3 6的選定部份或表面，譬如 放置凹處 5 0，以便導引靜電電荷離開放置晶 片。其它的具體實施例可包括將薄膜 1 〇***模 塑到包括凹處 5 0、邊牆 5 2及其結合之盤 3 6的 全部頂部表面。 一般可將晶片盤 3 6的周圍邊牆 5 2成形，以 可與其它晶片盤 3 6堆疊結合。在盤 3 6底部部 份上的堆疊柱/元件與/或者周圍邊牆突出物的 尺寸與形狀可用來與盤 3 6之頂部表面上的對 應溝槽或唇狀物相對齊。可同樣地將一般熟諳 該技藝者所已知的其它堆疊技術與盤的設計想 像成與本發明一起實施。爲了提供接地的一傳 導路徑，可沿著來自放置凹處 5 0的區域，而將 薄膜 1 〇模塑到周圍邊牆 5 2，以沿著複數個堆 疊盤 3 6而提供傳導性互連。 由於晶圓處理器 3 4，將至少一傳導薄膜 1 0 23 200301009 選擇性地接合到晶片盤 3 6的被選定目標表 面，其係提供 E S D優點的較佳應用，而卻仍允 許製造者架構出令人希望之非傳導性聚合物之 盤 3 6的剩下部份。 本發明可以用其它特定的形式來實施，而不 會背離其精神與基本特性，而且令人因此希望 的是，在所有態樣中，本具體實施例可視爲是 說明性而非限制性。 圖式之簡單說明： 圖1係爲根據本發明一具體實施例而設計之 傳導薄膜***模塑系統的側橫剖圖。 圖 2係爲圖1之部分傳導薄膜***模塑系統 的側橫剖圖。 圖3係爲根據本發明一具體實施例而設計之 傳導薄膜***模塑系統的側橫剖圖。 圖 4係爲根據本發明一具體實施例而設計之 成形部件與接合傳導薄膜的側橫剖圖。 圖5係爲根據本發明一具體實施例而設計之 一模塑部件與接合傳導薄膜疊層的側橫剖圖。 圖 6係爲根據本發明一具體實施例而設計之 一半導體晶圓處理裝置的透視圖。 圖7係爲根據本發明一具體實施例而設計之 半導體晶圓處理裝置的分解透視圖。 圖8係爲根據本發明一具體實施例而設計之 可堆疊晶片處理裝置的透視圖。 24 200301009 圖9係爲根據本發明一具體實施例而設計之 可堆疊 晶 片 處 理 裝置的側橫 元件符 號 說 明 10 傳 導 薄 膜 12 半 導 體 元 件處理裝置 2 0 模 塑 單 元 2 2 模 穴 2 3 晶 圓 處 理 器 2 4 遮 蓋 部 份 2 6 成 形 表 面 2 8 注 入 通 道 2 9 真 空 通 道 3 0 可 塑 性 材 料 3 2 模 塑 部 件 3 4 晶 圓 處 理 裝置 3 5 載 體 3 6 晶 片 盤 3 8 體 部 4 0 支 撐 結 構 4 2 支 撐 架 4 4 凸 緣 4 6 動 態 耦 合 5 0 放 置 凹 處 5 2 周 圍 邊 牆200301009 发明 、 Invention and discussion of the invention The present invention filed a priority application No. 60/3 3 3, 6 8 6 on November 27, 1990. The title of the invention is to provide a polymer film for electrostatic discharge insert molding. , Which is hereby incorporated by reference. FIELD OF THE INVENTION The present invention relates generally to thin film insert molding, and more particularly to inserting a thin conductive polymer film during molding of a semiconductor element processor or carrier to provide electrostatic discharge away from the semiconductor element. Background of the Invention = Conventional film insert molding techniques are generally used in manufacturing processes to increase aesthetic appeal in various consumer products. Also β 卩, decorative patterns, instructions, trademarks, and other visual patterns are printed on one surface of a thin transparent polymer film for use in the insert molding process. Later developments expanded the use of films to permanently fix functional features such as barcodes to the product. In both cases, the film can be placed in a part of the mold before the plastic material is injected. This situation will produce a joint between the film and the joint portion, so that an inexpensive decoration or indicator can be selectively placed on the portion, but at the same time will be around the complex contour and difficult to reach locations The use of indicators is simplified. Similarly, by eliminating the need to subject the indicator to etching or forming the actual surface of the mold itself, this film insertion 200301009 molding or decorative molding will simplify the manufacturing process. This situation increases design and manufacturing flexibility and the level of detail that can be included in the final product. The semiconductor industry has introduced unique and unconventional requirements for purity and dirt resistance into the development and implementation of product design and manufacturing methods. Most importantly, the selection of materials is necessary in the manufacture, storage, and transportation of components and assemblies. For example, various polymer materials, such as polyetherimide (PE), polycarbonate (PC), polytetrafluoroethylene resin (PFA), polyaryletherketone (PEEK), and the like, are generally used to contain In the manufacture of components and structures that structure wafer carriers and wafer disks, wafer carriers = the process of processing wafer disks into integrated circuit wafers usually includes many steps. Here, the disks are repeatedly processed, Storage and transportation. Due to the fragile nature of the discs and their extreme fragility, it is necessary to properly protect them throughout this process. One purpose of wafer carriers is to provide this protection. In addition, since the processing of wafer disks is generally automated, it is necessary to accurately place the disks in relation to processing equipment for automatic removal and insertion of wafers. The second purpose of the wafer carrier is to securely hold the wafer disc during transport. The carrier is generally structured to align the wafer or disk axially in a rack or slot, and to support the wafer or disk by or near the peripheral edge. Conventionally, wafers or disks can be removed from the carrier upward or horizontally in the radial direction. The carrier may have an additional top cover, a bottom cover, or a housing that seals the wafer or disc. There are many material features that are useful and advantageous for wafer carriers, depending on the type of carrier and the particular part of the carrier. Due to the processing of semiconductor wafers or magnetic disks, the existence and generation of particulate matter presents a very obvious pollution problem. Pollution is considered to be the single largest cause of production loss in the semiconductor industry. Since the size of integrated circuits has been continuously reduced, the particle size of contaminated integrated circuits has also become smaller, which makes the reduction of pollutants even more important. Contaminants in the form of particles can be generated by abrasion, such as friction or cutting of carriers and wafers or discs, carrier covers or enclosures, storage racks, other carriers, or other process equipment. The most desirable feature of the carrier is therefore the effect of preventing the generation of particles in the abrasion, friction, or cutting of plastic molding materials. U.S. Patent No. 5,780,127 discloses various plastic properties related to the suitability of such materials for wafer carriers, which are incorporated herein by reference. Carrier materials should also have minimal leakage of volatile components. When they are likely to leave the film, they should also constitute contamination that can harm wafers and discs. When the carrier is loaded, the carrier material must have sufficient dimensional stability, that is, 200301009 stiffness. Dimensional stability is necessary in order to prevent damage to the wafer or disk and to minimize the movement of the wafer or disk within the carrier. The tolerance between the groove holding the wafer and the disc is basically very small, and any deformation of the carrier can directly damage the highly fragile wafer or increase wear, and when the wafer or disc is moved in, it will result from The carrier or particles within it. When the carrier is loaded in a certain direction, such as when the carriers are stacked during loading, or when the carrier is combined with a processing device, dimensional stability is also extremely important. The carrier material should also maintain its dimensional stability under the high temperatures that can be encountered during storage or cleaning. Conventional carriers used in the semiconductor industry can develop and retain electrostatic charging. When a charging plastic part is brought into contact with an electronic device or process device, it can be considered as an electrostatic discharge (ESD) injury phenomenon. In addition, electrostatically charged carriers attract and retain particles, especially particles that travel through the air. Similarly, the build-up of static electricity on the carrier can cause the semiconductor process device to shut down automatically. As a result, it is most desirable to have a carrier with electrostatic discharge characteristics to discharge E S D and avoid attracting particles. Wafer visibility in sealed containers is highly desirable and needed by end users. Transparent plastics suitable for this container, such as polycarbonate, are desirable in situations where the cost of the plastic is low, but the plastic does not have the inherent static discharge characteristics and wear resistance is desired. 200301009 Other important considerations include the cost of the carrier material and the ease of shaping the material. The carrier is typically formed of injection molded plastics such as pc (polycarbonate), ABS (acrylonitrile-butadiene-styrene copolymer), PP (polypropylene), PE (polyetherimide), PFA ( Polytetrafluoroethylene resin), PEEK (polyaryletherketone) and similar materials. A major benefit of specific specialty polymers, such as PEEK, is their anti-wear properties. Typical low-cost conventional plastics release tiny particles into the air when worn or even rubbed against other materials or objects. Although these particles are largely invisible to the naked eye, they lead to the introduction of potentially harmful contamination that can attach to the semiconductor component being processed, and into the environment that must be controlled. However, certain thermoplastic polymers are significantly more expensive than conventional polymers. In fact, the specific thermoplastic polymers vary greatly, that is, PEEK (polyaryletherketone) is more expensive than PC (polycarbonate). In addition to their anti-wear properties, thermoplastic polymers may have additives such as carbon fibers or powder fillers added to produce conductive properties. It has been added to injection molding plastics for electrostatic discharge fillings, including carbon powder or carbon fiber, metal fibers, metal-coated graphite, and organic (amine-based) additives. Therefore, thermoplastics with this additive can be used in the material architecture of semiconductor component processors to promote E S D. 10 200301009 The conventional implementation includes the use of a material, such as PEEK or other compatible materials, to form an integrated wafer carrier / processor element to promote ESD. However, as noted, the manufacture and use of special materials is significantly more expensive, and the use of such materials in the architecture of large processor components is often not desirable or even impractical. In addition, it is difficult to handle and mold materials such as PEEK (polyaryletherketone) in a manner necessary for manufacturing such a semiconductor processor. Manufacturers of wafer carriers are now forced to make a decision between the benefits of the E S D properties of conductive thermoplastics and the cost of manufacturing all or a substantial portion of the material. Although ESD-promoting materials are only needed for special applications on those contact surfaces of the carrier, which are in contact with fragile semiconductor components or processing devices, all or part of the processor is typically driven by ESD Polymer to prevent damage to components caused by static electricity. For example, Japanese patent applications JP62220516, JP8293536, JP3012949, JP9036216, and JP9162273 disclose various methods for forming all components from a wafer carrier having a thermoplastic characteristic of conductive properties, wherein the conductive characteristics are provided by, for example, a carbon filler, resin And similar conductive additives. Furthermore, the Japanese patent applications JP1013717 and JP 6 2 2 8 7 6 3 8 disclose the wafer carrier body, which has conductive rods or wirings extending along the surface of the wafer carrier to provide a ground path. These conventional tests on E S D 11 200301009 caused problems in manufacturing because of inefficiency and cost. In addition, the use of conductive metals in the wafer carrier architecture can cause contamination and lead to unacceptable component wear. As a result, in the semiconductor industry, the provision of electrostatic discharge is required for manufacturing technologies that substantially reduce unnecessary manufacturing processes and allow the goal and localization of conductive materials. This innovation will significantly reduce manufacturing and design costs by allowing the selective use of desired but often expensive thermoplastic polymers. Description of the invention = The present invention is generally related to the molding process of processors, carriers, carriers, trays and similar devices used in the semiconductor process industry, including a thin, conductive polymer film, such as a battery Systems and methods for carbon polymers. A conductive film of a predetermined size and shape is selectively placed along the forming surface in the cavity to align the desired target surface of the plastic material. The forming process causes the surface of the film to bond to the contact surface of the plastic material in order to permanently adhere the film to the plastic material. As a result, the compatible conductive polymer can be selectively bonded to only those target surfaces that require ESD. For example, a semiconductor wafer carrier support structure may include at least a portion of this conductive polymer film to provide a path to guide static electricity away from a receivable and secure wafer. Furthermore, the ESD film may include an additional film layer to include a thin film stack to be bonded to the semiconductor element processing device 12 200301009, and a polymer layer having other functional characteristics, such as abrasion resistance, heat resistance, Impedes absorption protection, chemical resistance, and countless other functional characteristics. The purpose and features of a specific embodiment of the present invention is that it can provide a cost-saving method for selectively utilizing a desired polymer and the corresponding functional characteristics of the polymer, wherein it is not necessary to utilize more polymers than needed. . Another object and feature of certain embodiments of the present invention is that a conductive thermoplastic film can be bonded to a portion of a wafer carrier, wafer tray, or other semiconductor component processor or contact sensitive component, component, or processing device. Conveyor to provide for ESD. In addition, this discharge minimizes the environmental electrostatic charge that attracts unwanted particles of pollution. A further object and feature of the specific embodiment of the present invention is the selective use of better wear-resistant polymer films for components used in the semiconductor industry. As such, E S D and desired abrasion resistance can be improved on target surfaces using a single polymer film or film stack. Still another object and feature of the specific embodiment of the present invention is to form a semiconductor device processing apparatus having a transparent or translucent polymer film surface area. This processing device is formed by forming a sufficiently thin material layer on the selected target structure of the device, and with or without an intermediate layer, the structure is overmolded to, for example, a PC (polycarbonate) material. It is formed by the body of the substantially transparent device. 13 200301009 Still another object and feature of certain embodiments of the present invention is that at least one conductive film can be insert-molded into various components of the semiconductor processing device to facilitate matte alignment with other components of the same device, or Stackable matte parts of substantially equivalent devices to provide conductive interconnects along a general ground path. Detailed description of the preferred embodiment: Referring to Figures 1-9, the present invention includes insert molding a conductive electrostatic discharge thermoplastic film 10 onto a selected target surface of a semiconductor element processing device 12 using a molding unit 20. E S D film At least one conductive or E S D film 10 is a thermoplastic polymer having a measurable degree of conductivity. The film 10 is at least partially defined by a limited thickness level. For example, a single thin film layer having a thickness of about 0.40 inches (40 thousandths) is promising. Preferably, a single thin film layer is less than or equal to about .30 inches (30 thousandths). Of course, the implementation of multilayer stacking will change the critically better thickness. It should be noted that in this application, the term conductivity includes various degrees of conductivity and / or E S D. In general, surface resistivity, or ohms per square, defines the conductivity of a substance. For the purposes of this application, conductivity will include antistatic, static discharge, and conductive characteristics. The acceptable resistivity range of the present invention is approximately greater than or less than 1 X 1 0 1 2 ohms per square, or between 1x10_5 ohms per square and 1x101: 14 200301009 ohms per square. This range is exemplary and provides an acceptable range as understood by those skilled in the art. Any compatible material can be used for the thin film 10, provided that it has effective conductive properties. For example, polyester, Polyimide (PI), Polyether Iniide (PEI), Poly Ether Ether Ketone (PEEK), Perfluoroalkoxy Resin (PFA) ), Fluorinated Ethylene Propylene (FEP), Polyvinylidene Fluoride (PVDF), Polymethyl Methacrylate (PMMA), Polyether Sulfone (PES), Polystyrene (PS), Polyphenylene Sulfide (PPS), and countless other compatible polymers are useful. A specific embodiment would include a thermoplastic material, which is an additive material having a conductive property such as carbon fiber or powder filler to promote ESD. These additives include carbon powder or fibers, metal fibers, metal-coated graphite, organic (amine-based) additives, and the like. Other polymers and additives that enhance the conductive properties of thermoplastics are equally well known to those skilled in the art and can be used without departing from the spirit and scope of the invention. As explained herein, the E S D function of the thin film 10 can provide a ground path and remove the charge from the relevant semiconductor element to reduce the attraction of particles and other contaminants. U.S. Application No. _, which is owned by the present applicant and is entitled "Semiconductor Element Processing Device with Functional Thin Film", which is incorporated herein by reference. In order to apply the conductive thin film 10 in the manufacture of the semiconductor device processing device 12, the thin film i 0 is generally cut into a predetermined shape and size according to the particular needs of the bonding application. After cutting, the film can then be heat-formed. The film 10 is generally thin and thin like a sheet to better promote plasticity, and is utilized for the transparent or translucent properties of the material. In addition to inserting a single conductive thin film 10 into a mold, a plurality of thin films 10 can be laminated to include a synthetic thin film structure and can be plastically bonded to a semiconductor element processing device 12. For example, various thin film layers may include different conductive strengths. In a specific embodiment, the film stack bonded to the surface of the processor 12 may have a higher conductivity than the outer layer to increase the effectiveness of the conduction path and minimize potential damage from static electricity. Still another embodiment may combine other thin film layers with the conductive thin film 10 to increase the abrasion resistance, chemical resistance, temperature resistance, absorption resistance, gas leakage resistance and similar characteristics to the processing device 1 which can moldably receive the film stack. 2 parts or surfaces. Various film lamination techniques known to those skilled in the art of film lamination are conceived for use with the present invention. For example, U.S. Patent Nos. 3, 660, 200, 4, 605, 591, 5, 194, 327, 5, 3 4 4, 7 0 3, and 5, 8 1 1, 1 9 7 expose the thermoplastic laminate 16 200301009 Technology is also incorporated herein by reference. E S D film insert molding Referring mainly to Figs. 1-7, the molding unit 20 generally includes a cavity 2 2, a covering portion 2 4, and at least one injection channel portion 28. The at least one injection channel 28 can be in fluid communication with the cavity 22. The cavity 22 may include a shaped surface 26 or more that is designed to mold the injected plastic material 30 and / or the film 10 during the molding process. The covering portion 2 4 selectively combines or covers the cavity 22. Various specific embodiments of the molding unit 20 may further include at least one vacuum channel 2 9 interconnected with the mold cavity 22 and / or the molding surface 26 to fix a substance such as a film 10 to the mold cavity 2 2 Introduce vacuum suction. Other known techniques for fixedly conforming the film 10 within the cavity 22 and applying a static fixation and forcing to form the surface 26 are similarly conceivable for use with the present invention. It should be noted that several figures depict the film 10 as disproportionately large compared to the corresponding processing device, which is for illustration purposes only and is not intended to represent the true scale used in the present invention. In a specific embodiment, the covering portion 24 is movably fixed to the cavity 22 to facilitate the insertion of the film 10 and the movement of the processing device portion or component 32 after completion. The molded part 3 2 is generally smaller than the finished processing device 12. For example, it is common to mold the side wall insert separately from the wafer carrier and often in a different plastic than the carrier body. 17 200301009 Various injection and insert molding techniques are known to those skilled in the art, and they can be implemented without departing from the spirit and scope of the present invention. The plastic material 30 is preferably a substantially non-conductive thermoplastic material, which is generally used in molded parts used in the semiconductor process industry. In addition, the material 30 may be PFA (polytetrafluoroethylene resin), PE (polyetherimide), PC (polycarbonate), and the like. More specifically, the plastic material 30 may be a material conventionally used to structure a wafer carrier, a wafer tray, and its components and parts. When in operation, the conductive film 10 can be cut into a predetermined shape, and then heated to form a desired form. The heat-formed film 10 is placed in the molding unit 20 such that the surface of the film 10 is in contact with at least a part of at least one of the molding surfaces 26 of the cavity 22. As noted herein, various techniques such as vacuum, static, and compulsory fixation can be implemented to help properly place the film 10 on the cavity 22 or the forming surface 26. The covering portion 24 can then be sealed to prepare the material 30 for injection. During this stage of the process, the plastic material 30 is injected into the cavity in a substantially molten state via at least one injection channel 28. After waiting for an indispensable cooling period, the plastic material 30 in the molding unit 20 is cooled to form a substantially solid molded part 32. The melt injection combined with the cooling process forms a permanent adhesive bond between at least one film 10 and the molded part 32. 18 200301009 After the molding process is completed, the molded part 32 can be discharged from the molding unit 32, and the conductive film 10 of the part 32 can be permanently bonded to the selected target surface. It is a process, technique, and implementation known to those skilled in the art that can be used for the injection of material 30 and the discharge of parts 32. Wafer Processors / Carriers Various conventional wafer processing devices 34 and devices 34 are shown in Figures 4-7. The conductive thin film 10 or the thin film stack may be bonded to selected components and / or portions of the wafer processing apparatus 3 4 (that is, a wafer carrier) by a thin film insertion molding process referred to herein. The wafer processor 3 4-is generally formed from at least two different molten processable materials. As a result, once the component 32 of the wafer processor 3 4 has been injection-molded as described, it is often necessary later to place the component 32 in the second cavity for the wafer processor 3 4 Another overmolded part or component. This is another reason why the film 10 must be made of a durable polymer plastic. Repeated exposure to shear and high temperatures during the molding process requires the use of better thermoplastic polymers. The pending U.S. patent application No. 0 9/3 1 7, 9 8 9 owned by the present applicant discloses the use of overmolding to manufacture a wafer carrier, which is hereby incorporated herein by reference. . In addition, U.S. Patent No. 6,4 3,9,84 discloses molding techniques for wafer carriers, which are also incorporated herein by reference. 19 200301009 U.S. Patent Nos. 6, 428, 729, 6, 039, 186, 5, 4 8 5, 0 9 4 and 5, 9 4 4, 1 9 4 disclose the special use of the wafer processing device 34. The architecture and processes are incorporated herein by reference. In a specific embodiment, the wafer processor 34 includes at least one integrated portion 38 and a support structure 40 having a plurality of axial support frames 42 that can be received receivably by or near their peripheral periphery. Support the wafer or disk. On the shelf 42, the wafer or disk is conventionally removed from the carrier 34 in a radial direction or horizontally. The shelf 42 is used as the main contact point between the wafer and the carrier 34. As a result, a specific embodiment of the present invention includes inserting an ESD film 10 into at least a portion of the support structure 40 and / or the support frame 42. The ESD film 10 can be selectively placed in the cavity 22 of the molding unit 20 so that it can cover all surfaces or sides of the molded part, wherein the molded part 32 is a support 40, a support The shelf 42, a limited pre-defined portion of the shelf 42, or various other combinations. Furthermore, the film 10 can be explicitly bonded to align the ground path, such as the corresponding film 10 on the body, or any other adjacent and adjoinable components of the wafer processor 23 to provide processing along the wafer. Device 3 4 extends the ground path. By promoting the selectively bondable placement of the thin film 10 to any surface or component surface close to the wafer processor 34, it is possible to use the conventional technique without fully molding the contactable components of the conductive material Next, the contact processor 3 4 components are introduced to the 20 200301009 ESD interconnect. In another embodiment of the present invention, the wafer processor 34 may include a flange 4 4 (FIG. 6) along the outer portion of the processor body 38 to facilitate transportation, including in the semiconductor process. During the integration via automatic devices. These flanges 44 may also include insert molded conductive films 10 to provide E S D advantages. For its part, the remainder and surface of the body 38 may be composed of a less conductive polymer. FIG. 6 further illustrates various overmolding paths to the grounding element of the processing device 34, which processing device may introduce selective placement contact with at least one conductive film 10 so that the combined conductive interconnects in the overmolding and insert mold Possible between plastic film and parts. Still further specific embodiments may include a molded film 10 on a selected surface of a dynamic coupling structure 46, wherein the dynamic coupling 4 6 (FIG. 7) is adapted to facilitate device integration with the processing device 34, such as a US patent Case No. 6, 0 1 0, 0 0 8 described. In some cases, the insert-molded functional film 10 cannot sufficiently adhere to other polymers. For example, PEEK (polyaryletherketone) (ie, film 10) cannot adhere to the overmolded PC (ie, wafer processor 34 components such as body 38) in all cases. Referring to Figure 5, an intermediate film or tie layer, such as PEI (polyether sulfonimide), was found to adhere to both PEEK (polyaryletherketone) and PC (polycarbonate). Therefore, before injecting the PC material and placing the intermediate film 21 200301009 between the film 10 and the meltable formable PC material 30, the film stack 10 of at least two polymer films can be individually inserted into a mold, Take as a stack. Otherwise, the two films can be adhered to each other, for example, by the vacuum molding, lamination process described herein, or by other methods, in which two layers or films are inserted and placed in the molding unit 2 Engage before 0. Other materials can also be used to promote adhesion and implementable molding processes. Because of this selective bonding of at least one conductive film 10, surface-to-ground interconnections can be established to direct electrostatic charges away from sensitive components or devices. For example, at these contact points, a conductive ESD film 10 provides continuous conductive interconnection to the ground, thereby directing any charge away from sensitive semiconductor components or devices to minimize costly damage . The use of this film 10 at a limited target position on part 32 (ie, the shelf in the carrier) allows the end user to obtain the full benefits of ESD, while at the same time being able to structure the remaining parts, Or a whole body, or another preferred polymer. This desired or necessary film 10 material can be very different from what is needed to construct the remainder of the wafer carrier 34, or even its specific components 32. Wafer processor / disk In another specific embodiment, the processing device 2 is a wafer tray 36, which includes a plurality of placement recesses or recess components 50 adapted to hold a plurality of wafers, and a peripheral edge Wall 5 2, 22 200301009 is shown in Figure 8-9. U.S. Patent Nos. 5,4 84, 062 and 6,079, 565 disclose such wafer discs, which are incorporated herein by reference. Because of the processes and materials used herein for the wafer handler 34, it is beneficial to provide an ESD path to direct electrostatic charge away from the acceptable wafer and / or process equipment. Conventional techniques are typically directed to the formation of all wafer disks 36 of polymers having conductive properties. As mentioned, this conventional technique is expensive, ineffective, and often undesirable. A specific embodiment of the present invention includes inserting a conductive film 10 into a selected portion or surface of the wafer tray 36, such as a recess 50, to guide the electrostatic charge away from the wafer. Other specific embodiments may include inserting the film 10 into the entire top surface including the recess 50, the side wall 52, and the combined disk 36. Generally, the surrounding sidewalls 52 of the wafer trays 36 can be formed so as to be stacked with other wafer trays 36. The size and shape of the stacked posts / elements and / or surrounding side wall protrusions on the bottom portion of the tray 36 can be aligned with corresponding grooves or lips on the top surface of the tray 36. Other stacking techniques and tray designs known to those skilled in the art can similarly be imagined to be implemented with the present invention. To provide a conductive path to ground, the film 10 may be molded to the surrounding side wall 52 along the area from which the recess 50 is placed to provide conductive interconnects along a plurality of stacked disks 36. Since the wafer processor 34 selectively attaches at least one conductive film 1023200301009 to the selected target surface of the wafer tray 36, it is a better application that provides the advantages of ESD, while still allowing the manufacturer to construct The remainder of the promising non-conductive polymer plate 36. The invention may be embodied in other specific forms without departing from its spirit or essential characteristics, and it is therefore desirable that, in all aspects, this particular embodiment be considered as illustrative and not restrictive. Brief description of the drawings: Fig. 1 is a side cross-sectional view of a conductive film insertion molding system designed according to a specific embodiment of the present invention. FIG. 2 is a side cross-sectional view of a part of the conductive film insertion molding system of FIG. 1. FIG. Fig. 3 is a side cross-sectional view of a conductive film insertion molding system designed according to an embodiment of the present invention. Fig. 4 is a side cross-sectional view of a molded component and a bonding conductive film designed according to a specific embodiment of the present invention. Fig. 5 is a side cross-sectional view of a laminate of a molded part and a bonding conductive film designed according to a specific embodiment of the present invention. FIG. 6 is a perspective view of a semiconductor wafer processing apparatus designed according to an embodiment of the present invention. FIG. 7 is an exploded perspective view of a semiconductor wafer processing apparatus designed according to an embodiment of the present invention. Fig. 8 is a perspective view of a stackable wafer processing apparatus designed according to an embodiment of the present invention. 24 200301009 FIG. 9 is a side cross element symbol description of a stackable wafer processing device designed according to a specific embodiment of the present invention 10 conductive film 12 semiconductor element processing device 2 0 molding unit 2 2 cavity 2 3 wafer processor 2 4 Covering part 2 6 Forming surface 2 8 Injection channel 2 9 Vacuum channel 3 0 Plastic material 3 2 Molded part 3 4 Wafer processing device 3 5 Carrier 3 6 Wafer tray 3 8 Body 4 0 Support structure 4 2 Support Frame 4 4 Flange 4 6 Dynamic coupling 5 0 Place recess 5 2 Surrounding side wall
2525