SU473387A3 - Диодна матрица - Google Patents
Диодна матрицаInfo
- Publication number
- SU473387A3 SU473387A3 SU1246034A SU1246034A SU473387A3 SU 473387 A3 SU473387 A3 SU 473387A3 SU 1246034 A SU1246034 A SU 1246034A SU 1246034 A SU1246034 A SU 1246034A SU 473387 A3 SU473387 A3 SU 473387A3
- Authority
- SU
- USSR - Soviet Union
- Prior art keywords
- gold
- strips
- matrix
- oxide
- layer
- Prior art date
Links
- 239000011159 matrix material Substances 0.000 title abstract description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 11
- 239000010931 gold Substances 0.000 abstract description 11
- 229910052737 gold Inorganic materials 0.000 abstract description 11
- 239000004020 conductor Substances 0.000 abstract description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052759 nickel Inorganic materials 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000004347 surface barrier Methods 0.000 abstract description 3
- 230000008021 deposition Effects 0.000 abstract 3
- 229910018487 Ni—Cr Inorganic materials 0.000 abstract 2
- 239000003963 antioxidant agent Substances 0.000 abstract 1
- 230000003078 antioxidant effect Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000005669 field effect Effects 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910001120 nichrome Inorganic materials 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
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- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
- Manufacture Or Reproduction Of Printing Formes (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Element Separation (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
(54) ДИОДНАЯ МАТРИЦА
Изобретение относитс к радиотехнике, в
частности к изготовлению интегральных схем запоминающих устройств.
Известны диодные матрицы в виде сформованных на покрытой слоем двуокиси кремни полупроводниковой пластине диодов.
Цель изобретени - повышение надежности и упрощение технологии изготовлени матрицы - достигаетс тем, что полупроводникова пластина предлагаемой матрицы разделена на р д параллельных полос, на нижние плоскости которых нанесены металлические шины, например из золота, образующие с поверхностью полупроводника омическпй контакт, а на слой двуокиси кремни нанесены полоски металла, расположенные перпендикул рно шинам, причем анод каждого диода электрически соединен с расположенными на слое двуокиси кре.мпи полосками металла.
На фиг. 1 показан общий вид матрицы; на фиг. 2 - монтажна схема; на фиг. 3 - монтажна схема диодной матрицы одностороннего запоминающего устройства; на фиг. 4- часть диодной матрицы в разрезе.
Полупроводникова пластина 1, выполненна , например, из кремни , обработана дл получени проводника /г-типа. Нижн ее плоскость имеет малое удельное сопротивление , а верхн , эпитаксиально выращенна на нижней, - сравнительно высокое. Пластина
разделена на р д параллельных полос одинаковой ширины более узкими промежутками. На нижние плоскости полос нанесены щины 2, например, из золота, образующие с поверхностью проводника омпческпй контакт. Эти шины вл ютс горизонтальными проводниками диодной матрицы, их ширина равна ширине полупроводниковых полос. Верхн поверхность пластины, за исключением небольших
участков, покрыта тонким слоем двуокиси кремни 3, на который нанесен слой металла 4, например золота, образующий контакт, называемый поверхностно-барьерным.
Металлический (золотой) слой 4 вл етс
диодом, а нижн плоскость полупроводниковой пластины - катодом. Диоды 5, характеризуюпи1ес значительным быстродействием, соединены перемычкой 6 из металла с относительно большим удельным сопротивлением,
например нихрома, с полосками металла 7. преимущественно золота, расположенными на слое 3 на верхней плоскости пластины 1. Полоскп 7, перпендикул рные полупроводниковым полосам пластины, вл ютс вертикальными проводниками матрицы. Кроме того, эти полоскп, прочно припа нные к пластине, удерживают полупроводниковые полосы вместе на определенном рассто нии одну от другой, что обеспечиваетс сло ми нихрома 8 и никел 9,
на которые нанесен электролитическим путем
золотой слой 10, преп тствующий окислению никел .
Блок представл ет собой полную диодную матрицу, в которой каждый диод 5 односторопие соедин ет полоски 7 с шинами 2.
Изолировав некоторые диоды 5 от полосок 7, можно из полной матрицы получить иеполЕ1ую диодиую матрицу, котора может действовать как одиостороииее запоминающее устройство . При этом кажда полоска соедин етс только с определе}1ной щииой 2 через остальные неизолированные диоды. Дл изол ции диодов полоску 7 подсоедин ют к положительному полюсу источника напр жени , другой полюс подключают к щиие 2, к которой подсоединены катоды изолиропапных диодов. Разность напр женпй между полоской и шиной такова, что образуетс ток, достаточный дл расплавлени перемычек 6, в результате чего металл 4 соедин етс с аподом диода.
При подаче входного сигнала на оиределенную полоску выходпой сигнал ио вл етс на тех щииах, которые соединены полосками через пере.мычки и диоды. Таким образом получаетс одностороннее заноминающее устройство , быстродействие которого обеспечиваетс быстродействием диодов и у.меиьшением емкостной св зн между элементами схемы.
Предмет изобретени
Диодна матрица з виде сформованных на покрытой слоем двуокиси кремни иолупроводииковой иластиие диодов, отличающа с тем, что, с целью повыщени ее надежиости и упрощени технологии изготовлени , полупроводнико: а пластина разделена па р д параллельных полос, на нижние плоскости которых нанесены металлические щипы, например из золота, образующие с поиерхиоСТ1ЛО полупроводника омический контакт, а па слой двуокиси крем) папесепы полоски металла , расположенные перпендикул рно шинам , иричем апод каждого электрически соедипеп с расположенными па слое двуокиси кремии полосками металла.
%
6
-J-x:,-j - /
Фиг 5
Фиг if
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT1664467 | 1967-05-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
SU473387A3 true SU473387A3 (ru) | 1975-06-05 |
Family
ID=11149070
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SU1246034A SU473387A3 (ru) | 1967-05-30 | 1968-05-30 | Диодна матрица |
Country Status (6)
Country | Link |
---|---|
US (1) | US3555365A (ru) |
DE (1) | DE1764378C3 (ru) |
FR (1) | FR1585038A (ru) |
GB (1) | GB1220843A (ru) |
SU (1) | SU473387A3 (ru) |
YU (1) | YU32377B (ru) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3699395A (en) * | 1970-01-02 | 1972-10-17 | Rca Corp | Semiconductor devices including fusible elements |
DE2023219C3 (de) * | 1970-05-12 | 1979-09-06 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Programmierbarer Halbleiter-Festwertspeicher |
US3699403A (en) * | 1970-10-23 | 1972-10-17 | Rca Corp | Fusible semiconductor device including means for reducing the required fusing current |
BE794202A (fr) * | 1972-01-19 | 1973-05-16 | Intel Corp | Liaison fusible pour circuit integre sur substrat semi-conducteur pour memoires |
GB1445479A (en) * | 1974-01-22 | 1976-08-11 | Raytheon Co | Electrical fuses |
FR2311410A1 (fr) * | 1975-05-13 | 1976-12-10 | Thomson Csf | Circuit de commutation integre, matrice de commutation et circuits logiques utilisant ledit circuit |
US4032949A (en) * | 1975-05-15 | 1977-06-28 | Raytheon Company | Integrated circuit fusing technique |
GB1532286A (en) * | 1976-10-07 | 1978-11-15 | Elliott Bros | Manufacture of electro-luminescent display devices |
NL8002634A (nl) * | 1980-05-08 | 1981-12-01 | Philips Nv | Programmeerbare halfgeleiderinrichting en werkwijze ter vervaardiging daarvan. |
US4412308A (en) * | 1981-06-15 | 1983-10-25 | International Business Machines Corporation | Programmable bipolar structures |
US4518981A (en) * | 1981-11-12 | 1985-05-21 | Advanced Micro Devices, Inc. | Merged platinum silicide fuse and Schottky diode and method of manufacture thereof |
US4974048A (en) * | 1989-03-10 | 1990-11-27 | The Boeing Company | Integrated circuit having reroutable conductive paths |
US5139883A (en) * | 1989-05-09 | 1992-08-18 | Grigory Raykhtsaum | Intermetallic time-temperature integration fuse |
US5247735A (en) * | 1991-12-18 | 1993-09-28 | International Business Machines Corporation | Electrical wire deletion |
US5914648A (en) | 1995-03-07 | 1999-06-22 | Caddock Electronics, Inc. | Fault current fusing resistor and method |
US6059917A (en) * | 1995-12-08 | 2000-05-09 | Texas Instruments Incorporated | Control of parallelism during semiconductor die attach |
US5731624A (en) * | 1996-06-28 | 1998-03-24 | International Business Machines Corporation | Integrated pad and fuse structure for planar copper metallurgy |
-
1968
- 1968-05-28 YU YU1235/68A patent/YU32377B/xx unknown
- 1968-05-28 DE DE1764378A patent/DE1764378C3/de not_active Expired
- 1968-05-28 GB GB25487/68A patent/GB1220843A/en not_active Expired
- 1968-05-29 US US732988A patent/US3555365A/en not_active Expired - Lifetime
- 1968-05-30 SU SU1246034A patent/SU473387A3/ru active
- 1968-05-30 FR FR1585038D patent/FR1585038A/fr not_active Expired
Also Published As
Publication number | Publication date |
---|---|
GB1220843A (en) | 1971-01-27 |
DE1764378C3 (de) | 1973-12-20 |
DE1764378B2 (de) | 1973-05-17 |
US3555365A (en) | 1971-01-12 |
YU32377B (en) | 1974-10-31 |
YU123568A (en) | 1974-04-30 |
FR1585038A (ru) | 1970-01-09 |
DE1764378A1 (de) | 1972-03-23 |
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