SG91840A1 - An inductor or low loss interconnect and a method of manufacturing an inductor or low loss interconnect in an integrated circuit - Google Patents

An inductor or low loss interconnect and a method of manufacturing an inductor or low loss interconnect in an integrated circuit

Info

Publication number
SG91840A1
SG91840A1 SG9905340A SG1999005340A SG91840A1 SG 91840 A1 SG91840 A1 SG 91840A1 SG 9905340 A SG9905340 A SG 9905340A SG 1999005340 A SG1999005340 A SG 1999005340A SG 91840 A1 SG91840 A1 SG 91840A1
Authority
SG
Singapore
Prior art keywords
inductor
low loss
loss interconnect
interconnect
manufacturing
Prior art date
Application number
SG9905340A
Other languages
English (en)
Inventor
Belk Nathan
Thomas Cochran William
Ranjit Frei Michel
Moinian Shahriar
K Ng Kwok
Richard Pinto Mark
Xie Ya-Hong
Clayton Goldthorp David
Original Assignee
Lucent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/386,132 external-priority patent/US6225182B1/en
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
Publication of SG91840A1 publication Critical patent/SG91840A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Coils Or Transformers For Communication (AREA)
SG9905340A 1998-11-04 1999-10-27 An inductor or low loss interconnect and a method of manufacturing an inductor or low loss interconnect in an integrated circuit SG91840A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10694598P 1998-11-04 1998-11-04
US12447899P 1999-03-15 1999-03-15
US09/386,132 US6225182B1 (en) 1999-08-30 1999-08-30 Simplified high Q inductor substrate

Publications (1)

Publication Number Publication Date
SG91840A1 true SG91840A1 (en) 2002-10-15

Family

ID=27380226

Family Applications (2)

Application Number Title Priority Date Filing Date
SG9905340A SG91840A1 (en) 1998-11-04 1999-10-27 An inductor or low loss interconnect and a method of manufacturing an inductor or low loss interconnect in an integrated circuit
SG9905440A SG87846A1 (en) 1998-11-04 1999-11-02 Simplified high q inductor substrate

Family Applications After (1)

Application Number Title Priority Date Filing Date
SG9905440A SG87846A1 (en) 1998-11-04 1999-11-02 Simplified high q inductor substrate

Country Status (7)

Country Link
US (1) US6410974B2 (fr)
EP (2) EP0999579B1 (fr)
JP (1) JP2000150783A (fr)
KR (1) KR20000035195A (fr)
DE (2) DE69936175T2 (fr)
SG (2) SG91840A1 (fr)
TW (2) TW437085B (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8421158B2 (en) 1998-12-21 2013-04-16 Megica Corporation Chip structure with a passive device and method for forming the same
US6303423B1 (en) * 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
US8021976B2 (en) 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US8178435B2 (en) 1998-12-21 2012-05-15 Megica Corporation High performance system-on-chip inductor using post passivation process
JP4969715B2 (ja) * 2000-06-06 2012-07-04 ルネサスエレクトロニクス株式会社 半導体装置
JPWO2002056381A1 (ja) 2001-01-16 2004-05-20 ソニー株式会社 半導体装置及びその製造方法
US6759275B1 (en) 2001-09-04 2004-07-06 Megic Corporation Method for making high-performance RF integrated circuits
JP3898024B2 (ja) 2001-10-19 2007-03-28 Ｎｅｃエレクトロニクス株式会社 集積回路及びその製造方法
US8384189B2 (en) 2005-03-29 2013-02-26 Megica Corporation High performance system-on-chip using post passivation process
CN102157494B (zh) 2005-07-22 2013-05-01 米辑电子股份有限公司 线路组件
US8749021B2 (en) 2006-12-26 2014-06-10 Megit Acquisition Corp. Voltage regulator integrated with semiconductor chip
JP5335931B2 (ja) 2008-12-26 2013-11-06 メギカ・コーポレイション 電力管理集積回路を有するチップ・パッケージおよび関連技術
DE102011016159B3 (de) 2011-04-05 2012-10-18 Micronas Gmbh Anordnung aus einem integrierten passiven Bauelement und einem auf einem Metallträger angeordneten Halbleiterkörper
DE102011100485B4 (de) 2011-05-04 2016-04-28 Micronas Gmbh Integriertes passives Bauelement sowie dessen Verwendung
DE102011100487A1 (de) 2011-05-04 2012-11-08 Micronas Gmbh Integriertes passives Bauelement

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2194677A (en) * 1984-08-08 1988-03-09 Japan Res Dev Corp Tunnel injection static induction transistor and its integrated circuit
EP0262723A2 (fr) * 1986-10-01 1988-04-06 STMicroelectronics S.r.l. Procédé pour la fabrication d'un dispositif semi-conducteur monolithique haute tension
US4960725A (en) * 1985-09-25 1990-10-02 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing process for providing device regions on the semiconductor device and isolation regions to isolate the device regions from each other.
US5805043A (en) * 1996-10-02 1998-09-08 Itt Industries, Inc. High Q compact inductors for monolithic integrated circuit applications

Family Cites Families (16)

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Publication number Priority date Publication date Assignee Title
US3878001A (en) * 1970-07-13 1975-04-15 Siemens Ag Method of making a hypersensitive semiconductor tuning diode
US4224631A (en) * 1978-10-25 1980-09-23 Raytheon Company Semiconductor voltage reference device
US4458158A (en) * 1979-03-12 1984-07-03 Sprague Electric Company IC Including small signal and power devices
KR940004847A (ko) * 1992-08-04 1994-03-16 리차드 제이. 컬 낮은 드레쉬 홀드 전압을 갖는 에피택셜 이중 확산형 금속 산화 실리콘(dmos) 트랜지스터 구조체 형성방법
DE69434937D1 (de) 1994-06-23 2007-04-19 St Microelectronics Srl Verfahren zur Herstellung von Leistungsbauteilen in MOS-Technologie
GB2301706A (en) * 1995-06-01 1996-12-11 Plessey Semiconductors Ltd Intergrated inductor arrangement
US5712501A (en) 1995-10-10 1998-01-27 Motorola, Inc. Graded-channel semiconductor device
JP4061418B2 (ja) * 1996-07-30 2008-03-19 株式会社Ｓｕｍｃｏ シリコン基板とその製造方法
US5831331A (en) * 1996-11-22 1998-11-03 Philips Electronics North America Corporation Self-shielding inductor for multi-layer semiconductor integrated circuits
US5734194A (en) 1997-01-31 1998-03-31 Motorola, Inc. Semiconductor device and method of making
US6093951A (en) * 1997-06-30 2000-07-25 Sun Microsystems, Inc. MOS devices with retrograde pocket regions
JP2001527292A (ja) * 1997-12-22 2001-12-25 アイハーピー ゲーエムベーハー イノヴェーションズ フォー パフォーマンス マイクロエレクトロニクス インスティテュート フュア イノヴェーティブ マイクロエレクトロニクス 集積回路のための埋設絶縁層を有する半導体基板
US6169008B1 (en) * 1998-05-16 2001-01-02 Winbond Electronics Corp. High Q inductor and its forming method
US6020611A (en) 1998-06-10 2000-02-01 Motorola, Inc. Semiconductor component and method of manufacture
US6064088A (en) * 1998-06-15 2000-05-16 Xemod, Inc. RF power MOSFET device with extended linear region of transconductance characteristic at low drain current
US5918121A (en) * 1998-07-09 1999-06-29 Winbond Electronics Corp. Method of reducing substrate losses in inductor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2194677A (en) * 1984-08-08 1988-03-09 Japan Res Dev Corp Tunnel injection static induction transistor and its integrated circuit
US4960725A (en) * 1985-09-25 1990-10-02 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing process for providing device regions on the semiconductor device and isolation regions to isolate the device regions from each other.
EP0262723A2 (fr) * 1986-10-01 1988-04-06 STMicroelectronics S.r.l. Procédé pour la fabrication d'un dispositif semi-conducteur monolithique haute tension
US5805043A (en) * 1996-10-02 1998-09-08 Itt Industries, Inc. High Q compact inductors for monolithic integrated circuit applications

Also Published As

Publication number Publication date
DE69936175D1 (de) 2007-07-12
US20010009795A1 (en) 2001-07-26
KR20000035195A (ko) 2000-06-26
TW437085B (en) 2001-05-28
SG87846A1 (en) 2002-04-16
DE69937868D1 (de) 2008-02-14
EP0999579A2 (fr) 2000-05-10
EP0999580B1 (fr) 2008-01-02
DE69936175T2 (de) 2008-01-24
EP0999579B1 (fr) 2007-05-30
JP2000150783A (ja) 2000-05-30
TW550654B (en) 2003-09-01
DE69937868T2 (de) 2009-01-02
EP0999580A3 (fr) 2003-06-04
US6410974B2 (en) 2002-06-25
EP0999580A2 (fr) 2000-05-10
EP0999579A3 (fr) 2003-06-04

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