SG11202006671PA - Semiconductor package and method of forming the same - Google Patents

Semiconductor package and method of forming the same

Info

Publication number
SG11202006671PA
SG11202006671PA SG11202006671PA SG11202006671PA SG11202006671PA SG 11202006671P A SG11202006671P A SG 11202006671PA SG 11202006671P A SG11202006671P A SG 11202006671PA SG 11202006671P A SG11202006671P A SG 11202006671PA SG 11202006671P A SG11202006671P A SG 11202006671PA
Authority
SG
Singapore
Prior art keywords
forming
same
semiconductor package
package
semiconductor
Prior art date
Application number
SG11202006671PA
Inventor
Teck Guan Lim
Hideaki Fukuzawa
Hang Liu
Original Assignee
Agency Science Tech & Res
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency Science Tech & Res filed Critical Agency Science Tech & Res
Publication of SG11202006671PA publication Critical patent/SG11202006671PA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
SG11202006671PA 2018-01-29 2019-01-28 Semiconductor package and method of forming the same SG11202006671PA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SG10201800726W 2018-01-29
PCT/SG2019/050043 WO2019147189A1 (en) 2018-01-29 2019-01-28 Semiconductor package and method of forming the same

Publications (1)

Publication Number Publication Date
SG11202006671PA true SG11202006671PA (en) 2020-08-28

Family

ID=67395601

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202006671PA SG11202006671PA (en) 2018-01-29 2019-01-28 Semiconductor package and method of forming the same

Country Status (3)

Country Link
US (1) US11177318B2 (en)
SG (1) SG11202006671PA (en)
WO (1) WO2019147189A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11450626B2 (en) * 2020-08-25 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994007349A1 (en) 1992-09-24 1994-03-31 Hughes Aircraft Company Magnetic vias within multi-layer, 3-dimensional structures/substrates
US6092281A (en) 1998-08-28 2000-07-25 Amkor Technology, Inc. Electromagnetic interference shield driver and method
JP3821630B2 (en) 2000-03-31 2006-09-13 株式会社東芝 High frequency shield structure
KR100432361B1 (en) * 2001-05-29 2004-05-22 김성열 Lead-through type filter with improved function of shielding
US6603193B2 (en) 2001-09-06 2003-08-05 Silicon Bandwidth Inc. Semiconductor package
US6720597B2 (en) 2001-11-13 2004-04-13 Motorola, Inc. Cladding of a conductive interconnect for programming a MRAM device using multiple magnetic layers
US6940153B2 (en) 2003-02-05 2005-09-06 Hewlett-Packard Development Company, L.P. Magnetic shielding for magnetic random access memory card
KR100755088B1 (en) * 2003-03-28 2007-09-03 티디케이가부시기가이샤 Multilayered substrate and manufacturing method thereof
CN1681119A (en) 2004-04-09 2005-10-12 曾世宪 IC device and production thereof
US20060289970A1 (en) 2005-06-28 2006-12-28 Dietmar Gogl Magnetic shielding of MRAM chips
US7427803B2 (en) * 2006-09-22 2008-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Electromagnetic shielding using through-silicon vias
US7648858B2 (en) 2007-06-19 2010-01-19 Freescale Semiconductor, Inc. Methods and apparatus for EMI shielding in multi-chip modules
US7651889B2 (en) 2007-09-13 2010-01-26 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
US20090201654A1 (en) 2008-02-08 2009-08-13 Lambert Simonovich Method and system for improving electrical performance of vias for high data rate transmission
US8378466B2 (en) 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
US8624127B2 (en) * 2010-02-26 2014-01-07 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
JP2012151353A (en) * 2011-01-20 2012-08-09 Sharp Corp Semiconductor module
US9070692B2 (en) 2013-01-12 2015-06-30 Avalanche Technology, Inc. Shields for magnetic memory chip packages
US8952504B2 (en) 2013-02-08 2015-02-10 Qualcomm Incorporated Small form factor magnetic shield for magnetorestrictive random access memory (MRAM)
US10510946B2 (en) 2015-07-23 2019-12-17 Globalfoundries Singapore Pte. Ltd. MRAM chip magnetic shielding
JP2016192445A (en) * 2015-03-30 2016-11-10 株式会社東芝 Memory device
US9786839B2 (en) 2015-07-23 2017-10-10 Globalfoundries Singapore Pte. Ltd. 3D MRAM with through silicon vias or through silicon trenches magnetic shielding
KR102444235B1 (en) 2015-08-13 2022-09-16 삼성전자주식회사 MRAM(Magnetic Random Access Memory) device and MRAM package comprising magnetic shielding layer and methods for the MRAM device and the MRAM package

Also Published As

Publication number Publication date
WO2019147189A1 (en) 2019-08-01
US20200350363A1 (en) 2020-11-05
US11177318B2 (en) 2021-11-16

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