SG10201913140RA - Semiconductor package and method of forming the same - Google Patents
Semiconductor package and method of forming the sameInfo
- Publication number
- SG10201913140RA SG10201913140RA SG10201913140RA SG10201913140RA SG10201913140RA SG 10201913140R A SG10201913140R A SG 10201913140RA SG 10201913140R A SG10201913140R A SG 10201913140RA SG 10201913140R A SG10201913140R A SG 10201913140RA SG 10201913140R A SG10201913140R A SG 10201913140RA
- Authority
- SG
- Singapore
- Prior art keywords
- forming
- same
- semiconductor package
- package
- semiconductor
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Error Detection And Correction (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG10201602169T | 2016-03-21 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201913140RA true SG10201913140RA (en) | 2020-03-30 |
Family
ID=59900716
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201913140RA SG10201913140RA (en) | 2016-03-21 | 2017-03-17 | Semiconductor package and method of forming the same |
SG11201807803SA SG11201807803SA (en) | 2016-03-21 | 2017-03-17 | Semiconductor package and method of forming the same |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201807803SA SG11201807803SA (en) | 2016-03-21 | 2017-03-17 | Semiconductor package and method of forming the same |
Country Status (3)
Country | Link |
---|---|
US (1) | US11018080B2 (en) |
SG (2) | SG10201913140RA (en) |
WO (1) | WO2017164810A1 (en) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10535622B2 (en) * | 2017-12-07 | 2020-01-14 | Dyi-chung Hu | Substrate structure and electronic device having coarse redistribution layer electrically connected to fine redistribution layer |
KR102491103B1 (en) | 2018-02-06 | 2023-01-20 | 삼성전자주식회사 | Semiconductor package and method of fabricating the same |
US11276676B2 (en) * | 2018-05-15 | 2022-03-15 | Invensas Bonding Technologies, Inc. | Stacked devices and methods of fabrication |
US11456268B2 (en) * | 2019-01-21 | 2022-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and manufacturing method thereof |
US11769735B2 (en) | 2019-02-12 | 2023-09-26 | Intel Corporation | Chiplet first architecture for die tiling applications |
US11296053B2 (en) | 2019-06-26 | 2022-04-05 | Invensas Bonding Technologies, Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
US11600567B2 (en) * | 2019-07-31 | 2023-03-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method for manufacturing the same |
US11784091B2 (en) * | 2019-08-30 | 2023-10-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of chip package with fan-out feature |
US11587905B2 (en) * | 2019-10-09 | 2023-02-21 | Industrial Technology Research Institute | Multi-chip package and manufacturing method thereof |
US11164817B2 (en) | 2019-11-01 | 2021-11-02 | International Business Machines Corporation | Multi-chip package structures with discrete redistribution layers |
US11094637B2 (en) | 2019-11-06 | 2021-08-17 | International Business Machines Corporation | Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers |
US11114410B2 (en) * | 2019-11-27 | 2021-09-07 | International Business Machines Corporation | Multi-chip package structures formed by joining chips to pre-positioned chip interconnect bridge devices |
US11616026B2 (en) * | 2020-01-17 | 2023-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
US11289453B2 (en) | 2020-02-27 | 2022-03-29 | Qualcomm Incorporated | Package comprising a substrate and a high-density interconnect structure coupled to the substrate |
JP2021150311A (en) * | 2020-03-16 | 2021-09-27 | キオクシア株式会社 | Semiconductor device |
US20210296241A1 (en) * | 2020-03-20 | 2021-09-23 | Intel Corporation | Microelectronic package with reduced through-substrate routing |
US11605594B2 (en) | 2020-03-23 | 2023-03-14 | Qualcomm Incorporated | Package comprising a substrate and a high-density interconnect integrated device coupled to the substrate |
US11942386B2 (en) * | 2020-08-24 | 2024-03-26 | Texas Instruments Incorporated | Electronic devices in semiconductor package cavities |
CN114388471A (en) * | 2020-10-06 | 2022-04-22 | 欣兴电子股份有限公司 | Packaging structure and manufacturing method thereof |
TWI730917B (en) * | 2020-10-27 | 2021-06-11 | 矽品精密工業股份有限公司 | Electronic package and manufacturing method thereof |
TWI762309B (en) * | 2021-01-21 | 2022-04-21 | 欣興電子股份有限公司 | Circuit board structure and spliced circuit board |
US20220256722A1 (en) * | 2021-02-05 | 2022-08-11 | Advanced Semiconductor Engineering, Inc. | Electronic device package and method of manufacturing the same |
US20230245999A1 (en) * | 2022-01-31 | 2023-08-03 | Intel Corporation | Forwarded supply voltage for dynamic voltage and frequency scaling with stacked chip packaging architecture |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4581768B2 (en) * | 2005-03-16 | 2010-11-17 | ソニー株式会社 | Manufacturing method of semiconductor device |
US8064224B2 (en) | 2008-03-31 | 2011-11-22 | Intel Corporation | Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same |
US8227904B2 (en) | 2009-06-24 | 2012-07-24 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
US8039304B2 (en) * | 2009-08-12 | 2011-10-18 | Stats Chippac, Ltd. | Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structures |
US8866301B2 (en) * | 2010-05-18 | 2014-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers with interconnection structures |
KR101332916B1 (en) * | 2011-12-29 | 2013-11-26 | 주식회사 네패스 | Semiconductor package and method of manufacturing the same |
US8716859B2 (en) | 2012-01-10 | 2014-05-06 | Intel Mobile Communications GmbH | Enhanced flip chip package |
US9391041B2 (en) * | 2012-10-19 | 2016-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out wafer level package structure |
US8946900B2 (en) | 2012-10-31 | 2015-02-03 | Intel Corporation | X-line routing for dense multi-chip-package interconnects |
US9478474B2 (en) * | 2012-12-28 | 2016-10-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for forming package-on-packages |
US8901748B2 (en) | 2013-03-14 | 2014-12-02 | Intel Corporation | Direct external interconnect for embedded interconnect bridge package |
US9209154B2 (en) * | 2013-12-04 | 2015-12-08 | Bridge Semiconductor Corporation | Semiconductor package with package-on-package stacking capability and method of manufacturing the same |
US20150206866A1 (en) * | 2014-01-17 | 2015-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Package and Methods of Forming Same |
US9601463B2 (en) * | 2014-04-17 | 2017-03-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out stacked system in package (SIP) and the methods of making the same |
US9768145B2 (en) * | 2015-08-31 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming multi-die package structures including redistribution layers |
-
2017
- 2017-03-17 WO PCT/SG2017/050133 patent/WO2017164810A1/en active Application Filing
- 2017-03-17 SG SG10201913140RA patent/SG10201913140RA/en unknown
- 2017-03-17 US US16/087,621 patent/US11018080B2/en active Active
- 2017-03-17 SG SG11201807803SA patent/SG11201807803SA/en unknown
Also Published As
Publication number | Publication date |
---|---|
US11018080B2 (en) | 2021-05-25 |
SG11201807803SA (en) | 2018-10-30 |
WO2017164810A1 (en) | 2017-09-28 |
US20190043792A1 (en) | 2019-02-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
SG10201913388VA (en) | Semiconductor package and method of forming the same | |
SG10201913140RA (en) | Semiconductor package and method of forming the same | |
TWI563546B (en) | Semiconductor device and methods of forming the same | |
SG11202001724TA (en) | Photonic integrated circuit package and method of forming the same | |
EP3345215A4 (en) | Semiconductor apparatus and method of manufacturing the same | |
SG10201907920TA (en) | Semiconductor Package And Method Of Manufacturing The Same | |
TWI562323B (en) | Semiconductor device package and method of manufacturing the same | |
SG10201907737SA (en) | Semiconductor package and method of fabricating the same | |
SG10201707563VA (en) | Method of manufacturing semiconductor package | |
EP3204966A4 (en) | Semiconductor device and method of manufacturing the same | |
SG10201608814YA (en) | Semiconductor device and method for manufacturing the semiconductor device | |
SG10201505824YA (en) | Semiconductor device and method of manufacturing the same | |
HK1245999A1 (en) | Semiconductor device and method of manufacturing semiconductor device | |
TWI560822B (en) | Wafer level package and fabrication method thereof | |
TWI560828B (en) | Chip package and method for forming the same | |
TWI800792B (en) | Method for fabricating semiconductor package and semiconductor package using the same | |
HK1252326A1 (en) | Semiconductor device and manufacturing method of the same | |
TWI563624B (en) | Semiconductor device structure and method of fabricating the same | |
SG10201700762PA (en) | Semiconductor package and method of manufacturing semiconductor package | |
KR101748949B9 (en) | semiconductor memory device and method of fabricating the same | |
SG11202103709VA (en) | Semiconductor structure and method of forming the same | |
SG11202100905XA (en) | Semiconductor package and method of forming the same | |
HK1251718A1 (en) | Semiconductor device and manufacturing method thereof | |
TWI563665B (en) | Semiconductor device and method of manufacturing the same | |
TWI560827B (en) | Semiconductor package and its carrier structure and method of manufacture |