SG10201913140RA - Semiconductor package and method of forming the same - Google Patents

Semiconductor package and method of forming the same

Info

Publication number
SG10201913140RA
SG10201913140RA SG10201913140RA SG10201913140RA SG10201913140RA SG 10201913140R A SG10201913140R A SG 10201913140RA SG 10201913140R A SG10201913140R A SG 10201913140RA SG 10201913140R A SG10201913140R A SG 10201913140RA SG 10201913140R A SG10201913140R A SG 10201913140RA
Authority
SG
Singapore
Prior art keywords
forming
same
semiconductor package
package
semiconductor
Prior art date
Application number
SG10201913140RA
Inventor
Roshan Weerasekera
Surya Bhattacharya
Ka Fai Chang
Vempati Srinivasa Rao
Original Assignee
Agency Science Tech & Res
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency Science Tech & Res filed Critical Agency Science Tech & Res
Publication of SG10201913140RA publication Critical patent/SG10201913140RA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Error Detection And Correction (AREA)
SG10201913140RA 2016-03-21 2017-03-17 Semiconductor package and method of forming the same SG10201913140RA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SG10201602169T 2016-03-21

Publications (1)

Publication Number Publication Date
SG10201913140RA true SG10201913140RA (en) 2020-03-30

Family

ID=59900716

Family Applications (2)

Application Number Title Priority Date Filing Date
SG10201913140RA SG10201913140RA (en) 2016-03-21 2017-03-17 Semiconductor package and method of forming the same
SG11201807803SA SG11201807803SA (en) 2016-03-21 2017-03-17 Semiconductor package and method of forming the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
SG11201807803SA SG11201807803SA (en) 2016-03-21 2017-03-17 Semiconductor package and method of forming the same

Country Status (3)

Country Link
US (1) US11018080B2 (en)
SG (2) SG10201913140RA (en)
WO (1) WO2017164810A1 (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10535622B2 (en) * 2017-12-07 2020-01-14 Dyi-chung Hu Substrate structure and electronic device having coarse redistribution layer electrically connected to fine redistribution layer
KR102491103B1 (en) 2018-02-06 2023-01-20 삼성전자주식회사 Semiconductor package and method of fabricating the same
US11276676B2 (en) * 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US11456268B2 (en) * 2019-01-21 2022-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US11769735B2 (en) 2019-02-12 2023-09-26 Intel Corporation Chiplet first architecture for die tiling applications
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11600567B2 (en) * 2019-07-31 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same
US11784091B2 (en) * 2019-08-30 2023-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out feature
US11587905B2 (en) * 2019-10-09 2023-02-21 Industrial Technology Research Institute Multi-chip package and manufacturing method thereof
US11164817B2 (en) 2019-11-01 2021-11-02 International Business Machines Corporation Multi-chip package structures with discrete redistribution layers
US11094637B2 (en) 2019-11-06 2021-08-17 International Business Machines Corporation Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers
US11114410B2 (en) * 2019-11-27 2021-09-07 International Business Machines Corporation Multi-chip package structures formed by joining chips to pre-positioned chip interconnect bridge devices
US11616026B2 (en) * 2020-01-17 2023-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11289453B2 (en) 2020-02-27 2022-03-29 Qualcomm Incorporated Package comprising a substrate and a high-density interconnect structure coupled to the substrate
JP2021150311A (en) * 2020-03-16 2021-09-27 キオクシア株式会社 Semiconductor device
US20210296241A1 (en) * 2020-03-20 2021-09-23 Intel Corporation Microelectronic package with reduced through-substrate routing
US11605594B2 (en) 2020-03-23 2023-03-14 Qualcomm Incorporated Package comprising a substrate and a high-density interconnect integrated device coupled to the substrate
US11942386B2 (en) * 2020-08-24 2024-03-26 Texas Instruments Incorporated Electronic devices in semiconductor package cavities
CN114388471A (en) * 2020-10-06 2022-04-22 欣兴电子股份有限公司 Packaging structure and manufacturing method thereof
TWI730917B (en) * 2020-10-27 2021-06-11 矽品精密工業股份有限公司 Electronic package and manufacturing method thereof
TWI762309B (en) * 2021-01-21 2022-04-21 欣興電子股份有限公司 Circuit board structure and spliced circuit board
US20220256722A1 (en) * 2021-02-05 2022-08-11 Advanced Semiconductor Engineering, Inc. Electronic device package and method of manufacturing the same
US20230245999A1 (en) * 2022-01-31 2023-08-03 Intel Corporation Forwarded supply voltage for dynamic voltage and frequency scaling with stacked chip packaging architecture

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4581768B2 (en) * 2005-03-16 2010-11-17 ソニー株式会社 Manufacturing method of semiconductor device
US8064224B2 (en) 2008-03-31 2011-11-22 Intel Corporation Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same
US8227904B2 (en) 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US8039304B2 (en) * 2009-08-12 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structures
US8866301B2 (en) * 2010-05-18 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers with interconnection structures
KR101332916B1 (en) * 2011-12-29 2013-11-26 주식회사 네패스 Semiconductor package and method of manufacturing the same
US8716859B2 (en) 2012-01-10 2014-05-06 Intel Mobile Communications GmbH Enhanced flip chip package
US9391041B2 (en) * 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US8946900B2 (en) 2012-10-31 2015-02-03 Intel Corporation X-line routing for dense multi-chip-package interconnects
US9478474B2 (en) * 2012-12-28 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for forming package-on-packages
US8901748B2 (en) 2013-03-14 2014-12-02 Intel Corporation Direct external interconnect for embedded interconnect bridge package
US9209154B2 (en) * 2013-12-04 2015-12-08 Bridge Semiconductor Corporation Semiconductor package with package-on-package stacking capability and method of manufacturing the same
US20150206866A1 (en) * 2014-01-17 2015-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Package and Methods of Forming Same
US9601463B2 (en) * 2014-04-17 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) and the methods of making the same
US9768145B2 (en) * 2015-08-31 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming multi-die package structures including redistribution layers

Also Published As

Publication number Publication date
US11018080B2 (en) 2021-05-25
SG11201807803SA (en) 2018-10-30
WO2017164810A1 (en) 2017-09-28
US20190043792A1 (en) 2019-02-07

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