SG11202001177SA - Bottom-up approach to high aspect ratio hole formation in 3d memory structures - Google Patents
Bottom-up approach to high aspect ratio hole formation in 3d memory structuresInfo
- Publication number
- SG11202001177SA SG11202001177SA SG11202001177SA SG11202001177SA SG11202001177SA SG 11202001177S A SG11202001177S A SG 11202001177SA SG 11202001177S A SG11202001177S A SG 11202001177SA SG 11202001177S A SG11202001177S A SG 11202001177SA SG 11202001177S A SG11202001177S A SG 11202001177SA
- Authority
- SG
- Singapore
- Prior art keywords
- approach
- aspect ratio
- high aspect
- hole formation
- memory structures
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201762554528P | 2017-09-05 | 2017-09-05 | |
PCT/US2018/048342 WO2019050714A1 (en) | 2017-09-05 | 2018-08-28 | Bottom-up approach to high aspect ratio hole formation in 3d memory structures |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11202001177SA true SG11202001177SA (en) | 2020-03-30 |
Family
ID=65634276
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11202001177SA SG11202001177SA (en) | 2017-09-05 | 2018-08-28 | Bottom-up approach to high aspect ratio hole formation in 3d memory structures |
Country Status (7)
Country | Link |
---|---|
US (1) | US11315943B2 (en) |
JP (1) | JP7194725B2 (en) |
KR (1) | KR102227347B1 (en) |
CN (1) | CN111133579B (en) |
SG (1) | SG11202001177SA (en) |
TW (1) | TWI724323B (en) |
WO (1) | WO2019050714A1 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI778118B (en) * | 2017-09-05 | 2022-09-21 | 美商應用材料股份有限公司 | Self-aligned structures from sub-oxides |
KR102476262B1 (en) | 2017-12-14 | 2022-12-08 | 어플라이드 머티어리얼스, 인코포레이티드 | Methods to Etch Metal Oxides with Less Etch Residue |
US11170992B2 (en) * | 2018-04-27 | 2021-11-09 | Tokyo Electron Limited | Area selective deposition for cap layer formation in advanced contacts |
US11121143B2 (en) * | 2019-05-24 | 2021-09-14 | Micron Technology, Inc. | Integrated assemblies having conductive posts extending through stacks of alternating materials |
TW202115827A (en) * | 2019-09-26 | 2021-04-16 | 美商應用材料股份有限公司 | Selective and self-limiting tungsten etch process |
KR20220074927A (en) * | 2019-10-31 | 2022-06-03 | 칼 짜이스 에스엠테 게엠베하 | FIB-SEM 3D Tomography to Measure Shape Deviation of Solid Aspect Ratio Structures |
Family Cites Families (29)
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US6576113B1 (en) | 1999-10-29 | 2003-06-10 | California Institute Of Technology | Method of electroplating of high aspect ratio metal structures into semiconductors |
JP4315424B2 (en) | 2003-08-29 | 2009-08-19 | キヤノン株式会社 | Method for producing nanostructure |
US8158532B2 (en) * | 2003-10-20 | 2012-04-17 | Novellus Systems, Inc. | Topography reduction and control by selective accelerator removal |
TWI274403B (en) | 2005-08-12 | 2007-02-21 | Powerchip Semiconductor Corp | Non-volatile memory and fabrication method thereof |
US7368394B2 (en) | 2006-02-27 | 2008-05-06 | Applied Materials, Inc. | Etch methods to form anisotropic features for high aspect ratio applications |
JP2008283045A (en) | 2007-05-11 | 2008-11-20 | Toshiba Corp | Method of manufacturing semiconductor device, and the semiconductor device |
JP2008305921A (en) * | 2007-06-06 | 2008-12-18 | Panasonic Corp | Semiconductor device and manufacturing method therefor |
WO2008153674A1 (en) * | 2007-06-09 | 2008-12-18 | Boris Kobrin | Method and apparatus for anisotropic etching |
US7884012B2 (en) * | 2007-09-28 | 2011-02-08 | Tokyo Electron Limited | Void-free copper filling of recessed features for semiconductor devices |
US20100330805A1 (en) | 2007-11-02 | 2010-12-30 | Kenny Linh Doan | Methods for forming high aspect ratio features on a substrate |
JP2010205904A (en) | 2009-03-03 | 2010-09-16 | Toshiba Corp | Method for manufacturing nonvolatile semiconductor memory device, and nonvolatile semiconductor memory device |
US8575753B2 (en) | 2009-05-27 | 2013-11-05 | Samsung Electronics Co., Ltd. | Semiconductor device having a conductive structure including oxide and non oxide portions |
US8076241B2 (en) * | 2009-09-30 | 2011-12-13 | Tokyo Electron Limited | Methods for multi-step copper plating on a continuous ruthenium film in recessed features |
JP5775288B2 (en) | 2009-11-17 | 2015-09-09 | 三星電子株式会社Samsung Electronics Co.,Ltd. | Semiconductor device |
US8846451B2 (en) * | 2010-07-30 | 2014-09-30 | Applied Materials, Inc. | Methods for depositing metal in high aspect ratio features |
CN103249873B (en) | 2010-10-21 | 2016-03-30 | 惠普发展公司,有限责任合伙企业 | Form the method for nanostructure |
US8450710B2 (en) * | 2011-05-27 | 2013-05-28 | Crossbar, Inc. | Low temperature p+ silicon junction material for a non-volatile memory device |
EP2939261B1 (en) * | 2012-12-31 | 2016-08-24 | FEI Company | Depositing material into high aspect ratio structures |
TWI660429B (en) * | 2013-09-27 | 2019-05-21 | 美商應用材料股份有限公司 | Method of enabling seamless cobalt gap-fill |
GB201320387D0 (en) * | 2013-11-19 | 2014-01-01 | Almirante Cacua Agricola Com Rcio E Exporta O Ltda | Plant production |
US9449821B2 (en) | 2014-07-17 | 2016-09-20 | Macronix International Co., Ltd. | Composite hard mask etching profile for preventing pattern collapse in high-aspect-ratio trenches |
TWI670831B (en) * | 2014-09-03 | 2019-09-01 | 美商應用材料股份有限公司 | Nanocrystalline diamond carbon film for 3d nand hardmask application |
US9184060B1 (en) | 2014-11-14 | 2015-11-10 | Lam Research Corporation | Plated metal hard mask for vertical NAND hole etch |
US9620377B2 (en) * | 2014-12-04 | 2017-04-11 | Lab Research Corporation | Technique to deposit metal-containing sidewall passivation for high aspect ratio cylinder etch |
US9543148B1 (en) * | 2015-09-01 | 2017-01-10 | Lam Research Corporation | Mask shrink layer for high aspect ratio dielectric etch |
US10121858B2 (en) | 2015-10-30 | 2018-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Elongated semiconductor structure planarization |
JP2019530242A (en) | 2016-09-30 | 2019-10-17 | アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated | Method for forming self-aligned vias |
TWI719262B (en) | 2016-11-03 | 2021-02-21 | 美商應用材料股份有限公司 | Deposition and treatment of films for patterning |
KR20190067939A (en) * | 2016-11-08 | 2019-06-17 | 어플라이드 머티어리얼스, 인코포레이티드 | Geometry control of bottom-up fillers for patterning applications |
-
2018
- 2018-08-28 CN CN201880057320.7A patent/CN111133579B/en active Active
- 2018-08-28 WO PCT/US2018/048342 patent/WO2019050714A1/en active Application Filing
- 2018-08-28 SG SG11202001177SA patent/SG11202001177SA/en unknown
- 2018-08-28 JP JP2020512673A patent/JP7194725B2/en active Active
- 2018-08-28 KR KR1020207008942A patent/KR102227347B1/en active IP Right Grant
- 2018-08-28 US US16/643,965 patent/US11315943B2/en active Active
- 2018-09-03 TW TW107130784A patent/TWI724323B/en active
Also Published As
Publication number | Publication date |
---|---|
JP2020532870A (en) | 2020-11-12 |
JP7194725B2 (en) | 2022-12-22 |
CN111133579B (en) | 2023-09-01 |
KR102227347B1 (en) | 2021-03-11 |
WO2019050714A1 (en) | 2019-03-14 |
TWI724323B (en) | 2021-04-11 |
CN111133579A (en) | 2020-05-08 |
TW201921643A (en) | 2019-06-01 |
KR20200035500A (en) | 2020-04-03 |
US20210050365A1 (en) | 2021-02-18 |
US11315943B2 (en) | 2022-04-26 |
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