SG11201900829YA - Method for manufacturing a semiconductor structure - Google Patents

Method for manufacturing a semiconductor structure

Info

Publication number
SG11201900829YA
SG11201900829YA SG11201900829YA SG11201900829YA SG11201900829YA SG 11201900829Y A SG11201900829Y A SG 11201900829YA SG 11201900829Y A SG11201900829Y A SG 11201900829YA SG 11201900829Y A SG11201900829Y A SG 11201900829YA SG 11201900829Y A SG11201900829Y A SG 11201900829YA
Authority
SG
Singapore
Prior art keywords
layer
silicon nitride
international
patterned layer
nitride patterned
Prior art date
Application number
SG11201900829YA
Other languages
English (en)
Inventor
Bich-Yen Nguyen
Gweltaz Gaudin
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11201900829YA publication Critical patent/SG11201900829YA/en

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13Integrated optical circuits characterised by the manufacturing method
    • G02B6/132Integrated optical circuits characterised by the manufacturing method by deposition of thin films
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13Integrated optical circuits characterised by the manufacturing method
    • G02B6/136Integrated optical circuits characterised by the manufacturing method by etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816Aspects relating to the layout of the pattern or to the size of vias or trenches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Optical Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Lasers (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Semiconductor Memories (AREA)
SG11201900829YA 2016-08-04 2017-07-27 Method for manufacturing a semiconductor structure SG11201900829YA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1657575A FR3054927B1 (fr) 2016-08-04 2016-08-04 Procede de fabrication d'une structure de semi-conducteur
PCT/EP2017/068979 WO2018024595A1 (en) 2016-08-04 2017-07-27 Method for manufacturing a semiconductor structure

Publications (1)

Publication Number Publication Date
SG11201900829YA true SG11201900829YA (en) 2019-02-27

Family

ID=57539362

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201900829YA SG11201900829YA (en) 2016-08-04 2017-07-27 Method for manufacturing a semiconductor structure

Country Status (9)

Country Link
US (1) US11156778B2 (ko)
EP (1) EP3494425B1 (ko)
JP (1) JP6759520B2 (ko)
KR (1) KR102152705B1 (ko)
CN (1) CN109716185B (ko)
FR (1) FR3054927B1 (ko)
SG (1) SG11201900829YA (ko)
TW (1) TWI775763B (ko)
WO (1) WO2018024595A1 (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3054927B1 (fr) 2016-08-04 2018-07-13 Soitec Procede de fabrication d'une structure de semi-conducteur
KR20210006538A (ko) 2019-07-08 2021-01-19 삼성전자주식회사 반도체 발광소자 제조방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5968239A (en) * 1996-11-12 1999-10-19 Kabushiki Kaisha Toshiba Polishing slurry
US6057210A (en) * 1998-04-21 2000-05-02 Vanguard International Semiconductor Corporation Method of making a shallow trench isolation for ULSI formation via in-direct CMP process
US6048775A (en) * 1999-05-24 2000-04-11 Vanguard International Semiconductor Corporation Method to make shallow trench isolation structure by HDP-CVD and chemical mechanical polish processes
TW429514B (en) * 1999-10-06 2001-04-11 Mosel Vitelic Inc Planarization method for polysilicon layer deposited on the trench
US6500729B1 (en) 2000-06-02 2002-12-31 Agere Systems Guardian Corp. Method for reducing dishing related issues during the formation of shallow trench isolation structures
US6645867B2 (en) 2001-05-24 2003-11-11 International Business Machines Corporation Structure and method to preserve STI during etching
US8008205B2 (en) 2006-03-08 2011-08-30 Sharp Kabushiki Kaisha Methods for producing a semiconductor device having planarization films
US7364975B2 (en) * 2006-07-20 2008-04-29 Infineon Technologies Ag Semiconductor device fabrication methods
FR2906078B1 (fr) 2006-09-19 2009-02-13 Commissariat Energie Atomique Procede de fabrication d'une structure micro-technologique mixte et une structure ainsi obtenue
WO2009051903A1 (en) * 2007-10-18 2009-04-23 Bae Systems Information And Electronic Systems Integration Inc. Method for manufacturing multiple layers of waveguides
EP2648025A1 (en) * 2012-04-02 2013-10-09 Caliopa NV A process for manufacturing a photonic circuit
EP2685297B1 (en) * 2012-07-13 2017-12-06 Huawei Technologies Co., Ltd. A process for manufacturing a photonic circuit with active and passive structures
FR3054927B1 (fr) 2016-08-04 2018-07-13 Soitec Procede de fabrication d'une structure de semi-conducteur

Also Published As

Publication number Publication date
JP2019528566A (ja) 2019-10-10
EP3494425A1 (en) 2019-06-12
JP6759520B2 (ja) 2020-09-23
EP3494425B1 (en) 2022-02-16
CN109716185B (zh) 2023-03-31
WO2018024595A1 (en) 2018-02-08
TWI775763B (zh) 2022-09-01
KR102152705B1 (ko) 2020-09-07
US11156778B2 (en) 2021-10-26
FR3054927A1 (ko) 2018-02-09
FR3054927B1 (fr) 2018-07-13
CN109716185A (zh) 2019-05-03
TW201816443A (zh) 2018-05-01
KR20190028532A (ko) 2019-03-18
US20190187376A1 (en) 2019-06-20

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