SG11201900403PA - Circuits and methods providing mutual capacitance in vertical electrical connections - Google Patents

Circuits and methods providing mutual capacitance in vertical electrical connections

Info

Publication number
SG11201900403PA
SG11201900403PA SG11201900403PA SG11201900403PA SG11201900403PA SG 11201900403P A SG11201900403P A SG 11201900403PA SG 11201900403P A SG11201900403P A SG 11201900403PA SG 11201900403P A SG11201900403P A SG 11201900403PA SG 11201900403P A SG11201900403P A SG 11201900403PA
Authority
SG
Singapore
Prior art keywords
international
vertical electrical
electrical connections
san diego
vertical
Prior art date
Application number
SG11201900403PA
Inventor
Priyatharshan Pathmanathan
Devarshi Patel
Dennis Allen Northgrave
Kyle Roberts
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of SG11201900403PA publication Critical patent/SG11201900403PA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0228—Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09636—Details of adjacent, not connected vias

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Details Of Connecting Devices For Male And Female Coupling (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrotherapy Devices (AREA)
  • Geometry (AREA)

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 08 March 2018 (08.03.2018) WIPO I PCT (10) International Publication Number WO 2018/044514 A1 (51) International Patent Classification: H05K1/02 (2006.01) H01L 23/498 (2006.01) H0SK1/11 (2006.01) H05K1/16 (2006.01) (21) International Application Number: (22) International Filing Date: (25) Filing Language: (26) Publication Language: PCT/US2017/045888 08 August 2017 (08.08.2017) English English (30) Priority Data: 15/255,412 02 September 2016 (02.09.2016) US (71) Applicant: QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration, 5775 Morehouse Drive, San Diego, California 92121-1714 (US). (72) Inventors: PATHMANATHAN, Priyatharshan; 5775 Morehouse Drive, San Diego, California 92121 (US). PA- TEL, Devarshi; 5775 Morehouse Drive, San Diego, Cali­ fornia 92121 (US). NORTHGRAVE, Dennis Allen; 5775 Morehouse Drive, San Diego, California 92121 (US). ROBERTS, Kyle; 5775 Morehouse Drive, San Diego, Cal­ ifornia 92121-1714 (US). (74) Agent: KELTON, Thomas W. et al.; HAYNES AND BOONE, LLP, 2323 Victory Avenue, Suite 700, Dallas, Texas 75219 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available)'. AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available)'. ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). (54) Title: CIRCUITS AND METHODS PROVIDING MUTUAL CAPACITANCE IN VERTICAL ELECTRICAL CONNECTIONS 100 •t i-H •t •t © 00 i-H o CJ O £ FIG 1 (57) : An electrical device including a structure having a plural­ ity of dielectric layers, the structure further having a plurality of vertical electrical connections extending from a top layer of the dielectric layers to a bottom layer of the dielectric layers, a first vertical electrical connection of the plurality of vertical electrical connections including a first capacitive structure that extends in a plane perpendicular to a vertical dimension of the vertical electrical connection, wherein the first capacitive structure is dis­ posed on a first dielectric layer of the plurality of dielectric layers, wherein the first dielectric layer is below the top layer, and a second vertical electri­ cal connection of the plurality of vertical electrical connections including a second capacitive structure extending in the plane and disposed on the first dielectric layer. [Continued on next page] WO 2018/044514 A1 llll II II11 III III II II llllI I Hill II III Declarations under Rule 4.17: — as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(H)) — as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(Hi)) Published: — with international search report (Art. 21(3))
SG11201900403PA 2016-09-02 2017-08-08 Circuits and methods providing mutual capacitance in vertical electrical connections SG11201900403PA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/255,412 US9722012B1 (en) 2016-09-02 2016-09-02 Circuits and methods providing mutual capacitance in vertical electrical connections
PCT/US2017/045888 WO2018044514A1 (en) 2016-09-02 2017-08-08 Circuits and methods providing mutual capacitance in vertical electrical connections

Publications (1)

Publication Number Publication Date
SG11201900403PA true SG11201900403PA (en) 2019-03-28

Family

ID=59382664

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201900403PA SG11201900403PA (en) 2016-09-02 2017-08-08 Circuits and methods providing mutual capacitance in vertical electrical connections

Country Status (8)

Country Link
US (1) US9722012B1 (en)
EP (1) EP3508039A1 (en)
KR (1) KR102000779B1 (en)
CN (1) CN109691241B (en)
AU (1) AU2017321176B2 (en)
SG (1) SG11201900403PA (en)
TW (1) TWI630608B (en)
WO (1) WO2018044514A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10149377B2 (en) 2016-06-24 2018-12-04 Invensas Corporation Stacked transmission line
US11862547B2 (en) * 2020-02-28 2024-01-02 Intel Corporation Differential crosstalk self-cancelation in stackable structures
TWI756860B (en) * 2020-10-08 2022-03-01 緯創資通股份有限公司 Channel structure for signal transmission
CN115003008B (en) * 2022-05-25 2023-10-20 长鑫存储技术有限公司 Conductor structure, semiconductor packaging structure and circuit board for improving far-end crosstalk
CN117787197A (en) * 2022-09-22 2024-03-29 长鑫存储技术有限公司 Circuit structure, forming method thereof and memory

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6316801B1 (en) * 1998-03-04 2001-11-13 Nec Corporation Semiconductor device having capacitive element structure and multilevel interconnection structure and method of fabricating the same
US6819543B2 (en) * 2002-12-31 2004-11-16 Intel Corporation Multilayer capacitor with multiple plates per layer
US7154047B2 (en) * 2004-02-27 2006-12-26 Texas Instruments Incorporated Via structure of packages for high frequency semiconductor devices
CN101484976B (en) * 2006-05-02 2011-02-23 Nxp股份有限公司 Electric device comprising an improved electrode and its manufacture method
TWI325512B (en) * 2006-08-01 2010-06-01 Au Optronics Corp Liquid crystal display panel and method for making liquid crystal display panel
KR100791339B1 (en) * 2006-08-25 2008-01-03 삼성전자주식회사 An embeded semiconductor device including planarization resistant patterns and method for fabricating the same
US9240621B2 (en) 2009-06-24 2016-01-19 Intel Corporation Micro-strip crosstalk compensation using stubs
JP5724531B2 (en) * 2010-04-12 2015-05-27 セイコーエプソン株式会社 Electro-optical device and electronic apparatus
TWI438882B (en) * 2011-11-01 2014-05-21 Unimicron Technology Corp Package substrate having embedded capacitors and fabrication method thereof
US9331137B1 (en) * 2012-03-27 2016-05-03 Altera Corporation Metal-insulator-metal capacitors between metal interconnect layers
JP5904856B2 (en) * 2012-04-23 2016-04-20 キヤノン株式会社 Printed wiring board, semiconductor package and printed circuit board
US20140177150A1 (en) 2012-12-21 2014-06-26 Olufemi B. Oluwafemi Crosstalk cancelation in striplines
US9105635B2 (en) 2013-03-13 2015-08-11 Intel Corporation Stubby pads for channel cross-talk reduction
US10103054B2 (en) 2013-03-13 2018-10-16 Intel Corporation Coupled vias for channel cross-talk reduction
US20150085458A1 (en) 2013-09-26 2015-03-26 Raul Enriquez Shibayama Reducing Far End Crosstalk in Single Ended Interconnects and Buses
US9893761B2 (en) 2014-09-25 2018-02-13 Intel Corporation Signal routing with reduced crosstalk

Also Published As

Publication number Publication date
KR102000779B1 (en) 2019-07-17
CN109691241B (en) 2022-09-30
EP3508039A1 (en) 2019-07-10
TW201812761A (en) 2018-04-01
CN109691241A (en) 2019-04-26
AU2017321176B2 (en) 2019-12-12
AU2017321176A1 (en) 2019-02-07
KR20190028551A (en) 2019-03-18
WO2018044514A1 (en) 2018-03-08
US9722012B1 (en) 2017-08-01
TWI630608B (en) 2018-07-21
BR112019003457A2 (en) 2019-05-21

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