SG10202007838PA - Packaged device with a chiplet comprising memory resources - Google Patents
Packaged device with a chiplet comprising memory resourcesInfo
- Publication number
- SG10202007838PA SG10202007838PA SG10202007838PA SG10202007838PA SG10202007838PA SG 10202007838P A SG10202007838P A SG 10202007838PA SG 10202007838P A SG10202007838P A SG 10202007838PA SG 10202007838P A SG10202007838P A SG 10202007838PA SG 10202007838P A SG10202007838P A SG 10202007838PA
- Authority
- SG
- Singapore
- Prior art keywords
- chiplet
- memory resources
- packaged device
- packaged
- resources
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17306—Intercommunication techniques
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0756—Stacked arrangements of devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Software Systems (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Semiconductor Memories (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/586,167 US10998302B2 (en) | 2019-09-27 | 2019-09-27 | Packaged device with a chiplet comprising memory resources |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10202007838PA true SG10202007838PA (en) | 2021-04-29 |
Family
ID=74873193
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10202007838PA SG10202007838PA (en) | 2019-09-27 | 2020-08-17 | Packaged device with a chiplet comprising memory resources |
Country Status (6)
Country | Link |
---|---|
US (1) | US10998302B2 (en) |
JP (1) | JP2021057570A (en) |
KR (1) | KR20210037531A (en) |
CN (1) | CN112582390A (en) |
DE (1) | DE102020121319A1 (en) |
SG (1) | SG10202007838PA (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20230413586A1 (en) * | 2020-01-20 | 2023-12-21 | Monolithic 3D Inc. | 3d semiconductor devices and structures with electronic circuit units |
US20230095914A1 (en) * | 2021-09-24 | 2023-03-30 | Intel Corporation | Test and debug support with hbi chiplet architecture |
CN115617739B (en) * | 2022-09-27 | 2024-02-23 | 南京信息工程大学 | Chip based on Chiplet architecture and control method |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5593053B2 (en) * | 2009-10-09 | 2014-09-17 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor device |
US20110175218A1 (en) * | 2010-01-18 | 2011-07-21 | Shiann-Ming Liou | Package assembly having a semiconductor substrate |
KR20150066555A (en) * | 2012-10-15 | 2015-06-16 | 피에스4 뤽스코 에스.에이.알.엘. | Semiconductor device |
KR101401708B1 (en) * | 2012-11-15 | 2014-05-30 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device and manufacturing method thereof |
US9324698B2 (en) * | 2013-08-13 | 2016-04-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-chip structure and method of forming same |
US9368479B2 (en) * | 2014-03-07 | 2016-06-14 | Invensas Corporation | Thermal vias disposed in a substrate proximate to a well thereof |
KR102254104B1 (en) * | 2014-09-29 | 2021-05-20 | 삼성전자주식회사 | Semiconductor package |
US9570399B2 (en) * | 2014-12-23 | 2017-02-14 | Mediatek Inc. | Semiconductor package assembly with through silicon via interconnect |
JP2016174101A (en) * | 2015-03-17 | 2016-09-29 | 株式会社東芝 | Semiconductor device and manufacturing method of the same |
KR102649471B1 (en) * | 2016-09-05 | 2024-03-21 | 삼성전자주식회사 | Semiconductor package and method of fabricating the same |
US10347598B2 (en) * | 2017-05-19 | 2019-07-09 | Samsung Electro-Mechanics Co., Ltd. | Composite antenna substrate and semiconductor package module |
JP2019054181A (en) * | 2017-09-19 | 2019-04-04 | 東芝メモリ株式会社 | Semiconductor package |
US10510650B2 (en) * | 2018-02-02 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias |
US10910344B2 (en) | 2018-06-22 | 2021-02-02 | Xcelsis Corporation | Systems and methods for releveled bump planes for chiplets |
-
2019
- 2019-09-27 US US16/586,167 patent/US10998302B2/en active Active
-
2020
- 2020-06-23 CN CN202010579110.3A patent/CN112582390A/en active Pending
- 2020-06-24 JP JP2020108363A patent/JP2021057570A/en active Pending
- 2020-08-13 DE DE102020121319.0A patent/DE102020121319A1/en active Pending
- 2020-08-17 SG SG10202007838PA patent/SG10202007838PA/en unknown
- 2020-08-27 KR KR1020200108372A patent/KR20210037531A/en unknown
Also Published As
Publication number | Publication date |
---|---|
KR20210037531A (en) | 2021-04-06 |
CN112582390A (en) | 2021-03-30 |
DE102020121319A1 (en) | 2021-04-01 |
US10998302B2 (en) | 2021-05-04 |
US20210098440A1 (en) | 2021-04-01 |
TW202114063A (en) | 2021-04-01 |
JP2021057570A (en) | 2021-04-08 |
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