CN116055928B

CN116055928B - Data sampling method, device, electronic equipment and storage medium

Info

Publication number: CN116055928B
Application number: CN202310341739.8A
Authority: CN
Inventors: 张晋; 吴思远; 敖敏; 邵衍胜; 胡文龙
Original assignee: Shenzhen Pango Microsystems Co Ltd
Current assignee: Shenzhen Pango Microsystems Co Ltd
Priority date: 2023-04-03
Filing date: 2023-04-03
Publication date: 2023-06-02
Anticipated expiration: 2043-04-03
Also published as: CN116055928A

Abstract

The application belongs to the technical field of communication, and discloses a data sampling method, a device, electronic equipment and a storage medium, wherein the method comprises the following steps: configuring clock signals of first to N channels to enable a phase difference between clocks of any two adjacent channels to reach a first phase difference, wherein the first phase difference is not zero; GPON data are respectively input to the first to N channels, and clock signals of the first to N channels are configured as follows: marking a first phase and a second phase of a clock signal as a first sampling point and a second sampling point, sampling GPON data of each channel according to the first sampling point, and sampling the GPON data of each channel according to the second sampling point; and 2N data acquired according to the first sampling point and the second sampling point are output in parallel. The application uses multi-channel parallel double over-sampling, the sampling performance is equivalent to or exceeds that of four times over-sampling, and the required hardware cost is lower.

Description

Data sampling method, device, electronic equipment and storage medium

Technical Field

The present application relates to the field of communications technologies, and in particular, to a data sampling method, a data sampling device, an electronic device, and a storage medium.

Background

In GPON (Gigabit-Capable PON) technology, burst interruption and burst transmission are performed on uplink data sent by an opposite device, so that CDR (clock data recovery ) at a receiving end is required to be able to stably complete phase locking of recovered data within a time specified by a GPON protocol, so as to sample subsequent data.

According to the technical scheme, a sampling phase of GPON uplink transmission data is obtained by using a 4-time oversampling scheme based on a serdes module of an FPGA (Field Programmable Gate Array ), so that phase locking is achieved within a specified time of a GPON protocol.

However, with the pursuit of users for the uplink and downlink data transmission rates on the internet, FTTR (Fiber to The Room, fiber to the far end) technology is also applied by more users, and the GPON technology related to the uplink and downlink data transmission rate is also facing the requirement of upgrading the uplink data transmission rate to 2.488Gbps, but the traditional technical scheme obviously cannot meet the 4-time frequency of 2.488Gbps for the GPON uplink data in a 4-time oversampling mode for the symmetric GPON with both the uplink data rate and the downlink data rate being 2.488Gbps, so that only the 4-time frequency of 2.488Gbps for the GPON uplink data in a 4-time oversampling mode is required to be met, but only the serdes module with higher frequency is selected, and the hardware cost is obviously increased.

Disclosure of Invention

The application aims to provide a data sampling method, a data sampling device, electronic equipment and a storage medium, so as to provide the data sampling method aiming at a GPON uplink 2.488Gbps scene.

In a first aspect, the present application provides a data sampling method, including:

configuring clock signals of first to N channels to enable a phase difference between clocks of any two adjacent channels to reach a first phase difference, wherein the first phase difference is not zero;

GPON data are respectively input to the first to N-th channels, and clock signals of the first to N-th channels are configured as follows:

marking a first phase and a second phase of the clock signal as a first sampling point and a second sampling point, sampling the GPON data of each channel according to the first sampling point, and sampling the GPON data of each channel according to the second sampling point;

2N data acquired by N channels according to the first sampling point and the second sampling point are output in parallel;

wherein configuring clock signals of first to nth channels so that a phase difference between clocks of any two adjacent channels reaches a first phase difference includes:

configuring a first channel to an N channel of serdes as a near-end serial loop, and enabling a transmitting end of the first channel to the N channel to continuously transmit first data to a receiving end, wherein the first data comprises at least one jump edge;

shifting the phase of the clock signals of the first to N-th channels according to the first data, so that the phase difference between clocks of any two adjacent channels is zero;

and moving the phases of clock signals of the second to N-th channels until the phase difference between clocks of any two adjacent channels reaches the first phase difference, and releasing the near-end serial loop back of the first to N-th channel configurations.

In some embodiments, the step of shifting the phase of the clock signals of the first to nth channels according to the first data so that the phase difference between clocks of any two adjacent channels is zero includes:

marking a first bit of the first data, and acquiring the first bit in the first to N-th channels respectively;

and shifting the clock phases of the first to N-th channels until the first bit jumps.

In some embodiments, the data sampling method provided in the present application, the first phase difference is

Degree.

In some embodiments, in the data sampling method provided in the present application, a phase difference between the second phase and the first phase of the clock signal of any one of the first to nth channels is 180 degrees.

In some embodiments, the application provides a data sampling method, where the method includes

Or said->

。

In some embodiments, before the step of configuring the clock phases of the first to nth channels so that the phase difference between the clocks of any two adjacent channels reaches the first phase difference, the method further includes:

initializing clocks of the first to nth channels.

In a second aspect, the present application further provides a data sampling device, including:

the clock alignment module is used for configuring clock signals of the first channel to the N channel so that the phase difference between clocks of any two adjacent channels reaches a first phase difference, and the first phase difference is not zero;

the sampling module is used for respectively inputting GPON data into the first to N channels, and configuring clock signals of the first to N channels as follows:

and the output module is used for outputting 2N data acquired by the N channels according to the first sampling points and the second sampling points in parallel.

In a third aspect, the present application also provides an electronic device comprising a memory and a processor, wherein:

the memory is used for storing a computer program;

the processor is configured to read the computer program in the memory and perform the steps of the data sampling method as provided in the first aspect above.

In a fourth aspect, the present application also provides a computer readable storage medium having stored thereon a readable computer program which when executed by a processor performs the steps of the data sampling method as provided in the first aspect above.

According to the data sampling method, clock signals of the first channel to the N channel are configured, so that the phase difference between clocks of any two adjacent channels reaches a first phase difference; GPON data are respectively input to the first to N channels, and clock signals of the first to N channels are configured as follows: marking a first phase and a second phase of a clock signal as a first sampling point and a second sampling point, sampling GPON data of each channel according to the first sampling point, and sampling the GPON data of each channel according to the second sampling point; and 2N data acquired according to the first sampling point and the second sampling point are output in parallel. According to the data sampling method, sampled data can be sampled at the first sampling point and the second sampling point of each channel and outputted in parallel, phase locking of the recovered data can be completed within the specified time of the GPON protocol, for the transmission rate of GPON uplink data of 2.488Gbps, the phase locking of the recovered data can be completed within the specified time as long as the clock frequency of each channel receiving end meets the twice frequency of 2.488Gbps, 2N sampled data can be obtained in a unit time interval for data recovery, when only two channels are used for sampling, the sampling performance is equivalent to the sampling performance of phase locking within the specified time of the GPON protocol through a 4-time oversampling mode, and when more than two channels are used for sampling, the sampling performance exceeds the sampling performance of phase locking within the specified time of the GPON protocol through the 4-time oversampling mode, the clock frequency required by each channel is lower, hardware with low clock frequency can be selected for sampling, and hardware cost is saved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 shows a flowchart of a data sampling method according to an embodiment of the present application.

Fig. 2 shows a flowchart of configuring clock signals of first to nth channels according to an embodiment of the present application.

Fig. 3 shows a schematic diagram of configuring first to second channel clock alignment provided in an embodiment of the present application.

Fig. 4 shows a schematic diagram of configuring first to second channel phase differences provided in an embodiment of the present application.

Fig. 5 shows a schematic diagram of sampling of the first to second channels according to an embodiment of the present application.

Fig. 6 shows a schematic diagram of a data sampling device according to an embodiment of the present application.

Fig. 7 shows a schematic diagram of an electronic device provided in an embodiment of the present application.

Fig. 8 shows a schematic diagram of a computer storage medium provided in an embodiment of the present application.

Detailed Description

In order to better understand the solution of the present application, the following description will make clear and complete descriptions of the technical solution of the embodiment of the present application with reference to the accompanying drawings in the embodiment of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

It should be noted that in the embodiments of the present application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The embodiment of the application provides a data sampling method, which is applied to a scene that a plurality of optical network units are mounted on an optical modem of a user side, and GPON technology is in need of a scene that the speed of 2.488Gbps (high precision is 2.48832) is increased from the speed of 1.244Gbps (high precision is 1.24416) to the speed of 2.488Gbps (high precision is 2.48832) and the speed of 2.488Gbps (high precision is 2.48832).

The uplink data of the GPON protocol can be subjected to burst interruption and burst transmission, so that a receiving end CDR (clock data recovery ) is required to be capable of stably completing phase locking of recovered data within the time specified by the protocol, for the traditional technical scheme, the downlink 2.488Gbps rate and the uplink 1.244Gbps rate are usually selected by an FPGA device comprising 6.6G serdes, the rate of a GPON frame sent by a sending end of one channel of the serdes is 1.244Gbps, the receiving end of the channel receives 4 times of frequency of 1.244Gbps, a correct sampling point is found firstly through a 4 times oversampling mode, and then the phase drift of the sampling point (the phase drift generated by small-range frequency offset and period change of an opposite end or the phase drift generated by small-range frequency offset and rate change of the opposite end) is tracked, so that the phase locking within the time specified by the GPON protocol is realized; however, if the serdes receiving end samples the GPON frame according to 4 times frequency, the serdes with the 6.6G clock frequency in the existing FPGA obviously cannot meet the requirement in the face of the downlink 2.488Gbps rate and the uplink 2.488Gbps rate; if higher frequency serdes are selected, such as a 10G clock frequency serdes, the GPON frame can be sampled by 4 times, but this brings higher hardware cost. Therefore, the embodiment of the application provides a data sampling method, which uses a multi-channel parallel double oversampling scheme, increases sampling points by increasing sampling channels, can select two channels or more than two channels to be parallel according to actual needs, performs burst interrupt and burst transmission on uplink data of a GPON protocol, and enables a receiving end to stably complete phase locking of recovered data within a time specified by the protocol when the uplink data rate is upgraded to 2.5Gbps, and can acquire 2N (N is the number of selected channels) sampling data for data recovery in a unit time interval.

The first to nth channels described in the embodiments of the present application are all located in serdes, that is, the data sampling method described in the embodiments of the present application is implemented, and the number of selected channels cannot exceed the total channel data in serdes.

The SERDES includes a Serializer (Deserializer), which is a device that changes parallel data into serial data, and a Deserializer (Deserializer), which is a device that restores serial data into parallel data. In an actual application scene, the receiving end realizes a corresponding data receiving function through the FPGA, and the FPGA is generally internally provided with the SERDES, so that the receiving end can realize the data receiving through the internally provided SERDES. When the transmitting end communicates with the receiving end, based on the GPON protocol, the transmitting end transmits the GPON frame through the seriizer, when the receiving end receives the GPON frame, the optical modem is in a non-luminous state according to the allocated time slot, and after the receiving end receives the optical signal of the GPON frame, the receiving end converts the optical signal of the GPON frame into an electrical signal of the GPON frame and transmits the electrical signal to the desializer.

Fig. 1 shows a flowchart of a data sampling method according to an embodiment of the present application, as shown in fig. 1, where the data sampling method includes:

step S10: the clock signals of the first to N-th channels are configured so that the phase difference between clocks of any two adjacent channels reaches a first phase difference, and the first phase difference is not zero.

According to the data sampling method provided by the embodiment of the application, a multi-channel parallel double oversampling scheme is used, sampling points are increased by adding sampling channels, and clock phases on different channels of serdes are possibly not aligned in an initial state, so that clocks of selected channels are firstly trained through first data, and the initial phases of the clocks are aligned, wherein the first data are a group of data composed of binary numbers customized by a user, and when the clock phases of different channels are aligned, all channels are configured into a near-end serial loop-back mode (namely, the sending end of the channels sends the first data, and the receiving end of the channels receives the first data) so as to perform clock alignment training.

In some embodiments, fig. 2 shows a flowchart of configuring clock signals of first to nth channels according to an embodiment of the present application, as shown in fig. 2, step S10: configuring clock signals of first to N-th channels so that a phase difference between clocks of any two adjacent channels reaches a first phase difference, wherein the first phase difference is not zero, and the method comprises the following steps:

step S11: the method comprises the steps that a first channel, a second channel, a third channel and a fourth channel are configured to be near-end serial loopback, so that a sending end of the first channel, the second channel and the fourth channel continuously send first data to a receiving end, and the first data comprises at least one jump edge;

the first data is a group of data which is defined by a user and consists of binary numbers, when clock phases of different channels are aligned, all channels are configured into a near-end serial loopback mode (namely, a transmitting end of the channel transmits the first data, a receiving end of the channel receives the first data) so as to perform clock alignment training of each channel; for example, when the user self-defines the first data as 4' b1110,4 represents the number of bits, b represents the binary number, 1011 represents a specific value of the first data, and configures the first channel and the second channel to be in the near-end serial loopback mode, the transmitting ends of the first to nth channels continuously transmit the first data 1110 to the respective receiving ends, and in this embodiment, each channel uses the double oversampling method to sample, and the first data received by the receiving ends of the first to nth channels should be 11111100.

Step S12: shifting the phase of the clock signals of the first to N-th channels according to the first data, so that the phase difference between the clocks of any two adjacent channels is zero, namely the clocks of the first to N-th channels are in an aligned state at the moment;

in some embodiments, according to step S12: shifting the phase of the clock signals of the first to nth channels according to the first data so that the phase difference between the clocks of any two adjacent channels is zero, specifically comprising:

marking a first bit value of the first data, and respectively acquiring the first bit value in the first to N-th channels;

and shifting the clock phases of the first channel to the N channel until the first bit value jumps.

First marking first bits of first data, wherein the marked first bits can be first bits of the first data, when a user self-defines the first data as 4' b1110, for a transmitting end of any channel, a specific value of the marked first bits is 1 (first 1 in 1110), for a receiving end of any channel, received data is 11111100, taking the first channel as an example, the first channel receiving end continuously receives the first data, the received data of the receiving end is 11111100, the specific value of the obtained first bits is 1 (first 1 in 11111100), and then moving a clock phase of the first channel until the value of the first bits jumps, and the value of the first bits is changed from 1 to 0; the second through nth channels are the same as the first channel.

Taking n=2 as an example, fig. 3 shows a schematic diagram of clock alignment of the first to nth channels provided in the embodiment of the present application, as shown in fig. 3, D1 and D2 in fig. 3 represent first data (fig. 3 only shows two UIs) received by two adjacent UIs (Unit Interval), S0 and S0 'represent clock phases of first bits in D1 of the first channel and the second channel, respectively, and S5' represent clock phases of first bits in D2 of the first channel and the second channel, respectively; in practical application, only one UI needs to be selected. The following describes clock alignment in the embodiment of the present application through S0 and S0', as shown in fig. 3, the first channel and the second channel are not aligned in clock after receiving the first data (S0 and S0' are not aligned), which indicates that initial clock phases of the first channel and the second channel are not aligned; the clock phase of the first channel and the clock phase of the second channel are shifted, respectively, until S0 and S0' are aligned, indicating that the initial clock phases of the first channel and the second channel have been aligned. Specifically, the method for judging the alignment of S0 and S0' is as follows: respectively judging whether S0 in the first channel and S0' in the second channel move to a data jump edge or not; in D1, the first bits corresponding to S0 and S0' are both 1, and the PI value (Phase Interpolator ) of the CDR (clock data recovery, clock data recovery) is configured by the serdes low-speed configuration bus to shift the clock phase of the first channel and the clock phase of the second channel, where when the first bit corresponding to S1 changes from 1 to 0 and the first bit corresponding to S1' changes from 1 to 0 (i.e., the transition edge in fig. 3), it indicates that S0 and S0' are aligned, and also indicates that the clocks of the first channel and the second channel are aligned. Step S13: and shifting the phase of the clock signals of the second to N-th channels until the phase difference between the clocks of any two adjacent channels reaches the first phase difference, and releasing the near-end serial loop back of the first to N-th channel configurations.

Taking n=2 as an example, after the clocks of the first channel and the second channel are aligned, the phase of the clock of the second channel is continuously shifted until the phase difference between the clock of the second channel and the clock of the first channel is the first phase difference value. Fig. 4 is a schematic diagram showing the configuration of the first to second channel phase differences provided in the embodiment of the present application, as shown in fig. 4, the configuration of each channel phase difference in the embodiment of the present application is illustrated by S0 and S0', where the phase difference between S0' and S0 is the phase difference between the clock of the second channel and the clock of the first channel, and because the clock of the first channel and the clock of the second channel are already aligned, when the clock phase of the second channel is moved again, only the corresponding PI value needs to be configured according to the required first phase difference value, and then the near-end serial loop of the first channel and the second channel is released.

According to the data sampling method provided by the embodiment of the application, a multi-channel parallel double oversampling scheme is used, sampling points are increased by increasing sampling channels, and clock phases on different channels of serdes are possibly not aligned in an initial state, so that clocks of a first channel to an N channel are firstly trained through first data, initial phases of the clocks are aligned, and then the clock phases of a second channel to the N channel are moved, so that the phase difference of clocks between adjacent channels reaches a first phase difference. It should be clear that, in the embodiment of the present application, the receiving end of each channel continuously receives the first data until the clocks of the channels are aligned, where in the above example, the first data includes 4 binary numbers, and the number of binary numbers is not limited when the first data is customized in practical application, as long as the first data includes a jump edge. Fig. 3 shows only data of two UIs, and is used only for explaining step S12 and step S13 of the embodiment of the present application.

In some embodiments, the data sampling method provided in the embodiments of the present application, before step S10, further includes:

the clocks for the various channels are initialized.

Step S20: GPON data are respectively input to the first to N channels, and clock signals of the first to N channels are configured as follows:

the first phase and the second phase of the clock signal are marked as a first sampling point and a second sampling point, the GPON data of each channel is sampled according to the first sampling point, and the GPON data of each channel is sampled according to the second sampling point.

After the near-end serial loop of the first to N-th channels is released, based on the GPON protocol, the optical module receives the optical signal of the GPON frame in the opposite-end non-luminous state according to the allocated time slot, converts the optical signal into an electrical signal, outputs the electrical signal to the serdes of the FPGA, namely respectively outputs the electrical signal to the first to N-th channels of the serdes, wherein the electrical signal comprises data to be sampled, and for GPON data, the electrical signal comprises GPON effective data and a preamble, and the first to N-th channels firstly receive the preamble to acquire the correct sampling position. Taking n=2 as an example, fig. 5 shows a schematic diagram of sampling of the first to second channels provided in the embodiment of the present application, where D1 and D2 represent preambles received by two adjacent UIs (Unit Interval), S1 and S2 represent a first phase and a second phase in the first channel (i.e., a first sampling point and a second sampling point of the first channel), S1' and S2' represent a first phase and a second phase in the second channel (i.e., a first sampling point and a second sampling point of the second channel), S3 and S4 represent two sampling phases in the first channel of the adjacent UIs, S3' and S4' represent two sampling phases in the second channel of the adjacent UIs, respectively, and in the embodiment of the present application, four sampling points can be acquired in the same UI in a multi-channel parallel double oversampling manner, and four sampling points S1, S2, S1', S2' and S1' and S2' are illustrated as example, and S3 and S4 are illustrated as phase difference values, and S1' and S2 are also phase difference values.

In some embodiments, the first phase difference is

A degree; and the phase difference between the second phase and the first phase of the clock signal of any channel is 180 degrees.

When n=2, the first phase difference value is 90 degrees, that is, when the phase of S1 is X, the phase of S2 is x+180 degrees; the phase difference between S2 and S1 is 90 degrees, the phase difference between S2 'and S1' is 90 degrees, and compared with the first channel, the phase of S2 'is X+90 degrees, and the phase of S2' is X+270 degrees; it should be clear that when the clock of the second channel is used as a reference, the phase of S1 'is X and the phase of S2' is x+180 degrees with respect to the clock of the second channel.

In some embodiments, when n=3, the first phase difference value is 60 degrees, that is, based on the first channel, the phases of the two sampling points obtained from the first channel are: x degrees, X+180 degrees; the phases of the two sampling points acquired from the second channel are: x+60 degrees, X+240 degrees; the phases of the two sampling points acquired from the third channel are: x+120 degrees, x+300 degrees.

Step S30: and 2N data acquired by the N channels according to the first sampling point and the second sampling point are output in parallel.

After four sampling points (S1S 1 'S2S 2') are acquired from the same UI (D1) of the first channel and the second channel, tracking the four sampling points at any moment, waiting for the transmission of sampling data, sampling the data to be sampled at the four sampling points, and for GPON data, after the transmission of a preamble is completed, receiving GPON valid data by the first to N channels, and sampling the GPON valid data according to the acquired four sampling points; and outputting the sampled data in parallel, namely, the total number of the acquired sampled data is 2N.

In this embodiment of the present application, whether each channel transmits the first data or each channel receives the preamble and the GPON valid data, it means that each channel receives the first data or both the preamble and the GPON valid data.

It should be clear that, in the data sampling method provided in the embodiment of the present application, when a multi-channel parallel double oversampling method is used, all sampling points can be obtained according to the phase difference between different sampling points as long as the position of the first phase S1 of the first channel is obtained, and the specific position of the first phase S1 of the first channel may be determined according to an existing method, for example, S1 may be a sampling point randomly obtained from a UI, or S1 may also be a sampling point obtained according to experience after multiple experiments by a designer, or S1 may also be a sampling point obtained according to an existing double oversampling method, or S1 may also be a sampling point obtained according to an existing quadrupling oversampling method, etc.; in order to ensure that 4 sampling points can be obtained in the same UI, as long as the phase of S1 is added to 270 degrees by no more than 360 degrees, in fact, if the phase of S1 selected is added to 270 degrees by more than 360 degrees, a sampling point indicating that the selected S1 is preceded by an appropriate phase may be selected. Specifically, the sample is that a position with a larger margin is selected as a sampling point in one period, and the sampling points have certain randomness when being selected.

According to the data sampling method provided by the embodiment of the application, a double oversampling scheme of multichannel parallelism is used, sampling points are increased by increasing sampling channels, phase locking of recovered data can be completed stably within the specified time of a GPON protocol, for the transmission rate of 2.488Gbps of GPON uplink data, the phase locking of the recovered data can be completed within the specified time as long as the clock frequency of a first channel receiving end and a second channel receiving end of 2.488Gbps is satisfied, 2N sampled data can be obtained in the first to N channels in a unit time interval for data recovery, the sampling performance is equivalent to the sampling performance of phase locking within the specified time of the GPON protocol through a 4-time oversampling mode when N=2, and when N > 2, the sampling performance is superior to the sampling performance of phase locking within the specified time of the GPON protocol through the 4-time oversampling mode in the traditional technical scheme.

Fig. 6 is a schematic diagram of a data sampling device according to an embodiment of the present application, as shown in fig. 6, based on the above data sampling method, the embodiment of the present application provides a data sampling device 60, as shown in fig. 6, where the device 60 includes:

a clock alignment module 100, configured to configure clock signals of the first to nth channels so that a phase difference between clocks of any two adjacent channels reaches a first phase difference, where the first phase difference is not zero;

the sampling module 200 is configured to input GPON data to the first to nth channels, and configure clock signals of the first to nth channels to be:

marking a first phase and a second phase of a clock signal as a first sampling point and a second sampling point, sampling GPON data of each channel according to the first sampling point, and sampling the GPON data of each channel according to the second sampling point;

the output module 300 is configured to output 2N data acquired according to the first sampling point and the second sampling point in parallel;

in the clock alignment module 100, configuring the clock signals of the first to nth channels so that the phase difference between the clocks of any two adjacent channels reaches the first phase difference includes:

For other details of implementing the above technical solution by each module in the above sampling device, reference may be made to the description in the data sampling method provided in the above embodiment of the present invention, which is not repeated herein.

Based on the data sampling method provided in the above embodiment, as shown in fig. 7, the embodiment of the application further provides a schematic structural diagram of an electronic device, where the electronic device includes a processor 71 and a memory 72 coupled to the processor. The memory 72 stores a computer program which, when executed by the processor 71, causes the processor 71 to perform the steps of the data sampling method in the above-described embodiment.

For further details of the implementation of the foregoing technical solution by the processor in the electronic device, reference may be made to the description of the data sampling method provided in the foregoing embodiment, which is not repeated herein.

Wherein the processor may also be referred to as a CPU (Central Processing Unit ), which may be an integrated circuit chip, having signal processing capabilities; the processor may also be a general purpose processor, which may be a microprocessor or which may also be any conventional processor, etc., a DSP (Digital Signal Process, digital signal processor), ASIC (Application Specific Integrated Circuit ), FPGA (Field Programmable Gata Array, field programmable gate array) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, etc.

As shown in fig. 8, the embodiment of the present application further provides a schematic structural diagram of a computer readable storage medium, where the storage medium 80 stores a readable computer program 81; the computer program 81 may be stored in the storage medium 80 as a software product, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a magnetic or optical disk, a ROM (Read-Only Memory), a RAM (Random Access Memory), or a terminal device such as a computer, a server, a mobile phone, or a tablet.

The foregoing is a further detailed description of the present application in connection with the specific embodiments, and it is not intended that the practice of the present application be limited to such descriptions. It should be understood by those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the present application, and the present application is not limited to the above-mentioned embodiments.

Claims

1. A method of data sampling, comprising:

2. The data sampling method according to claim 1, wherein the step of shifting the phases of the clock signals of the first to nth channels in accordance with the first data so that the phase difference between clocks of any two adjacent channels is zero, comprises:

3. The data sampling method of claim 1, wherein the first phase difference is

Degree.

4. The data sampling method according to claim 1, wherein the second phase of the clock signal of any one of the first to nth channels is 180 degrees out of phase with the first phase.

5. The data sampling method of claim 1, wherein the

Or said->

。

6. The data sampling method according to claim 1, wherein before the step of configuring the clock phases of the first to nth channels so that the phase difference between clocks of any two adjacent channels reaches the first phase difference, further comprising:

initializing clocks of the first to nth channels.

7. A data sampling device, comprising:

the output module is used for outputting 2N data acquired by the N channels according to the first sampling points and the second sampling points in parallel;

8. An electronic device comprising a memory and a processor, wherein:

the memory is used for storing a computer program;

the processor is configured to read the computer program in the memory and execute the steps of the data sampling method according to any one of claims 1 to 6.

9. A computer readable storage medium, having stored thereon a readable computer program which when executed by a processor performs the steps of the data sampling method according to any of claims 1 to 6.