SG10201804609UA - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- SG10201804609UA SG10201804609UA SG10201804609UA SG10201804609UA SG10201804609UA SG 10201804609U A SG10201804609U A SG 10201804609UA SG 10201804609U A SG10201804609U A SG 10201804609UA SG 10201804609U A SG10201804609U A SG 10201804609UA SG 10201804609U A SG10201804609U A SG 10201804609UA
- Authority
- SG
- Singapore
- Prior art keywords
- conductive type
- doping area
- insulating film
- gate insulating
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
- H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Thin Film Transistor (AREA)
Abstract
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF A semiconductor device, includes a first conductive type first doping area, a second conductive type second doping area, a source region, a drain region, a gate insulating film, and a gate electrode. The first conductive type first doping area is formed in a substr ate region. The second conductive type second doping area is formed in the substrate to be spaced apart from the first conductive type first doping area. The source region is formed in the first conductive type first doping area. The drain region is formed in the second conductive type second doping area. The gate insulating film is formed between the source region and the drain region. A thickness of a first end of the gate insulating film is different than a thickness of a second end of the gate insulating film. The gate electrode formed on the gate insulating film. Fig. 3
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020170089116A KR102299662B1 (en) | 2017-07-13 | 2017-07-13 | Semiconductor Device and Method for Fabricating the Same |
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SG10201804609UA true SG10201804609UA (en) | 2019-02-27 |
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SG10201804609UA SG10201804609UA (en) | 2017-07-13 | 2018-05-31 | Semiconductor device and manufacturing method thereof |
Country Status (6)
Country | Link |
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US (1) | US10727300B2 (en) |
KR (1) | KR102299662B1 (en) |
CN (1) | CN109256425A (en) |
DE (1) | DE102018116869A1 (en) |
SG (1) | SG10201804609UA (en) |
TW (1) | TWI791494B (en) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
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US11018266B2 (en) * | 2018-10-23 | 2021-05-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Reduced surface field layer in varactor |
KR102642021B1 (en) * | 2019-01-31 | 2024-02-29 | 매그나칩 반도체 유한회사 | Semiconductor device and manufacturing method thereof |
US11189565B2 (en) | 2020-02-19 | 2021-11-30 | Nanya Technology Corporation | Semiconductor device with programmable anti-fuse feature and method for fabricating the same |
KR102274813B1 (en) * | 2020-02-27 | 2021-07-07 | 주식회사 키 파운드리 | A Manufacturing Method of Semiconductor Device Using Gate-Through Implantation |
KR102362576B1 (en) | 2020-04-02 | 2022-02-11 | 매그나칩 반도체 유한회사 | Semiconductor device and manufacturing method thereof |
US11152381B1 (en) * | 2020-04-13 | 2021-10-19 | HeFeChip Corporation Limited | MOS transistor having lower gate-to-source/drain breakdown voltage and one-time programmable memory device using the same |
US11114140B1 (en) | 2020-04-23 | 2021-09-07 | HeFeChip Corporation Limited | One time programmable (OTP) bits for physically unclonable functions |
US11437082B2 (en) | 2020-05-17 | 2022-09-06 | HeFeChip Corporation Limited | Physically unclonable function circuit having lower gate-to-source/drain breakdown voltage |
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US10727300B2 (en) | 2020-07-28 |
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