SG10201406984RA - Semicondcutor device and method offorming embedded wafer level chip scale packages - Google Patents
Semicondcutor device and method offorming embedded wafer level chip scale packagesInfo
- Publication number
- SG10201406984RA SG10201406984RA SG10201406984RA SG10201406984RA SG10201406984RA SG 10201406984R A SG10201406984R A SG 10201406984RA SG 10201406984R A SG10201406984R A SG 10201406984RA SG 10201406984R A SG10201406984R A SG 10201406984RA SG 10201406984R A SG10201406984R A SG 10201406984RA
- Authority
- SG
- Singapore
- Prior art keywords
- wafer level
- chip scale
- level chip
- scale packages
- embedded wafer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10156—Shape being other than a cuboid at the periphery
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/070,509 US9704824B2 (en) | 2013-01-03 | 2013-11-02 | Semiconductor device and method of forming embedded wafer level chip scale packages |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201406984RA true SG10201406984RA (en) | 2015-06-29 |
Family
ID=53348180
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201800413PA SG10201800413PA (en) | 2013-11-02 | 2014-10-27 | Semiconductor device and method of forming embeddedwafer level chip scale packages |
SG10201406984RA SG10201406984RA (en) | 2013-11-02 | 2014-10-27 | Semicondcutor device and method offorming embedded wafer level chip scale packages |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201800413PA SG10201800413PA (en) | 2013-11-02 | 2014-10-27 | Semiconductor device and method of forming embeddedwafer level chip scale packages |
Country Status (3)
Country | Link |
---|---|
CN (1) | CN104701195B (zh) |
SG (2) | SG10201800413PA (zh) |
TW (1) | TWI651783B (zh) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10366956B2 (en) | 2015-06-10 | 2019-07-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20170098628A1 (en) * | 2015-10-05 | 2017-04-06 | Mediatek Inc. | Semiconductor package structure and method for forming the same |
US10123419B2 (en) * | 2016-03-30 | 2018-11-06 | Intel Corporation | Surface-mountable power delivery bus board |
TWI622142B (zh) | 2016-11-07 | 2018-04-21 | 財團法人工業技術研究院 | 晶片封裝體以及晶片封裝方法 |
TWI664683B (zh) * | 2017-03-16 | 2019-07-01 | 佳邦科技股份有限公司 | 半導體封裝件的製造方法 |
CN107342256A (zh) * | 2017-06-26 | 2017-11-10 | 矽力杰半导体技术(杭州)有限公司 | 半导体工艺及半导体结构 |
US10283424B1 (en) * | 2018-03-08 | 2019-05-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Wafer structure and packaging method |
CN109002806A (zh) * | 2018-07-27 | 2018-12-14 | 星科金朋半导体(江阴)有限公司 | 一种qfn产品的后道封装方法 |
TWI670779B (zh) * | 2018-11-16 | 2019-09-01 | 典琦科技股份有限公司 | 晶片封裝體的製造方法 |
TWI703615B (zh) * | 2019-08-12 | 2020-09-01 | 矽品精密工業股份有限公司 | 電子封裝件之製法 |
US11538787B2 (en) * | 2020-10-30 | 2022-12-27 | Advanced Semiconductor Engineering, Inc. | Method and system for manufacturing a semiconductor package structure |
CN112885793A (zh) * | 2021-03-12 | 2021-06-01 | 苏州晶方半导体科技股份有限公司 | 芯片封装结构及其制造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0574932A (ja) * | 1991-09-17 | 1993-03-26 | Fujitsu Ltd | 半導体ウエハのダイシング方法 |
CN101521165B (zh) * | 2008-02-26 | 2012-01-11 | 上海凯虹电子有限公司 | 芯片级封装方法 |
US20110014746A1 (en) * | 2009-07-17 | 2011-01-20 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Conductive TSV in Peripheral Region of Die Prior to Wafer Singulaton |
EP2453474A1 (en) * | 2010-11-10 | 2012-05-16 | Nxp B.V. | Semiconductor device packaging method and semiconductor device package |
US8659166B2 (en) * | 2010-11-18 | 2014-02-25 | Headway Technologies, Inc. | Memory device, laminated semiconductor substrate and method of manufacturing the same |
US8642385B2 (en) * | 2011-08-09 | 2014-02-04 | Alpha & Omega Semiconductor, Inc. | Wafer level package structure and the fabrication method thereof |
CN103035578B (zh) * | 2011-10-06 | 2017-08-18 | 新科金朋有限公司 | 形成具有较大载体的重构晶片的半导体器件和方法 |
CN103117232B (zh) * | 2011-11-16 | 2015-07-01 | 美新半导体(无锡)有限公司 | 晶圆级封装方法及其封装结构 |
TWI463619B (zh) * | 2012-06-22 | 2014-12-01 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
-
2014
- 2014-10-21 TW TW103136264A patent/TWI651783B/zh active
- 2014-10-27 SG SG10201800413PA patent/SG10201800413PA/en unknown
- 2014-10-27 SG SG10201406984RA patent/SG10201406984RA/en unknown
- 2014-10-31 CN CN201410858205.3A patent/CN104701195B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
TWI651783B (zh) | 2019-02-21 |
SG10201800413PA (en) | 2018-03-28 |
TW201519331A (zh) | 2015-05-16 |
CN104701195B (zh) | 2019-11-29 |
CN104701195A (zh) | 2015-06-10 |
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