SE9401882L - Device for converting a binary floating point into a 2 logarithm in binary form or vice versa - Google Patents

Device for converting a binary floating point into a 2 logarithm in binary form or vice versa

Info

Publication number
SE9401882L
SE9401882L SE9401882A SE9401882A SE9401882L SE 9401882 L SE9401882 L SE 9401882L SE 9401882 A SE9401882 A SE 9401882A SE 9401882 A SE9401882 A SE 9401882A SE 9401882 L SE9401882 L SE 9401882L
Authority
SE
Sweden
Prior art keywords
logarithm
floating
binary
point number
adder
Prior art date
Application number
SE9401882A
Other languages
Unknown language ( )
Swedish (sv)
Other versions
SE9401882D0 (en
SE502892C2 (en
Inventor
Erik Hertz
Original Assignee
Foersvarets Forskningsanstalt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Foersvarets Forskningsanstalt filed Critical Foersvarets Forskningsanstalt
Priority to SE9401882A priority Critical patent/SE502892C2/en
Publication of SE9401882D0 publication Critical patent/SE9401882D0/en
Priority to PCT/SE1995/000620 priority patent/WO1995033308A1/en
Publication of SE9401882L publication Critical patent/SE9401882L/en
Publication of SE502892C2 publication Critical patent/SE502892C2/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/14—Conversion to or from non-weighted codes
    • H03M7/24—Conversion to or from floating-point codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Complex Calculations (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The present invention concerns a device for conversion of a binary floating-point number into a binary fix-point 2-logarithm number or the opposite. This is done in the case of conversion of a binary floating-point number by making the invention include an input register where the floating-point number is stored, an output register for the calculated logarithm, a device that transfers the exponent of the floating-point number from the input register to the output register, where it directly forms the characteristic of the logarithm, a device that transfers the fractional part of the mantissa of the floating-point number from the input register to an adder and also to one or more part circuits that forms additional parts, a device that transfers the additional parts to the adder, said adder that adds the fractional part of the mantissa of the floating-point number and said additional parts and a device that transfers the sum from the adder to the output register where it forms the fractional part of 2-logarithm. Further, the part circuit or part circuits is arranged to be able to use different scale factors in different computing intervals. The conversion from a logarithm is carried out in a similar manner and with the same components.
SE9401882A 1994-06-01 1994-06-01 Device for converting a binary floating point into a 2-logarithm in binary form or vice versa SE502892C2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
SE9401882A SE502892C2 (en) 1994-06-01 1994-06-01 Device for converting a binary floating point into a 2-logarithm in binary form or vice versa
PCT/SE1995/000620 WO1995033308A1 (en) 1994-06-01 1995-05-31 A device for conversion of a binary floating-point number into a binary 2-logarithm or the opposite

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9401882A SE502892C2 (en) 1994-06-01 1994-06-01 Device for converting a binary floating point into a 2-logarithm in binary form or vice versa

Publications (3)

Publication Number Publication Date
SE9401882D0 SE9401882D0 (en) 1994-06-01
SE9401882L true SE9401882L (en) 1995-12-02
SE502892C2 SE502892C2 (en) 1996-02-12

Family

ID=20394197

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9401882A SE502892C2 (en) 1994-06-01 1994-06-01 Device for converting a binary floating point into a 2-logarithm in binary form or vice versa

Country Status (2)

Country Link
SE (1) SE502892C2 (en)
WO (1) WO1995033308A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7284027B2 (en) 2000-05-15 2007-10-16 Qsigma, Inc. Method and apparatus for high speed calculation of non-linear functions and networks using non-linear function calculations for digital signal processing

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5365465A (en) * 1991-12-26 1994-11-15 Texas Instruments Incorporated Floating point to logarithm converter
SE470542B (en) * 1992-12-07 1994-07-25 Foersvarets Forskningsanstalt Device for converting a binary floating point into a 2 logarithm in binary form or vice versa
FI96810C (en) * 1993-05-26 1996-08-26 Nokia Oy Ab Method and apparatus for converting an analog signal to a digital floating point number and converting the digital floating point number to an analog signal

Also Published As

Publication number Publication date
SE9401882D0 (en) 1994-06-01
SE502892C2 (en) 1996-02-12
WO1995033308A1 (en) 1995-12-07

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