NZ198035A - Integrated bipolar-mos switch - Google Patents

Integrated bipolar-mos switch

Info

Publication number
NZ198035A
NZ198035A NZ19803581A NZ19803581A NZ198035A NZ 198035 A NZ198035 A NZ 198035A NZ 19803581 A NZ19803581 A NZ 19803581A NZ 19803581 A NZ19803581 A NZ 19803581A NZ 198035 A NZ198035 A NZ 198035A
Authority
NZ
New Zealand
Prior art keywords
region
switch according
type semiconductor
contact
switch
Prior art date
Application number
NZ19803581A
Inventor
J Pernyeszi
Original Assignee
Int Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Int Standard Electric Corp filed Critical Int Standard Electric Corp
Publication of NZ198035A publication Critical patent/NZ198035A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
    • H01L27/0722—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with lateral bipolar transistors and diodes, or capacitors, or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
    • H01L27/0716—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Electronic Switches (AREA)

Description

Priority Date(s): 35; Complete Specification Filed: M-.'.'&'Sl Class: Publication Date: . .|f .1. .APR P.O. Journal, l\!o: NEW ZEALAND THE PATENTS ACT, 1953 COMPLETE SPECIFICATION "a semiconductor switch" WE, INTERNATIONAL STANDARD ELECTRIC CORPORATION, a Corporation of the State of Delaware, United States of America, of 320 Park Avenue, New York 22, New York, United States of America, hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: 1 98 0 35 The present invention relates to semiconductor devices and is particularly applicable to a high voltage semiconductor switch.
In U.S. Patent 4,170,740, entitled "High Voltage Switch and Capacitive Drive", the high voltage switch and capacitor drive employs two VMOS (Vertical Diffusion Differential Metal Oxide Semiconductor) transistors as the switching elements. The size of the VMOS transistors is dependent on the voltage and current rating of the device in which they are used. The circuit of the above-identified patent is a relay replacement and, therefore, the VMOS transistors should have a low ON resistance. For a high voltage device, the VMOS transistor switching elements known in the prior art have a high resistivity and a fairly thick substrate on n-type semiconductor material has to be used to provide sufficient room for the depletion layers and to keep the electric field well below the critical value. The resistance of the n-material of these prior art VMOS transistors is a major part of the ON resistance and, as a result, is relatively high and thereby causes a deterioration of the switching characteristics of these prior art VMOS transistors.
It is desirable to provide an improved high voltage semiconductor switch having a reduced ON resistance thereby overcoming the above-mentioned disadvantage of the prior art VMOS transistors.
J 98 0 3 A high voltage semiconductor switch employing a bipolar boost action in order to reduce the ON resistance per silicon area factor of the semiconductor switch is also desirable.
A high voltage semiconductor switch having a parasitic PNP transistor whose base current is supplied by the drain of an MOS of either the VMOS type or the DNOS (Lateral Double Diffusion Metal Oxide Semiconductor) type would also be advantageous.
In a preferred embodiment there is provided a high voltage semiconductor switch comprising an n-type semiconductor region to provide a drain for a MOS transistor and a base for a PNP transistor, the MOS transistor and the PNP transistor having the same base and drain current; a first p+ type semiconductor region disposed in the n- region to provide one of a collector and an emitter for the PNP transistor; a second p+ type semiconductor region disposed in the n- region spaced from the first p+ region to provide the other of the collector and emitter for the PNP transistor; a p semiconductor region disposed in the n- region adjacent one of the first and second p+ regions to provide a gate for the MOS transistor; and a n+ type semiconductor region disposed in the p region to provide a source for the MOS transistor.
Above-mentioned and other features and objects of this invention will become more apparent by reference to the following description taken in conjunction with the accompanying 1 98 0 3 drawing, in which: Fig. 1 is a schematic illustration of a high voltage semiconductor switch in accordance with the principles of the present application utilizing a VMOS type configuration; Fig. 2 is a schematic illustration of a modification of the high voltage semiconductor switch of Figure 1; Fig. 3 is an equivalent circuit diagram of the high voltage semiconductor switch of Figures 1 and 2; Fig. 4 is a schematic illustration of a high voltage semiconductor switch .employing a DMOS type configuration; and Fig. 5 is an equivalent circuit diagram of the high voltage switch of Figure 4.
Referring to Figure 1, there is illustrated therein a VMOS high voltage semiconductor switch having a p+ type semiconductor buried layer 1. Basically, the switch comprises a parasitic PNP transistor formed by the p+ buried layer 1 as its emitter, the n- type semiconductor undiffused starting material or substrate 2 as its base and a p+ type semiconductor contact diffusions 3 as its collector. The VMOS transistor is formed by material or substrate 2 as its drain, a p type semiconductor region 4 as its gate or bulk, and a n+ type semiconductor region 5 as its source. Layer 1 and regions 3-5 are >1 98035 provided by double diffusion techniques well known in the prior art.
A groove 6 is provided in each of regions 4 between regions 3 and extending into substrate 2 to provide the well known V groove channel for a VMOS. Each of grooves 6 have a semiconductor oxide layer 7 coated thereon which in turn is covered by a metal coating 8. Metal coating 8 is coupled to the gate voltage. The other regions 3 and 5 have contacts 9 on the surface thereof to enable these regions to be connected to a negative source voltage.
Layer 1 is coated by a semiconductor oxide such as silicon oxide (SiC^) - This same semiconductor oxide may also be employed for coating 7 in the V groove contacts.
In the modification of Figure 1 shown in Figure 2, the metal contacts 9 of region 3 are replaced by V groove contacts containing the metal contacts 11.
From Figures 1 and 2, the following observations are made. (1) The VMOS transistor drain and the PNP transistor base are the same region 2, meaning, that the VMOS transistor drain current becomes the PNP transistors base current. (2) The PNP transistor's base, namely, region 2, is uniformly doped, i.e., there is no built—in field. (3) The V groove contacts 11 of Figure 2 in the region f 98 0 3 5 3 will minimize the voltage drop that could forward bias the bulk-source junction (junction of regions 4 and 5) of the VMOS.
The equivalent circuit of the high voltage semiconductor switch of Figures 1 and 2 is shown in Figure 3 and includes a VMOS transistor with a PNP transistor and an NPN transistor 2 Q . The transistor is formed in the structure of Figures 1 and 2 by region 5 on one side of region 3 acting as its emitter, region 5 on the other side of region 3 acting as its base and region 3 acting as its collector. Transistors C>2 and can potentially latch, however, with careful design, resistor (the resistance of region 2) can be kept very small so that the voltage drop across it will be less than 0.6 volts, which is the turn-on voltage for the base of transistor C>2 • The emitter-base breakdown of transistor is pretty much the same as its collector-base breakdown. Therefore, transistor will act as a diode if the drain voltage is negative compared to the source voltage.
The following describes a reduction to practice of the VMOS high voltage semiconductor switch of Figures 1 and 2 illustrating the operability thereof to achieve a reduction in the ON resistance of the high voltage semiconductor switch of the present invention.
Starting material: 20 ohm cm, N type, <100>, 2/1014 -3 9 2 /sec 1/cm , yp = 400 cm /Vsec, T = 15ysec, Dp = 10.4 cm P s LD = /Dp Tp = Ao.4. 15. 10 6 = 124 . 7 ym ,The PNP is assumed to work in the high injection region and Dp in the transport efficiency equation will be taken double that of the equilibrium value.
X 3' = 1 = 1 - 0.9892 ;n , W ,38 u; LD 258 The above assumption will be verified by calculating the current density and comparing the injected hole density to the equilibrium electron density.
The p+ buried layer 1 is heavily doped and considered to form a step junction with the n- layer 2. The above is a valid assumption, although the profile is really a Gaussian one, but since the doping level of layer 1 is so much higher than that of layer 2 the transistion region is very short making the junction work like a step junction.
The buried layer's characteristics are: 19 3 2 0.01 ohm cm, P type, 10 1/cm , Dn = 2.5cm /sec, Tn = 1.2ysec LN = /DnTn = A.. 2.10_62.5 = 1.73 10_3cm = 17ym The resistivity figure is an exaggerated worst case value.
It is taken low to account for the high temperature processing subsequent to buried layer diffusion.
With the above values and a lower limit on the gain the maximum current density will be calculated again assuming high level injection conditions.
Y* 1 - Sp + W (l + — I (2) Ip Sn - Ln \ ND fl 98 0 3 5 The limit on y ' _> 0.95 is reasonable, since this results in a hpE = 20. The maximum current the device is to handle will not exceed 120 mA. From equation (2) Pn (1_Y) Sn Ln _ v r; Sp + W nd (1-0,95) 20;1.73■1Q~3 - 1 0.01 * 38 *10-4 14 2 .10 8.9-1015 1/cm3 This result is two orders of magnitude higher than the equilibrium electron density and it verifies the assumptions made for high level injection.
The collector current can be expressed as the derivative 10 of the hole density taken at the collector-base junction. :c = iE dx x=w (3A) Neglecting recombination and considering the high injection. ^pE - AgDp — (3B) From this, the emitter-base junction area that gives the: proper current density can be expressed. ~ _ JPE W = 0.12*38*10~4 = 1.54-10-2 cm2 (4) AgDpP 1.6*10~19-20.8-8.9-1015 This is a device 0.124 cm on the side. (48.8 mil) .
Adding 2 mils all around will make the device 52.8 mils on the side. According to Figure 1 this will accommodate a V channel 6 width of 54 x 1242ym. Using BTM's present diffusion ; schedule for VMOS with less oxide thickness for the channel i ( resistance we get. ; R , = 1 = 1 = 1 = 1 368 ohm (5) I ch e (tq - vt) k,h (vg-vt) 56i2m(10-2 L o . D / 2 5 This will be in series with the drain bulk resistance.
The drain bulk resistance can be calculated from the parameters of the N- starting material using the geometry of Figure 1 and considering the non-uniform current distribution. At the tip. of groove 6 there is a surface accumulation layer. The electrons coming from the channel will end up momentarily in this accumulation layer and be emitted into the n- layer 2 from there. For sake of simplicity, its shape is approximated with a half cylinder. So the n- resistance is somewhat independent of the thickness n- layer 2. r = s_ £n r_ = 20 Jin 11.5 =' 1.93 ohm' (6) &7T r 6. 7ir 1.5 o Where& is the channel width, o is the radius of the half cylinder, and r is the half distance between the grooves.
The rest of the resistance of layer 2 is the resistance of the section extending from r to the buried layer 1 lengthwise and from the middle of one contact groove to the middle of the next.
R2 = Sfw - r) = 20(40-11.5)10~4 = 3.69 ohm (7) AL 6.7 * 23 *10-4 where wis the thickness of region 2 and L is the distance between the two contact grooves 6.
From the above, the total resistance of region 2 is Rn- = R1 + R2 = 1.93 + 3.69 = 5.62 ohm This does not include the effect of the conductivity modulation, thus, it can be considered the most pessimistic approximation of the ON resistance calculation. The total VMOS ON resistance is the sum of the channel and bulk resistance.
R0N ~ Rch + Rn- = ^ + 5.62 = 6.98 ohm (8) This will be divided by the current gain of the parasitic PNP.
The diffusions are the same as were used by BTM except for the p bulk, where some modification might be necessary with simultaneously adjusting the gate oxide thickness to some lower value to achieve a 2 volt threshold. Lowering the threshold will lower the ON resistance. This effect is quite significant since the conductivity modulation taking place in the n- region 2 will lower its resistance. The resistivity is dependent on the minority carrier density. Since this is the base of a transistor, the minority carrier distribution and with it the resistivity will vary. The resistivity can be expressed as the function of the injected carrier density.
S1 = S 1 n- n- j—-—(9) % Substituting (9) into (7) we get W/" W el ( (10) n- dx \ dx ZL Sn~ / (1 +J ) ZL Q D The upper limit was also changed to W, since the hole distribution is not dependent on the lateral coordinate and, therefore, the current density is uniform.
Usine Equation (3B) to express Po we get P = Iw ° AgDp (11) Assuming P will become zero at the collector junction and is a linear function 7 98 035 P = Po (1 - x) ) = iw (1 - x ) (12) W AgDp W where x = o is the emitter-base junction.
Substituting (12) into (10) and executing the integral R2 = Sn- AgpPND n (i + iw = &LI AgDpN^j -1.54-10~2-1.6-10~19 20.8-2-1014 (13) 6.7*23 *10-4 *0.12 Jin (1 + 0.12-38-104 -9 -19 14^ 1.54-10 -16-10 -20.82-10 ' = 0.423 ohms When this is divided by the gain of the PNP transistor, the ON resistance will be about 0.02 ohms.
Referring to Figure 4, there is illustrated therein a high voltage semiconductor DMOS type switch embodying the present invention. In the switch of the DMOS type there is a lateral PNP transistor formed in one surface of the n- type semiconductor region 12 including the diffusion contacts of the p+ type semiconductor regions 13 and 14 whereas illustrated in Figure 4 region 13 provides the emitter of the PNP trans-ister and region 14 provides the colletor for the PNP trans-ister with region 12 providing the base therefor. The DMOS in the device of Figure 4 is provided by region 12 operating as the drain, the P type semiconductor region 15 diffused in region 12 on the same surface thereof as regions 13 and 14 operating as the DMOS gate and a n+ semiconductor region 16 diffused in the upper surface of region 15 remote from region 12, which functions as the source for DMOS transistor. A semiconductor oxide layer 17 is provided on the surface of region 12 opposite the surface containing regions 13 - 16. The regions 1 0 3 13 - 16 are each provided with metallic contacts 18 with certain of the contacts 18 having field plate 19 connected thereto to enhance the voltage breakdown in the device.
The switch of Figure 4 has a low ON resistance and a high current carrying capability. The electron current flow (minus) enduces a flow of positive charge (holes) in the reverse direction. The illustrated geometry of the switch of Figure 4 is such that the hole and electron flow is separated and such that the holes are carried to the desired region 14.
Figure 5 illustrates the equivalent circuit of the device of Figure 4 and again we find that the PNP transistor and the DMOS transistor have the same base and drain currents due to region 12 of Figure 4 being both the base for the PNP transistor and the drain for the DMOS transistor. 12

Claims (21)

198035 What we claim is:-
1. A high voltage semiconductor switch comprising:an n-type semiconductor region to provide a drain for a MOS transistor and a base for a PNP transistor, said MOS transistor and said PNP transistor having the same base and drain current; a first P+ type semiconductor region disposed in said n-region to provide one of a collector and an emitter for said PNP transistor; a second p+ type semiconductor region disposed in said n-region spaced from said first p+ region to provide the other of said collector and emitter for said PNP transistor; a p type semiconductor region disposed in said n-region adjacent one of said first and second p+ regions to provide a gate for said MOS transistor; and an n+ type semiconductor region disposed in said p region to provide a source for said MOS transistor.
2. A switch according to claim 1, wherein said n-region is uniformly doped.
3. A switch according to claim 1 or 2, wherein said n-region has a thickness greater than the thickness of any of the other of said regions such that the resistance of said n-region primarily determines the ON resistance of said switch.
4. A switch according to any one of claims 1 to 3 wherein said MOS transistor has a VMOS configuration.
5. A switch according to any one of claims 1 to 4 wherein one of the said first and second p+ regions includes at least 13 198035 one p+isemlconductor diffusion contact area at one surface of said n-region, and the other of said first and second p+ regions includes a p+ type semiconductor layer diffused on the other surface of said n-region.
6. A switch according to claim 5, wherein said p+ layer is heavily doped to provide a step junction with said n-region.
7. A switch according to claim 5 or 6 wherein said one of said first and second p+ regions includes a plurality of said contact areas each spaced with respect to each other along said one surface of said n-region.
8. A switch according to claim 7, wherein said p region is diffused in said one surface of said n-region between adjacent ones of said plurality of said contact areas, each of said p regions having therein a V-groove gate contact extending into said n-region,
9. A switch according to ciaimX8, wherein said V-groove gate contact includes a V-shaped groove extending from the outer surface of said p region into said n-region, a layer of a semiconductor oxide disposed to coat the surface of said V-shaped groove and a metal contact layer covering said semiconductor oxide layer.
10. A switch according to claim 9, wherein said semiconductor oxide is silicon oxide,
11. A switch according to any one of the preceding claims wherein said n+ region includes a n+ type semiconductor area - 14 - I 198035 diffused in said p region remote from said n-region extending from side of said first V-shaped groove.
12. A switch according to any one of claims 7 to 10 or according to claim 11 as appended to any one of claims 7 to 10, wherein each of said plurality of contact areas have a metal surface source contact disposed thereon.
13. A switch according to claim 11 or claim 12 as appended' to claim 11, wherein each of said n+ areas have a metal surface source contact disposed thereon.
14. A switch according to any one of claims 8 to 10 or claim 12, or claim 13, or claim 11 as appended to any one of claims 8 to 10, wherein each of said plurality of contact areas have a V-groove metal source contact disposed therein.
15. A switch according to any of claims 1 to 3 wherein said MOS transistor has a DMOS configuration.
16. A switch according to claim 15, wherein said first p+ region includes a first p+ type semiconductor diffusion contact area in one surface of said n-region, and said second p+ region includes a second p+ type semiconductor diffusion contact area in said one surface of said n- region spaced from said first contact area.
17. A switch according to claim 15 or 16 wherein: said p region includes a p type semiconductor diffusion contact area in said one surface of said n- region adjacent the side of that one of said first and second p+ contact areas providing said collector remote from the other of said first and second p+ contact areas.
18. A switch according to any one of claims 15 to 17 wherein: said n+ region includes an n+ type semiconductor contact.
19. A switch according to any one of claims 15 to 18 wherein: each of said contact areas include on the surface thereof a metallic contact, given ones of said metallic contacts having at least one field plate connected thereto to enhance voltage breakdown.
20. A VMOS high voltage semiconductor switch as herein described with reference to Figures 1 to 3 of the accompanying drawings.
21. A DMOS high voltage semiconductor switch as herein described with reference to Figures 4 and 5 of the accompanying drawings. INTERNATIONAI ~ 'RIC CORPORATION 0 P. M. CONRICK Authorized Agent 5/1/1053 1 4AUGt98( 16 RECEIVED
NZ19803581A 1980-08-25 1981-08-14 Integrated bipolar-mos switch NZ198035A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US18129080A 1980-08-25 1980-08-25

Publications (1)

Publication Number Publication Date
NZ198035A true NZ198035A (en) 1986-04-11

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EP (1) EP0047392B1 (en)
JP (1) JPS5772365A (en)
AU (1) AU547356B2 (en)
BR (1) BR8105277A (en)
DE (1) DE3175641D1 (en)
ES (1) ES8301391A1 (en)
NZ (1) NZ198035A (en)

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US5072266A (en) 1988-12-27 1991-12-10 Siliconix Incorporated Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
EP1291924A1 (en) 2001-09-10 2003-03-12 STMicroelectronics S.r.l. MOS semiconductor device having a body region
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JPS5772365A (en) 1982-05-06
ES504914A0 (en) 1982-12-01
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EP0047392B1 (en) 1986-11-20
EP0047392A3 (en) 1983-07-20
BR8105277A (en) 1982-04-27
EP0047392A2 (en) 1982-03-17
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DE3175641D1 (en) 1987-01-08
ES8301391A1 (en) 1982-12-01

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