NO320176B1 - Stacked layers of grid memory connected to integrated circuit. - Google Patents
Stacked layers of grid memory connected to integrated circuit. Download PDFInfo
- Publication number
- NO320176B1 NO320176B1 NO20040502A NO20040502A NO320176B1 NO 320176 B1 NO320176 B1 NO 320176B1 NO 20040502 A NO20040502 A NO 20040502A NO 20040502 A NO20040502 A NO 20040502A NO 320176 B1 NO320176 B1 NO 320176B1
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- Prior art keywords
- stack
- grid
- memory
- integrated circuit
- layers
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- 230000015654 memory Effects 0.000 title claims description 47
- 239000010409 thin film Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 5
- 239000004020 conductor Substances 0.000 description 23
- 238000012937 correction Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 208000000044 Amnesia Diseases 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000002322 conducting polymer Substances 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 231100000863 loss of memory Toxicity 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 229920006255 plastic film Polymers 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
- H10K19/202—Integrated devices comprising a common active layer
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
Description
OPPFINNELSENS RELASJONER THE RELATIONS OF THE INVENTION
Foreliggende oppfinnelse angår kobling av ledere, elektroniske ikke-flyktige minner, og tynnfilms minner. The present invention relates to the connection of conductors, electronic non-volatile memories, and thin film memories.
OPPFINNELSENS BAKGRUNN BACKGROUND OF THE INVENTION
Formålet med denne oppfinnelsen er å gi en billig og enkel måte å effektivt fabrikere 3-dimensjonelt minne, gjerne massivt 3D minne. The purpose of this invention is to provide a cheap and simple way to efficiently manufacture 3-dimensional memory, preferably massive 3D memory.
Moderne minne er typisk 2 dimensjonale objekter som består av noen få lag, som f.eks. integrerte kretser som produseres i en lag-prosess, eller som stabler av 2 sidige magnetiske plater, eller som 2 lags DVD med et transparant lag. En åpenbar måte å lage større minne på er å øke antallet lag, men dette introduserer mange praktiske problemer. Å produser integrerte kretser med flere lag resulterer i økt prosesskompleksitet og økt feilrate, grunnet den nødvendige presisjonen og flere steg i en allerede kompleks produksjonsprosess. For magnetiske og optiske plater er det et problem at alle lagene krever hvert sitt store, dyre, og kompliserte lese/skrive-hode. For holografiske minner er det problemer med deformering av materialet. Modern memory is typically 2 dimensional objects consisting of a few layers, such as e.g. integrated circuits produced in a layer process, or as stacks of 2-sided magnetic discs, or as 2-layer DVD with a transparent layer. An obvious way to make larger memory is to increase the number of layers, but this introduces many practical problems. Producing integrated circuits with multiple layers results in increased process complexity and an increased error rate, due to the required precision and multiple steps in an already complex manufacturing process. For magnetic and optical discs, it is a problem that all the layers each require a large, expensive and complicated read/write head. For holographic memories there are problems with deformation of the material.
Et tidligere eksempel på måter å koble minner i lag, er US-6,376,904, som er assignert Rambus Inc, et firma kjent for minneteknologi. Dette patentet dreier seg om stablede sammenkoblede integrerte kretser, som kan være minner. Ulemper med dette er at integrerte kretser vanligvis er mere kompliserte og dyrere enn minner behøver å være, f.eks. i form av enkle matriser på tynn film. Sammenkoblingen mellom de integrerte kretsene krever også presisjon og nøyaktighet i form av presist monterte ledninger, flytlodding, eller film med kontakter. Ingen av disse sammenkoblingene er mikroskopiske. An earlier example of ways to connect memories in layers is US-6,376,904, which is assigned to Rambus Inc, a company known for memory technology. This patent concerns stacked interconnected integrated circuits, which can be memories. Disadvantages of this are that integrated circuits are usually more complicated and more expensive than memories need to be, e.g. in the form of simple arrays on thin film. The connection between the integrated circuits also requires precision and accuracy in the form of precisely fitted wires, flux soldering, or film with contacts. None of these interconnections are microscopic.
Det har vært eksperimentert med produksjon av 3-dimensjonale minner ved å stable lag av minner laget av elektronikk på tynn film, som i den Norske søknaden NO-20001360, der lagene er koblet sammen ved å stable dem meget presist i en pyramide, slik at kontaktene på endetappene sammenfaller, og kan kobles sammen. Patentet påstår at denne gjør viaer, ledende hull i lagene, unødvendige. På tiden ved innleveringen av denne patentsøknaden her, rapporteres det at firmaet som har patentet over, Thin Film Electronics, har problemer med å få til mere enn 8 lag. There have been experiments with the production of 3-dimensional memories by stacking layers of memories made of electronics on thin film, as in the Norwegian application NO-20001360, where the layers are connected by stacking them very precisely in a pyramid, so that the contacts on the end pins coincide, and can be connected together. The patent claims that this makes vias, conductive holes in the layers, unnecessary. At the time of the filing of this patent application here, it is reported that the company that holds the above patent, Thin Film Electronics, is having trouble getting more than 8 layers.
Et par store problemer ved stabling av mange lag av tynnfilm med minne og elektronikk, er at det til sammen blir mange feil i elektronikken, og at det blir posisjoneringsproblemer for koblingene mellom lagene. Hvis den kompliserte elektronikken fjernes ved å bruke enklere gitterminne, så blir problemet med skadet elektronikk mindre. Dog, det å koble presist sammen millioner til milliarder av kontakter på endetapper på gitterminner fra forskjellige lag av tynnfilm, med mulige variasjoner i tykkelse og avstand mellom endetappene, virker som en umulig oppgave. A couple of major problems when stacking many layers of thin film with memory and electronics are that there will be many errors in the electronics altogether, and that there will be positioning problems for the connections between the layers. If the complicated electronics are removed by using simpler lattice memory, then the problem of damaged electronics is reduced. However, precisely connecting millions to billions of contacts on end pins on grid elements from different layers of thin film, with possible variations in thickness and distance between the end pins, seems like an impossible task.
BAKGRUNN FOR OPPFINNELSEN, OG FORDELER BACKGROUND OF THE INVENTION AND BENEFITS
Noen tekniske effekter ved eksemplet på utførelse av foreliggende oppfinnelse er: (a) Gitterminnene kan enkelt stables, uten mellomforbindelser. Ingen sammenkoblede endetapper som i det tidligere patentet. (b) Høy presisjon er ikke nødvendig i produksjonen av tynnfilms gitterminner. Gitteret kan være ujevnt, ha variabel tykkelse, ha kutt og kortslutninger, og være vridd og bøyd. Tynnfilms gitterminner kan ha variabel filmtykkelse, og ikke-rektangulært tverrsnitt av gitterledningene. Alt forutsatt at gitterminnene fortsatt kan bli stablet, og at feilene ikke er for overveldende. (c) Gitterminner er enkle systemer. Mye enklere enn de fleste integrerte kretser. De kan mangle kompleks elektronisk logikk. Dette gjør deres produksjon enklere, og således billigere. (d) Koblingen av millioner til milliarder av ledere fra gitterminner, er forenklet til festing av endetapper i en kuttet flate i en stabel av gitterminner, til overflate-kontaktene på en integrert krets, slik at det blir elektrisk kontakt. Dette omtales i patentkravene 1 og 4. Altså kobling av lederne i kuttet, til kretsen. (e) Alle kontrollkretser og kretser for feilkorreksjon har tilgang gjennom, eller er integrert inn i, den integrerte kretsen. (f) Det er mulig å lage massive minner ved å bruke store, eller flere, stabler av gitterminner, koblet til en eller flere integrerte kretser. Man kan forestille seg en liter med minne, som ligger som en stor kile på en hel vaffel av useparerte integrerte kretser, som lagrer 1 bit per gitterkryss, og som har 1 um avstand mellom dem, ville gi 100 000 GB i lagringskapasitet. (g) Stablingen av tynnfilms gitterminner, de omtales i patentkrav 3, kan gjøres industrielt ved å rulle filmen opp og kutte den opp i de nødvendige kileformene, eller andre former med et diagonalt kutt. Den svake krumningen som dette gir til stabelen, er ikke et problem for posisjoneringen. (h) Termisk ekspansjon og mekaniske belastninger kan minkes ved at stabelen er bøyd og forskjøvet. Dette reduserer behovet for å ha materialer med samme termiske ekspansjons-koeffisient. (i) Pris. Dette minnet bør være billig å produsere. Kostnaden bør være sammenlignbar med en enkelt integrert krets. Some technical effects of the example of implementation of the present invention are: (a) The lattice modules can be easily stacked, without intermediate connections. No interlocking end pins as in the earlier patent. (b) High precision is not required in the production of thin film gratings. The grid can be uneven, have variable thickness, have cuts and shorts, and be twisted and bent. Thin-film grid memories can have variable film thickness, and non-rectangular cross-section of the grid wires. All assuming the grid mines can still be stacked and the errors aren't too overwhelming. (c) Lattice memories are simple systems. Much simpler than most integrated circuits. They may lack complex electronic logic. This makes their production easier, and thus cheaper. (d) The connection of millions to billions of conductors from grid terminals is simplified to the attachment of end pins in a cut surface in a stack of grid terminals to the surface contacts of an integrated circuit, so that electrical contact is made. This is referred to in patent claims 1 and 4. That is, connection of the conductors in the cut to the circuit. (e) All control and error correction circuits are accessed through, or integrated into, the integrated circuit. (f) It is possible to make massive memories by using large, or several, stacks of lattice memories, connected to one or more integrated circuits. One can imagine a liter of memory, located as a large wedge on a whole wafer of unseparated integrated circuits, storing 1 bit per grid junction, and having 1 µm spacing between them, would provide 100,000 GB of storage capacity. (g) The stacking of thin-film gratings, they are referred to in patent claim 3, can be done industrially by rolling up the film and cutting it into the necessary wedge shapes, or other shapes with a diagonal cut. The slight curvature that this gives to the stack is not a problem for positioning. (h) Thermal expansion and mechanical loads can be reduced by bending and shifting the stack. This reduces the need to have materials with the same thermal expansion coefficient. (i) Price. This memory should be cheap to produce. The cost should be comparable to a single integrated circuit.
Videre fordeler vil være åpenbare utifrå en gjennomtenking av følgende beskrivelse og tegninger. Further advantages will be obvious from a consideration of the following description and drawings.
SAMMENDRAG SUMMARY
3 dimensjonelt elektronisk minne som består av stablede tynne lag (Fig 4) med gitter-minne, der gitrene er kuttet diagonalt (12)(Fig 1) slik at gitterledningene (13) kobles til overflaten på en integrert krets (14)(Fig 2). 3 dimensional electronic memory consisting of stacked thin layers (Fig 4) with lattice memory, where the lattices are cut diagonally (12)(Fig 1) so that the lattice wires (13) are connected to the surface of an integrated circuit (14) (Fig 2) ).
TEGNINGER—FIGURER DRAWINGS—FIGURES
Tegningene er ikke i skala, siden det ikke er noen foretrukket skala. FIG 1 er et perspektivbilde av en diagonalt kuttet stabel av gitterminner. Kuttet er synlig nedenfor det fremste laget. FIG 2 er et perspektivbilde av den kuttede stabelen av gitterminne, koblet til en integrert krets. FIG 3 viser grensesnittet mellom den integrerte kretsen og de kuttede gitterminnene. Kontaktene på den integrerte kretsen er representert som enkle firkanter for å gjøre figuren visuelt forståelig. Grensesnittet er ganske rotete. FIG 4 viser ett lag av kuttet gitterminne. The drawings are not to scale, as there is no preferred scale. FIG 1 is a perspective view of a diagonally cut stack of lattice blocks. The cut is visible below the top layer. FIG 2 is a perspective view of the cut stack of lattice memory connected to an integrated circuit. FIG 3 shows the interface between the integrated circuit and the cut gratings. The contacts of the integrated circuit are represented as simple squares to make the figure visually understandable. The interface is quite messy. FIG 4 shows one layer of cut lattice memory.
TEGNINGER—REFERANSENUMRE DRAWINGS—REFERENCE NUMBERS
10 Det fremste laget av gitterminne i stabelen. 10 The top layer of lattice memory in the stack.
11 Et kryssningspunkt for 2 forskjellige ledere i et gitterminne. 12 Det diagonale kuttet i stabelen. Alle gitterkuttene er synlige. 11 A crossing point for 2 different conductors in a grid memory. 12 The diagonal cut in the stack. All grid cuts are visible.
13 En kuttet leder i det diagonale kuttet. 13 A cut conductor in the diagonal cut.
14 En integrert krets. 14 An integrated circuit.
15 En kontakt på den integrerte kretsen. 15 A contact on the integrated circuit.
16 En side på stabelen, ikke det diagonale kuttet. Bare enden på halvparten av lederne i gitteret er synlige. 16 One side of the stack, not the diagonal cut. Only the ends of half of the conductors in the grid are visible.
DETALJERT BESKRIVELSE—FIG2 -FORETRUKKET FORM (s) DETAILED DESCRIPTION—FIG. 2 - PREFERRED EMBODIMENT(s)
Gitterminner består av rader av elektriske ledere i ett lag, og kolonner i et annet lag, slik at lederne i det ene laget krysser nær lederne i det andre laget. Mellom disse lagene er det mange forskjellige løsninger for å lagre data, som f.eks. Organiske sikringer, lysende og variabelt ledende polymerer, PN halvleder overganger, etc. Det eneste denne oppfinnelsen krever er at lederne er aksesserbart via gitteret, som kan være ujevnt, ha feil, og vinklet anderledes enn 90 grader. Et eksempel på en annen vinkel er 60 grader, som forekommer i heksagonal pakking, som muliggjør tettere pakking av lysende områder i lysende gitterminne. Grid memories consist of rows of electrical conductors in one layer, and columns in another layer, so that the conductors in one layer cross close to the conductors in the other layer. Between these layers there are many different solutions for storing data, such as e.g. Organic fuses, luminous and variably conducting polymers, PN semiconductor transitions, etc. The only thing this invention requires is that the conductors are accessible via the grid, which can be uneven, have errors, and angled differently than 90 degrees. An example of another angle is 60 degrees, which occurs in hexagonal packing, which enables tighter packing of luminous regions in luminous lattice memory.
En foretrukket form av foreliggende oppfinnelse, er i form av tynn film laget av spesiell plast, slik som i patentkrav 3. Denne tynne filmen har ledere trykket på hver side, slik at de krysser, og således danner et gitter. Denne tynne filmen stables i lag med isolerende lag imellom, og rulles sammen til en rull. Denne rullen kuttes omtrentlig langs lederne, i biter. Disse bitene blir igjen kuttet (12) diagonalt i forhold til gitteret, som i patentkrav 4, slik at det oppnås en kileform, som i Fig 1. Kilen er koblet unøyaktig til den integrerte kretsen (14), langs det diagonale kuttet, som i Fig 2, og patentkrav 1. Denne koblingen gjør at lederne i gitteret (13) kobles ledende sammen med kontaktene på den integrerte kretsen (15), slik at det blir et rotete mønster av elektriske koblinger, som i Fig 3. A preferred form of the present invention is in the form of a thin film made of special plastic, as in patent claim 3. This thin film has conductors printed on each side, so that they cross, thus forming a grid. This thin film is stacked in layers with insulating layers in between, and rolled up into a roll. This roll is cut roughly along the conductors, into pieces. These pieces are again cut (12) diagonally in relation to the grid, as in patent claim 4, so that a wedge shape is obtained, as in Fig 1. The wedge is connected inaccurately to the integrated circuit (14), along the diagonal cut, as in Fig 2, and patent claim 1. This connection means that the conductors in the grid (13) are conductively connected together with the contacts on the integrated circuit (15), so that there is a messy pattern of electrical connections, as in Fig 3.
Alternative Former Alternative Forms
Det kan også være en fordel med heksagonale kontakter på den integrerte kretsen. Størrelsen og avstanden mellom tappene er ikke spesifisert, ettersom de er avhengige av de fysiske størrelsene på lederne. Heller ikke tappenes areal er spesifisert. En blant flere faktorer som kan justeres, er sannsynligheten for at 2 eller flere ledere i gitteret kobles til 1 eller flere kontakter på kretsen. Som vist i Fig 4, behøver ikke en unøyaktig dobbel kobling resultere i noe problem, bare en "W" lignende krysning av ledere i stedet for en vanlig "X" lignende krysning. It can also be an advantage to have hexagonal contacts on the integrated circuit. The size and distance between the pins are not specified, as they depend on the physical sizes of the conductors. Nor is the area of the studs specified. One of several factors that can be adjusted is the probability that 2 or more conductors in the grid connect to 1 or more contacts on the circuit. As shown in Fig 4, an inaccurate double connection need not result in any problem, just a "W" like crossing of conductors instead of a normal "X" like crossing.
Lagene med ledere behøver ikke være så tynne og fleksible som tynn plastfilm. The layers of conductors do not have to be as thin and flexible as thin plastic film.
Å la lagene med ledere krysse flere integrerte kretser er en åpenbar mulighet, såvel som å ha flere stabler av lag på en krets. Having the layers of conductors cross multiple integrated circuits is an obvious possibility, as well as having multiple stacks of layers on a circuit.
Det er mulig å kutte vekk toppen av kilen av lag, slik at den blir flatere, slik at den får plass i flatere* forpakninger. Dette innebærer noe tap av minne, spesielt hvis stabelen er kuttet kvadratisk. It is possible to cut away the top of the wedge of layers, so that it becomes flatter, so that it fits in flatter* packages. This involves some loss of memory, especially if the stack is cut square.
VIRKEMÅTE. MODE OF OPERATION.
Måten å bruke dette minnet på, som består av lag meda gitterminner, er ved å aksessere lagene av gitterminne via den integrerte kretsen. For å aksessere minnene er det nødvendig med multipleksede forbindelser til lederne i gitrene. For å oppnå disse forbindelsene er stabelen av gitterminne kuttet diagonalt, slik at lederne i stabelen er tilgjengelige på en plan side. Denne sideflaten er så koblet til overflaten på en integrert krets for å gi nødvendig multipleksing og muligheten av nødvendig feilretting og nødvendig tilpasning til de rotete koblingene mellom kontakt-punktene på kretsen og gitrene. The way to use this memory, which consists of layers of lattice memories, is by accessing the layers of lattice memory via the integrated circuit. To access the memories, multiplexed connections to the conductors in the grids are required. To achieve these connections, the stack of grid memory is cut diagonally, so that the conductors in the stack are accessible on a flat side. This side surface is then connected to the surface of an integrated circuit to provide the necessary multiplexing and the possibility of necessary error correction and necessary adaptation to the messy connections between the contact points of the circuit and the grids.
For å aksessere et enkelt minne-element i et gitterkryss 11 (Fig 4), aktiverer den integrerte kretsen tappene 15 (Fig 4) koblet til lederne i gitteret som krysser hverandre i minne-element 11 (Fig 4). Dette er hovedprinsippet for virkemåten. Den integrerte kretsen kan således betraktes som en multiplekser som brukes til å aksessere lederne i stabelen av lag med gitterminner. To access a single memory element in a grid junction 11 (Fig 4), the integrated circuit activates the pins 15 (Fig 4) connected to the conductors in the grid which cross each other in memory element 11 (Fig 4). This is the main principle of operation. The integrated circuit can thus be thought of as a multiplexer used to access the conductors in the stack of layers of grid memories.
Det er 2 overlappende strategier for systematisk aksess av minnet. Et kart av forbindelsene i Fig 3 kan bli lagd ved å måle den elektriske oppførselen mellom nabotapper for å undersøke om de er koblet til kryssende ledere i gitteret. Dette kartet kan bli brukt til å systematisere tilgjengelige minne-enheter. Den andre strategien er å unngå- kartet, og i stedet måle ved hver aksess, og bruke hashe-teknikker for å gi illusjonen av et ordnet minne. I begge tilfellene må feilrettende metoder brukes. Dette er kjent kunnskap i design av harddisker og feilrettingskoder. There are 2 overlapping strategies for systematic memory access. A map of the connections in Fig 3 can be made by measuring the electrical behavior between neighboring pins to investigate whether they are connected to crossing conductors in the grid. This map can be used to systematize available memory units. The other strategy is to avoid the map, and instead measure at each access, and use hashing techniques to give the illusion of an ordered memory. In both cases, error-correcting methods must be used. This is known knowledge in the design of hard drives and error correction codes.
KONKLUSJON OG KONSEKVENSER. CONCLUSION AND CONSEQUENCES.
Og således vil leseren kunne se at denne oppfinnelsen kan brukes til å lage 3-dimensjonelle minner effektivt og billig. And thus the reader will be able to see that this invention can be used to make 3-dimensional memories efficiently and cheaply.
Claims (4)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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NO20040502A NO320176B1 (en) | 2004-02-03 | 2004-02-03 | Stacked layers of grid memory connected to integrated circuit. |
PCT/NO2005/000027 WO2005076356A1 (en) | 2004-02-03 | 2005-01-24 | Layered crossbar memory connected to integrated circuit |
EP05704640A EP1719177A1 (en) | 2004-02-03 | 2005-01-24 | Layered crossbar memory connected to integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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NO20040502A NO320176B1 (en) | 2004-02-03 | 2004-02-03 | Stacked layers of grid memory connected to integrated circuit. |
Publications (2)
Publication Number | Publication Date |
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NO20040502L NO20040502L (en) | 2005-08-04 |
NO320176B1 true NO320176B1 (en) | 2005-11-07 |
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NO20040502A NO320176B1 (en) | 2004-02-03 | 2004-02-03 | Stacked layers of grid memory connected to integrated circuit. |
Country Status (3)
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EP (1) | EP1719177A1 (en) |
NO (1) | NO320176B1 (en) |
WO (1) | WO2005076356A1 (en) |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6021074A (en) * | 1998-09-04 | 2000-02-01 | Advanced Micro Devices, Inc. | Direct access to random redundant logic gates by using multiple short addresses |
US6376904B1 (en) * | 1999-12-23 | 2002-04-23 | Rambus Inc. | Redistributed bond pads in stacked integrated circuit die package |
NO20001360D0 (en) * | 2000-03-15 | 2000-03-15 | Thin Film Electronics Asa | Vertical electrical connections in stack |
NO315728B1 (en) * | 2000-03-22 | 2003-10-13 | Thin Film Electronics Asa | Multidimensional addressing architecture for electronic devices |
-
2004
- 2004-02-03 NO NO20040502A patent/NO320176B1/en not_active IP Right Cessation
-
2005
- 2005-01-24 WO PCT/NO2005/000027 patent/WO2005076356A1/en active Application Filing
- 2005-01-24 EP EP05704640A patent/EP1719177A1/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
WO2005076356B1 (en) | 2005-10-06 |
EP1719177A1 (en) | 2006-11-08 |
NO20040502L (en) | 2005-08-04 |
WO2005076356A1 (en) | 2005-08-18 |
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