NL151213B - Werkwijze voor het vervaardigen van een planaire halfgeleiderinrichting, voorzien van een vrijwel uitsluitend uit palladium bestaande laag, alsmede de aldus vervaardigde halfgeleiderinrichting. - Google Patents

Werkwijze voor het vervaardigen van een planaire halfgeleiderinrichting, voorzien van een vrijwel uitsluitend uit palladium bestaande laag, alsmede de aldus vervaardigde halfgeleiderinrichting.

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Publication number
NL151213B
NL151213B NL696908469A NL6908469A NL151213B NL 151213 B NL151213 B NL 151213B NL 696908469 A NL696908469 A NL 696908469A NL 6908469 A NL6908469 A NL 6908469A NL 151213 B NL151213 B NL 151213B
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Netherlands
Prior art keywords
palladium
semi
procedure
manufacture
semiconductor device
Prior art date
Application number
NL696908469A
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English (en)
Other versions
NL6908469A (nl
Original Assignee
Matsushita Electronics Corp
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Filing date
Publication date
Priority claimed from JP3925268A external-priority patent/JPS4830785B1/ja
Priority claimed from JP43057739A external-priority patent/JPS4915381B1/ja
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Publication of NL6908469A publication Critical patent/NL6908469A/xx
Publication of NL151213B publication Critical patent/NL151213B/nl

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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B01PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01032Germanium [Ge]
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    • H01L2924/01Chemical elements
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01042Molybdenum [Mo]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01068Erbium [Er]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12032Schottky diode
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24851Intermediate layer is discontinuous or differential
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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NL696908469A 1968-06-05 1969-06-04 Werkwijze voor het vervaardigen van een planaire halfgeleiderinrichting, voorzien van een vrijwel uitsluitend uit palladium bestaande laag, alsmede de aldus vervaardigde halfgeleiderinrichting. NL151213B (nl)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP3925268A JPS4830785B1 (nl) 1968-06-05 1968-06-05
JP43057739A JPS4915381B1 (nl) 1968-08-12 1968-08-12
JP5773868 1968-08-12

Publications (2)

Publication Number Publication Date
NL6908469A NL6908469A (nl) 1969-12-09
NL151213B true NL151213B (nl) 1976-10-15

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NL696908469A NL151213B (nl) 1968-06-05 1969-06-04 Werkwijze voor het vervaardigen van een planaire halfgeleiderinrichting, voorzien van een vrijwel uitsluitend uit palladium bestaande laag, alsmede de aldus vervaardigde halfgeleiderinrichting.

Country Status (5)

Country Link
US (1) US3642528A (nl)
DE (1) DE1927646C3 (nl)
FR (1) FR2010192B1 (nl)
GB (1) GB1263980A (nl)
NL (1) NL151213B (nl)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1348811A (en) * 1970-11-27 1974-03-27 Siemens Ag Production of schottky contacts
DE2207012C2 (de) * 1972-02-15 1985-10-31 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Kontaktierung von Halbleiterbauelementen
FR2188304B1 (nl) * 1972-06-15 1977-07-22 Commissariat Energie Atomique
US3931492A (en) * 1972-06-19 1976-01-06 Nippon Telegraph And Telephone Public Corporation Thermal print head
DE2237616C3 (de) * 1972-07-31 1982-09-16 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum Einschmelzen eines Halbleiterelements in ein Glasgehäuse
US3900344A (en) * 1973-03-23 1975-08-19 Ibm Novel integratable schottky barrier structure and method for the fabrication thereof
US3839111A (en) * 1973-08-20 1974-10-01 Rca Corp Method of etching silicon oxide to produce a tapered edge thereon
US3896479A (en) * 1973-09-24 1975-07-22 Bell Telephone Labor Inc Reduced stresses in iii-v semiconductor devices
NL7415841A (nl) * 1974-12-05 1976-06-09 Philips Nv Werkwijze voor het vervaardigen van een half- geleiderinrichting en halfgeleiderinrichting, vervaardigd volgens de werkwijze.
JP2730357B2 (ja) * 1991-11-18 1998-03-25 松下電器産業株式会社 電子部品実装接続体およびその製造方法
DE19828846C2 (de) * 1998-06-27 2001-01-18 Micronas Gmbh Verfahren zum Beschichten eines Substrats
JP2007059704A (ja) * 2005-08-25 2007-03-08 Sumco Corp 貼合せ基板の製造方法及び貼合せ基板
US20100301467A1 (en) * 2009-05-26 2010-12-02 Albert Wu Wirebond structures
JP5532743B2 (ja) * 2009-08-20 2014-06-25 三菱電機株式会社 半導体装置及びその製造方法
DE102013108661A1 (de) * 2013-08-09 2015-02-12 Osram Opto Semiconductors Gmbh Verfahren zur Strukturierung und Planarisierung einer Schichtenfolge

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1356197A (fr) * 1962-06-29 1964-03-20 Western Electric Co Contact de semiconducteur
NL294675A (nl) * 1962-06-29

Also Published As

Publication number Publication date
DE1927646A1 (de) 1970-01-08
GB1263980A (en) 1972-02-16
FR2010192B1 (nl) 1974-02-22
NL6908469A (nl) 1969-12-09
DE1927646B2 (de) 1973-02-15
FR2010192A1 (nl) 1970-02-13
US3642528A (en) 1972-02-15
DE1927646C3 (de) 1973-10-18

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